First-Level Cache

The KA650 includes a 1 Kbyte, two-way associative, write through first-level cache with a 90 ns cycle time. CPU read references access one longword at a time, while CPU writes can access one byte at a time.

A single parity bit is generated, stored, and checked for each byte of data and each tag. The first-level cache can be enabled/disabled by setting/clearing the appropriate bits in the CADR. The first-level cache is flushed by any write to the CADR, as long as it is not in diagnostic mode.

3.3.2.1 First-Level Cache Organization

The first-level cache is divided into two independent storage arrays called set 1 and set 2. Each set contains a 64 row by 22-bit tag array and a 64 row by 72-bit data array. The two sets are organized as shown in Figure 3-8.

Set 1 Set 2

64 ROWS

[~~4_ITb_t A_2~--I.

~_;"_71_~_~l_Y_...J

:---

93 72 71 a 93 72 71 o

MA-1103-S1

Figure 3-8 First-Level Cache Organization

A row within a set corresponds to a cache entry, so there are 64 entries in each set and a total of 128 entries in the entire cache. Each entry contains a 22-bit tag block and a 72-bit (eight-byte) data block. A cache entry is organized as shown in Figure 3-9.

93 72 71 o

TAG BLOCK DATA BLOCK

MA,·1104-87

Figure 3-9 First-Level Cache Entry

A tag block consists of a parity bit, a valid bit, and a 20-bit tag. A tag block is organized as shown in Figure 3-10.

IplV I

PARITY BIT

I I

VALID BIT 19

TAG

Figure 3-10 First-Level Cache Tag Block

o

MA·1105·S7

A data block consists of eight bytes of data, each with an associated parity bit. The total data capacity of the cache is 128 eight-byte blocks, or 1024 bytes. A data block is organized as shown in Figure 3-11.

_ _ DATA BITS

63 56 55 4ll 47 4039 32 31 2423 16 15 8 i 0

I

I

^{I pi}

I pi

Ipi

I

I

I

I

Ip I

H

^I

6 5 ⁴ a

- PARITY BITS

MA·'11()..87

Figure 3-11 First-Level Cache Data Block

3-36 Architecture

3.3.2.2 First-Level Cache Address Translation

Whenever the CPU requires an instruction or data, the contents of the first-level cache is checked to detennine if the referenced location is stored there. The cache contents is checked by translating the physical address as follows:

• On noncacheable references, the reference is never stored in the cache, so a first-level cache miss occurs and a single 10ngword reference is generated on the CDAL bus.

• On cacheable references, the physical address must be translated to detennine if the contents of the referenced location is resident in the cache. The cache index field, bits <8:3> of the physical address, is used to select one of the 64 rows of the cache, with each row containing a single entry from each set. The cache tag field, bits

<28:9> of the physical address, is then compared to the tag block of the entry from both sets in the selected row.

If a match occurs with the tag block of one of the set entries, and the valid bit within the entry is set, the contents of the referenced location is contained in the cache and a cache hit occurs. On a cache hit, the set match signals generated by the compare operation select the data block from the appropriate set. The cache displacement field, bits <2:0> of the physical address, is used to select the byte(s) within the block. No CDAL bus transfers are initiated on CPU references that hit the first-level cache.

If no match occurs, then the contents of the referenced location is not contained in the cache and a cache miss occurs. In this case, the data must be obtained from either the second-level cache, or the main memory controller, so a quadword transfer is initiated on the CDAL bus (Figure 3-12).

2928 9 8 3 2 0

1

1 ^I I

LIIOSPACE CACHE INDEX-1

CACHE DISPLACEMENT . . .

VAL; BIT VALID BIT

SET 1

+

2D- 64-BIT 2D- 64-BIT

BIT DATA BLOCK BIT DATA BLOCK

TAG TAG

~ "y,~,,",

SET 1 MATCH?

I

DATA

~

'-'A·"Q6.87

Figure 3-12 First-Level Cache Address Translation

3.3.2.3 First-Level Cache Data Block Allocation

Cacheable references that miss the first-level cache, cause a quadword read to be initiated on the CDAL bus. When the requested quadword is supplied by either the second-level cache or the main memory controller, the requested longword is passed on to the CPU, and a data block is allocated in the cache to store the entire quadword.

3-38 Architecture

Due to the fact that the cache is two-way associative, there are only two data blocks (one in each set) that can be allocated to a given quadword.

These two data blocks are determined by the cache index field of the address of the quad word, which selects a unique row within the cache.

Selection of a data block within the row (for example, set selection) for storing the new entry is random.

Since the KA650 supports 64 Mbytes (8 M quadwords) of physical memory, up to 128K quadwords share each row (two data blocks) of the cache. Contiguous programs larger than 512 bytes or any noncontiguous programs separated by 512 bytes have a 50 percent chance of overwriting themselves when cache data blocks are allocated for the first time for data separated by 512 bytes (one page). After six allocations, there is a 97 percent probability both sets in a row will be filled.

3.3.2.4 First-Level Cache Behavior on Writes

On CPU generated write references, the first-level cache is write through.

All CPU write references that hit the first-level cache cause the contents of the referenced location in main memory to be updated as well as the copy in the cache.

On DMA write references that hit the first-level cache, the cache entry containing the copy of the referenced location is invalidated. If the first-level cache is configured to store only I-stream references, then the entire first-level cache is also flushed whenever an REI instruction is executed.

(The VAX architecture requires that an REI instruction be executed before executing instructions out of a page of memory that has been updated.) 3.3.2.5 Cache Disable Register

The cache disable register (CADR), IPR 37, controls the first-level cache, and is unique to CPU designs that use the CVAX chip (Figure 3-13).

31 8 7 6 5 4 3 2 , 0

I

III 11 1[1J IJ