Interprocessor Communication Register

The interprocessor communication register (IPCR), address 2000 1F40 16,

is a IS-bit register which resides in the Q22-bus 110 page address space and can be accessed by any device which can become Q22-busmaster (including the KA650 itself). The IPCR, implemented in the CQBIC chip, is byte accessible, meaning that a write byte instruction can write to either the low or high byte without affecting the other byte.

The IPCR also appears at Q22"bus address 17 777 500 (Figure 3-38).

151413 9 8 7 6 5 4 1 0

11 I

UJJ I

^{I I}

DMA OME

I I

I

I

OMCIA RESERVED M8Z RESERVED LM EAE RESERVED

Figure 3-38 Interprocessor Communication Register

Data Bit Defurition

<15> DMA QME. DMA Q22-bus address space memory error.

<14>

<13:9>

Read/write to clear. Indicates that an error occurred when a Q22-bus device was attempting to read main memory.

It sets if DMA system error register bit DSER<4> (main memory error) sets, or the CDAL bus timer expires. The main memory error bit indicates that an uncorrectable error occurred when an external device (or CPU) was accessing the KA650 local memory.

The CDAL bus timer expiring indicates that the memory controller did not respond when the Q22-bus interface initiated a DMA transfer. Cleared by writing a 1 to it, on power-up by the negation of DCOK when the processor halts, by writes to IPR 55 (IORESET), and whenever DSER<4> clears.

Q22-bus invalidate all (QMCIA). Write only. Writing a 1 ^to this bit clears the Cam Valid bits in the cached copy of the map. Always reads as zero. Writing a 0 has no effect.

Unused. Read as zeros. Must be written as zeros.

Reserved for DIGITAL use.

Unused. Read as zero. Must be written as zero.

Reserved for DIGITAL use.

3-92 Architecture

Data Bit

<4:1>

Definition

Local memory external access enable (LM EAE). Read/write when the KA650 is Q22-bus master. Read only when another device is Q22-bus master. Enables external access to local memory when set <through the Q22-bus map).

Cleared on power-up and by the negation of DCOK when the processor halts.

Unused. Read as zeros. Must be written as zeros.

Reserved for DIGITAL use.

3.8.4 Q22-bus Interrupt Handling

The KA650 responds to interru.pt requests BR7-4 with the standard Q22-bus interru.pt acknowledge protocol (DIN followed by IAK). The console serial line unit, the programmable timers, and the interprocessor doorbell request interrupts at IPL 14 and have priority over all Q22-bus BR4 interru.pt requests. After responding to any interru.pt request BR7-4, the CPU sets the processor priority to IPL 17. All BR7-4 interrupt requests are disabled unless software lowers the interrupt priority level.

Interrupt requests from the KA650 interval timer are handled directly by the CPU. Interval timer interrupt requests have a higher priority than BR6 interrupt requests. Mter responding to an interval timer interrupt request, the CPU sets the processor priority to IPL 16. Thus, BR7 interrupt requests remain enabled.

3.8.5 Configuring the Q22-bus Map

The KA650 implements the Q22-bus map in an 8K longword (32 Kbytes) block of main memory. This map must be configured by the KA650 firmware during a processor initialization by writing the base address of the uppermost 32 Kbytes block of good main memory into the Q22-bus map base register. The base of this map must be located on a 32 Kbyte boundary.

NOTE

This 32 Kbyte block of main memory must be protected by the system software. The only access to the map should be through local JJO page addresses 2008 8000 ¹⁶ through 2008 FFFC ^16'

3.8.5.1 Q22·bus Map Base Address Register

The Q22-bus map base address register (QBMBR), address 20080010 16,

controls the main memory location in the 32 Kbyte block of Q22-bus map registers.

This read/write register is accessed by the CPU on a longword boundary only. Bits <31:29,14:0> are unused and should be written as zero and returns to zero when read.

A write to the map base register flushes the Q22-bus map cache by clearing the Cam Valid bits in all the entries.

The contents of this register are undefined on power-up and the negation of DCOK when the processor halts. It is not affected by BINIT being asserted on the Q22-bus (Figure 3-39).

31 29 28 15 14 o

I

I

Figure 3-39 Q22·bus Map Base Address Register

3.8.6 System Configuration Register

The system configuration register (SCR), address 2008 0000 16, contains a BHALT enable bit and a power ok flag.

The system configuration register (SCR) is longword, word, and byte accessible. Programmable option fields clear on power-up and by the negation of DCOK when the processor halts. The format of the SCR register is shown in Figure 3-40.

3-94 Architecture

;31 ~5 14 1;3 12 11 10 9 8 7 6 5 4 ;3 2 1 0

[

I I I

I I

I I

_I

POK BHALT ENB

I I

RESERVED

ACTION ON DCOK NEGA110N RESERVED

MUST BE ZERO

Figure 3-40 System Configuration Register

Data Bit Definition

<31:16> Unused. Read as zero. Must be written as zero.

<15> Power ok (POK). Read only. Writes have no effect. Set if the Q22-bus BPOK signal asserts and clears if it negates.

Cleared on power-up and by the negation of DCOK when the processor halts.

<14> BHALT enable (BHALT EN). Readlwrite. Controls the effect the Q22-bus BHALT signal has on the CPU. When set, asserting the Q22-bus BHALT signal halts the CPU and asserts DSER<15>. When cleared, the Q22-bus BHALT signal has no effect. Cleared on power-up and by the negation of DCOK when the processor halts.

<13:11> Unused. Read as zero. Must be written as zero.

<10> Reserved for DIGITAL use.

<9:8> Unused. Read as zero. Must be written as zero.

Data Bit

<6:4>

<3:1>

Definition

Action on DCOK negation. Read/write. When cleared, the Q22-bus interface asserts SYSRESET causing a hardware reset of the board and control to be passed to the resident firmware through the hardware halt procedure with a halt code of 3 when DCOK is negated on the Q22-bus. When set, the Q22-bus interface asserts HALTIN (causing control to be passed to the resident firmware through the hardware halt procedure with a halt code of 2) when DCOK is negated on the Q22-bus. Cleared on power-up and the negation of DCOK when the processor halts.

Unused. Read as zero. Must be written as zero.

Reserved for DIGITAL use.

Unused. Read as

o.