L Row 8;t Even L,,,h - This manual is intended for internal use only and may not

"'1J

(")

:::r

(")

:::r

en :::r B

=t; r-+

:0 C"D c.o (ii' r-+

C"D

"""I Ul

c

o

4-108 3B Punch Cycle

E

3 •

1---

: : 0

-I

Rd 1 Row Bit Odd Latch Rd 1 Row Bit Even Latch (Not) 51 Col Feed Ctrl

I

4 5 6

70ns

.. 80 RP Sh;ft Ad,

V-J

⁵⁵

^I ^~

RP Sh;ft Ad.,nc" SS _ 4-1014A Time 2 2 5 - 3 0 0 - - l ] I

~

^{.. 6D}

RU016

Rd1RowBit~

4-1033B Read Cycle A OR PFR·Rd1 Shift G a t e - - - t

1 - 1 - - - - PFR Rd Row Bit

~0~

RT016

7 8

* Note: Position 8 is reset on, all others off;

therefore the EaR position turns on by the eigth advance pulse. This signals that the shift register is fu II.

t---

(Not) Col 8 Rd1-PFR Data In

~ (Not) Col 7 Rd1-PFR Data In

f---

(Not) Col 6 Rd1-PFR Data In PFR Row Bit Odd Latch

L Row 8;t Even L,,,h

- - - I

^{Rd1-PF R}

6~6

5- / 5 4J1' /4 3J1'/3 2

JI'

f - -

(Not) Col 5 Rd1-PFR Data In f--- (Not) Col 4 Rd1-PFR Data In

~ (Not) Col 3 Rd1·PFR Data In

~ (Not) Col 2 Rd1-PFR Data In

4-43 7D (RP-1) 4-1039C Reader Micro Shift L a t - - - - i

4-101 5C (Not) Diagnostic Single Cycle 4-1037C Reader Shift Adv L a t - - - i 4-1014A Time 4 5 0 - 5 2 5 - - - i 4-1034B (Not) Read Cycle - - - t 4-103 6B Reader Select Lat - - - f 4-1037 A (Block Advance)

4-1014A Time 375-450

- - - 1

Sh ift Register

Output line is active when the bit latch is off.

1 / 1 ~ (Not) Col 1 Rd1-PFR Data In

EaR ~ EaR Rd1 or P F R - -... --4-102 2A. 7D; 4-105 3C; 4-108 6D

~~ (8-EOR) RU033-037

4-108 9C Sh ift Advance Pch Latch ^{H t - - -}Reset R-P Shift R e g - - - ' * Th is 0 R is shown each place it is used (4-103 6D; 4-108 7D)

4-101 5D (Not) RP Diagnostic Lat 4-1086C Punch Micro L a t - - - I 4-1014A Time 4 5 0 - 5 2 5 - - - - -... --1 4-1089A Delta Pch Scan L a t - - - f 4-1087B Punch Select L a t - - - I 4-101 8D Diagnsotic Reset S h i f t - - - 1 4-101 48 Interegrated Rdr Pch Reset - - - I

RT015, 16,21

'--_ _ .. 6E; 4-111 5B

4-1037 A

End of Byte Record .. 7E EaR Rd2 or Pch Chk

4-1092A A N (Not) Block Rdr Advance - - - 4 ... - - 1

9

4-1036B

(Block A d v a n c = 8 - B - )

Reader Select 4·1037C Reader Shift Adv Lat A

RT015 Shift Advance Pch L a t - - - f OR RP Shift Adv .. 5A

I-~'--l

I _{::~ :} ::: :n L~:t',hh =§j ... --tl----

Rd2 Row Bit

----..r-,r-,

INotl 51 Col Feed C'"

I

4·10338 Re,d Cycle Pch Chk Row Bit Odd Latch

Pch Chk Row Bit Even Latch

i---+---Pch Chk Row Bit

RT016

A RT015

4-1089C

Delta Pch Scan L a t : E } 8

-A N (Not) Block Pch Advance - - - . - - - 4-109 2A

Sh ift Advance Pch Lat 4-111 2A

4-1089A

.. 6A RP Shift Advance SS

Pch-Chk Rd2 Shift Gate---1

Rd2-Pch Chk Sh ift Register

.. 5C Reset R-P Shift Reg

RT021

I - - -

(Not) Col 8 Rd2-Pch-Chk Data In

1---

(Not) Col 7 Rd2-Pch-Chk Data In

~-(Not) Col 6 Rd2-Pch-Chk Data In

I - - -

(Not) Col 5 Rd2-Pch-Chk Data In

~ (Not) Col 4 Rd2-Pch-Chk Data In

I - - -

(Not) Col 3 Rd2-Pch-CH Data In

~ (Not) Col 2 Rd2-Pch-Chk Data In

t - - -

(Not) Call Rd2-Pch-Chk Data In

4-437C (RP-2) Output line is active when the bit latch is off.

I - - -

EaR Rd2 or Pch Chk .. 7C; 4-102 2A; 4-105 3C (Active)

(S-EOR) RU038-041

a

N tn '"T1

m

0 -...

0 0)

... fa'

...

""'C C

~ (")

o

([) (")

o

([) (J)

=h .-+

:0 ([)

to :0 0.

:j 3

to ::J

"

4-108 9C Shift Advance Pch L a t = = E } - 70ns

A Pch Advance R-P Shift

'4-110 7D (Not) Block Pch Advance

~

RT021

4-1014ATimeOOO-075~

4-l4 3D 2540 Mode RU016 RU016

Pch Advance Decode 5 5 - - - , Punc h Decode Shift Register

•

*Note: The decode position is reset off; all other positions ore set on or off by the bit condition of the Ext 8us Out. If bit position 1 is on, the decode latch is turned off on the next advance and the Punch Decode signal is inactive.

4-1004A Ext A5 Field Decode F - - - - i

4-100 4D Gate CPU to Ext Pulse ~ _ _ _ _ _ _ Decode Enter SS

---,1 ---l

²⁵⁴⁰ ^{Pch Mag}

4-101 5D R-P Diagnostic Lot

---lJ----

^RU017 ^RU017 4-100 4A Ext Bus Out 0-7

_X ___ '-

^Reset

_I

RU017 Note: The bits from the image storage are the

inverse condition of punch ing.

4-110 5C Reset R-P Shift Reg---~

I ~ PL2:~dress I

(8-Decode) RU043-046

1~(Not) I

4-101 4A Time 225-525----:-. _ _ P_L2_57--j

'-108 3",,",h C,d,

L ______________________________________ J

4-14 8D 2540 Mode - - - 1 4-100 4A Ext A5 Field Decode F 4-100 4C Word Type 0 Set Pulse

RU019

P Or! P Equa Is K Set 4-100 4A K Low Bit 1

F R Restart Gate

~ ^FL

r---4-107 5A (Not) Punch Command In tlk-

----

^RU025

Reader Transfer Advance

I

060 060 060

,

Name MDM Page O~O

I I I

1 Rea der Brush 1m pu Ise 4-103 3A 500 us

-2 (Rdr Brush Imp TO) 4-1036A

--11-

^{150 us}

-3 (Block Advance) 4-1037A

375

4 Reader Se lee! 4-1036C

5 Reader Shift Adv Lot 4-1037C

6 Reset Address Reg 4-1093B

375 • 450 7

I

o~o

LPunch

DeCOde~

4-101 5C Diagnostic Single Cycle

4-101 5D

R-:

Diagnostic Lot A OR Punch Decode 4-434E Restart Gate

Punch

RU071

- l 1 - - - - -

²⁵⁴⁰

Restart

I

Pch Feed Stop IA FL

Pch Chk Diy

(Not) Pch Feed Stop JA

L ______ ^~

Punch T ronsfer Advance

I

³ ⁷

I

⁸

I

^Trap

I

Name MOM Page 000 000 o~o

abo

⁰⁰⁰ ⁰⁰⁰ ⁰⁰⁰ ⁰⁰⁰ ⁰⁰⁰

3 ₆₆₀

I

⁷ _O~O^\ ⁸ ₀₆₀

I

^Trap₀₆₀ ^I I Punch Scan 4-1083A

.. ^I

II I I I

2 Punch Scan #1 Lat 4-108 SA

'/ (

-I

I

3 Punch Scan #2 Lot 4-1087 A

- ^\\ ^I

4 Delta Pch Scan Lat 4-1089A

\ l (

. .

~ \

(

5 Punch Select lat 4-108 7B

)) \\

6 Punch Shift Adv lot 4-1089C

\\

II

_375.110 ^375·12 7 Punch Cycle 4-10838

000

\\

\\ I

8 Reset Address Reg 4-10938

450 • 525

\

_'1

Read Cyc Ie Latch 4-103 3B

000

\ \ -

Reset RP Shift Reg 4-11058

450 • 525 15·450 •

8 Advance AR 4-1094A

5·000 •

• • /. • 1.

10 Advance AR 4-1094A

6 ·000 •

• •

^{I •}

• •

9 RP Shift Adv 4-1106A

225 •

~\ I

I--- - - - -

• • • •

10 End of Byte Record 4-1103C

J ...J

^450·5

II RP Shift Adv 4-1106A

225

• • • -- ^•

12 Pch Advance Decode 4-111 SA

6'000.

• • • • •

11 Reader Trap Latch 4-1029D

\ ^_I 1

13 End of Byte Record 4-110 8C

- ...

12 Reader Micro Lot 4-1039C

\ \ ^j

L . - , 2 2 5 14 Punch Trap Lat 4-1087D

-13 Reset R-P Shift Req 4-1105B

375 • 450

\~

^12·450.

^{I I}

15 Punch Micro Lot 4-1086C

This shows the Shift Register being loaded with 8 bits ~nd recognizing when the register is full (End of Byte Punch Decode Shift Register Loaded

Record). Also the trap latch and the time for the trap; a \I 8 bits are transferred in parallel. When trap is The first 8 bits have been loaded into the Punch Decode Shift Register prior to receiving the punch scan pulse.

taken tile Reader Micro latch turns on, setting conditions for the next 8 bits to be loaded into the registers. One bit is shifted out for each Pch Advance Decode pulse. End of byte record signals the end of 8 bits.

I

000

•

0

² ³

..

⁴

..

⁵

..

⁶ ⁷ ⁸ ⁹

- " 0;' to

I\,) ^~_Q)

- - - - -

-3

²⁵⁴⁰

-

^{- "}₀ _~

-

~ ^0'>

^... !'J

(Not) Rem Stop

A Punch Run In 4 Bit Modify Pu liOn 4-43 4E

-1

3

^FL

to ::J .-+ 0

I\,) Die Sta Diy

01 _~ _~ PL 347

A PFR Unit Exception Gate 4-43 4E

~O Throat Diy FL

I\,) PRF EOF

~ FL OR

cO' en

::J 4- 1 08 3B Punch eyc Ie Power

Q) B (Even Address) Pch Read Out Drive On Reset

r-+ 4-10 1 4A Time 150-525 *Pch Clutch Latch

m

^(150-450) No 2 Br Diy

X (Reader) (Not) No 1 Br Diy

.-+ A 1400 Unit Exception Gate 4-43 8E

(1) End of File (Not) No 1 Br Sta

~ Rd Read Out Drive

::J 4-103 3B Read eyc Ie

Q) FL

'TI ~

OJ ("')

::t' 4-101 4A Time 075-150 Row Bit Reset Even Aux Latch

-<

Unit Exception Gate Reader 4-43 8E

C Rd Feed Stop Latch

=8

OR ,...---+-Gate Rd Complete 25404-43 8E

No 2 Br Diy or Runout

Pch Brush CL D e l a y - - - Pch Brush CL 4-43 4D

:J .-+

en .,

-I:U (")

en

2 3

External Out Interface 4-319D LS Data Bus In

P,O-7'---.r-_-~-~~=---1

4-13 (AS Field Decode (}-F ) - - - 1 4-12 Or! Reg Bits 8-11 _ _ _ _ _ _ _ _ -1 4-12 Orl Reg Bits 3 , 1 2 - 1 4 - - - 1

A 4-36 P2 6D Carry Bit 1 _ _ _ _ _ _ _ _ --1__ __ __ _ _ _

4-134A Or! Word Type 0---1 4-12 (Not) Or! Reg Bit 2 - - -....

4-119D T 6 - - - o o o 4 RMOOI 4134A Orl Word Type 0

-• 4-12 Or! Reg Bit 2 - - - 1 4-119D T 6 - - - I

RM001 4- 1 3 4A Or! W ord Type 3 _ _ ---I

4-12 Or! Reg Bit 2 - - - 1 4-12 Or! Reg Bit 12 _ _ _ _ _ ---1

4-119E T 8 - - - i RS031 4-134A Orl Word Type 3--~rT--' 4-156B KH Decode 7 - - - i A

4-12 (Not) Orl Reg Bit2---t

4-11 9D T7 _OR

4-1258 Prog Mem Word Cycle

~

{ (Not) Orl Reg Bit 2 4-12 Or! Reg Bit 12 - - - I

Or! Reg Bit 13---L--'_J A

RM061

S L091 , SX091-093

Ext Bus Out P,0-7 (Ext AS Field Decode O-F) (K Low Bits 0-3) (K High Bits 0-3) Carry Bit 1

Word Type 0 Reset Pulse

Word Type 0 Set Pulse

Sample AC Into S3

4-149D 1403 Mode PR052

5 6 7 8 ₉

Gate CPU to Ext .Pulse

N 0 N

Dans le document This manual is intended for internal use only and may not be (Page 130-134)

L Row 8;t Even L,,,h

:::r

:::r

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c

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3 •

1---

-I

I

4 5 6

V-J

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~

Rd1RowBit~

~0~

7 8

t---

f---

L Row 8;t Even L,,,h

- - - I

6~6

JI'

f - -

- - - 1

9

I-~'--l

I ::~ ~~: ::: ~~:n L~:t',hh =§j ... --tl----

----..r-,r-,

I

I - - -

1---

I - - -

I - - -

t - - -

I - - -

a

m

0

-...

... fa'

...

o

o

:j 3

"

"

~

4-1014ATimeOOO-075~

•

---,1 ---l

---lJ----

_X ___ '-

I

I ~ PL2:~dress I

1~(Not) I

L ______________________________________ J

----

I

I

,

--11-

I

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DeCOde~

R-:

- l 1 - - - - -

I

I

L ______ ~

I

I

I

I

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abo

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^I ^~

I _{::~ :} ::: :n L~:t',hh =§j ... --tl----

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L ______ ^~

.. ^I

- ^\\ ^I

• • • -- ^•

\ ^_I 1

\ \ ^j

^{I I}

^... !'J