The alternate method of determining which is

the shorted coil is by measuring the resistance from the output of the H D to the +60V return. A resistance of approximately 12 ohms is expected. A resistance of less than 10 ohms is probably a shorted coil

Diagram 1-300 P2

2025 FEMDM (1/69) 1-300

Form Y24-3S29-0 FES Y24-0086

A

B

c

o

E

F

G

H

2

Diagram 1-300 P1

If many positions indicate as errors, the cause may be Fuse F30, F31, F32 and/or F33 being blown.

This should be indicated by a power check light

Run diagnostic sections

*400 and 410

If the error is fault-located, replace the cards listed.

Error stops can occur in section *400 because of the failure of an individual

HD or print position. Fol-low the instructions given in the failing routine if the replacement of the fault located cards does not cor-rect the problem

~---1No

Yes

Run routine WE70 in sec-tion *420.

Note: Routine WE70 prints 2 blank lines followed by the chain image pattern

Use the CE trap buffer scan while running customer program to identify the error position. This will print out 264 characters on the 1052. Each two character group will represent the check plane data for the 132 hammer positions. An A,B, or C will indicate the failing position caused by a hammer driver being on when it should be off

The coil protect check is due to the failure of the current sense reed relay to operate.

Yes

3

Take appropriate action to correct the problem

The error is most probably because of a defective circuit in the coil protect check area

• Diagram 1-300. Coil Protect Diagnostic Technique (Part 2 of 2)

1-300 (1/69)

4

The setting of the coil protect check latch can be blocked by using switch 3 (coil protect check bypass).

This can be done safely because the check is a false check. The check can be due to one of these conditions.

1. An open HD line to the +60V causes the AHDO to indicate that the HD is on. The open could be an open coil or open line.

2.

An incorrect AHDO signal can be given because of a defective HD card or in the circuitry used to develop the AHDO line

Yes

5

Reset the error condition.

Open the current limit switch. Turn on the coil protect check bypass switch to allow running without turning off print ready. The printer can now be run and the previously indicated error positions can be observed.

The error is due to a false setting of the HD latch.

This can be due to a failure of one of the input diodes on the HD

6

.I:::a

0 •

Storage Timing

SAR Bit 9 Storage Timing- Control

.. 9A X Rd Current Source

Storage Timing

Address Main Storage SAR Bit 3

Address Main Storage or Address Aux Storage; there are 128 Y lines for Main storage and 8 Y lines for Aux Storage.

SARBit11 Decode SAR Bit 1

Note: SARBit1=1 MD362,372 selects 8-16K.

Y Storage Timing - Control

Drive

'"

a '"

(J1 11

m

0

...

a

-o

0;.

co _...,.

3 A

2 'Y 3 4

File Data n

-. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. -. ~PG

MS Data . . . Asm

CORE STORAGE

B

Storage Data Out

-Diag 3-3

c

o

1 -E

Diag 3-3

t

Core Storage Addressing

Diag 3-3

CONSOLE

Diag 3-2

I

CONTROLS (Control Register, Error Conditions, Mode Reg, MMSK Reg, Clock}

Diag 3-2

y 5

Integrated 2311 _

Diag 3-9

I

LS Data Asm

Diag 3-4

LS Data

Channel

Diag 3-10

I

6

_ Externa Bus In

...

Integrated 110 2540 Diag 3-7 1403 Diag 3-8 1052 Diag 3-6

I

- External Bus Out

1 R

⁸^Y" , - - - 0 _ _

T

LOCAL STORAGE

Busln

Z Bus

Diag 3-4

t

Local Storage Addressing

Diag 3-4

. . . • . . . ~PG

-

^PG

7

External Facilities

Diag 3-5

I

External Bus In

A-B . . . Data

Asm

Diag 3-4

- 1

Byte 1

~

ALU

8

A-B Register (A-Reg, B-Reg, Branch Conditions}

Diag 3-5

(TIC Control, Adder Decimal Correctod

-Diag 3-5

9 -w ₀

•

~ 0)'

c.c "'"

~ OJ

3

...

m

en

(")

A

0 :::l .-+

"'"

2-(")

"'"

("') C

;:::t'

•

0

OJ .-+ OJ

"

:?!

B

c

o

E

2

CONSOLE

Diag 4-1 to 4-8

ERROR CONDITION (CPU)

Diag 4-10

Control Cycle Oiag4-12

3

Single Cycle Set Address Display Store Load System Reset Interrupt Sw ABCD Start

Address Match

A Reg Check B Reg Check ALU Check Star Adr Check Ctrl Word Check Star Data Check Mach Check Hard Stop

3-2 BE Storage Data Out 0-15

x--.

Force File Control Words

Reset

Clock Controls Diag4-11

Ctrl Reg

Diag 4-12

o

4

CLO CK f -Diag 4-11

1 - - - 0 - 1 5

C trl Reg Bits

5

Time

.. ⁶

(0,1,15)----1

Sw D (4-7

Set

I

(3,8-1 4 ) - - X - - - I I

Set

I

(3,8-14)

X----.

7

Word Types

f---- Word Type 0-7 Diag 4-13

AS Decode

_ AS Decode O-F Diag 4-13,32

o

I - - - Diagnostic Reg Bits Diag

4-13

1-1

¹⁴⁰⁰

o

\---1400 Mode

X

Mode1

Reg 2 ₃

~---r-;::-==-"l

_External

4 S w C - Gates

Diag 5

~

4-14 6 To Local Stor 3-4 2-D Diag 4-14

7 ~~---~

o

Set - - - , MMSK

(3,12-14)

Reset

Set (3,8-11,14) Status Lines

- X I

(3,8-14)

-X

R""'t~

I

^Reg

X--_.

Diag 4- 15 9

o

S Reg

Diag 4-16 7

MMSK Reg Bits

S Reg Bits

8 El

^{Ext 2,3,4}

1

Mod, B;" 0, 1,2 Device

Modes Diag 4-14

9

Modes

N 0 N 01

"'T1

m

0 S

-

(j)

W W

(')

o

en

r l

o

co

::J 0.

J>

..,

~.

CO ::J

CI

Q) r l Q)

"'T1

0"

A

B

c

D

E

2 3 4 5

MORegSet~

3-4 8C Local Storage Bits P-7 .. 8E Storage Data Out Bit 5

.. 40 WO Reg Bits P-7 _ _ _ _ _ MO Asm

6 7

- Adr Match

Sw ABCD Bits Address

3-240 Ctrl Reg Bits

---1

3-2 8A Word Types

----I

^{MO, M1}

3-56A Branch Condition Asm Gates

a

MO

Reg Diag

4-21

0-7"1:::::=

^Match ^{t--. . .}^- Address Match 3-2 3B Control Lines

---,..j

3- 2 5B Ti me _ _ _ _ _ -1 Diag 4-20

Gates -.---~

3-2 3B Sw AB Bits _ _ _ _ _ --I

3-5 4B A Reg Bits P-7 _ _ _ _ _ .. 8E Storage Data Out Bit P1 .. 4E Wl Reg Bits P-6i _ _ _ _ _ _ 3-240 etrl Reg Bits _ _ _ _ _ -1

3-2 3B Sw CD

---1

Diag 4-20

o;ag

4-20

I I

R'9S"~

MMSK Reg Bits

Trap Request

WO Reg Set - - - P

o

WO Reg Diag 4-24

• _ _ _ Mem Adr Bits

M1 Reg Bit 7

X _0-7, P

~14, P1 ^~

Wl Reg Set X _ _ _ _ . . Wl Reg Diag 4-24

*Not Used

WO Reg Bits P·7..4A,3-4 38

Wl Reg Bits P·6 .. 4B,3-5 28

7 p

o

0-7.

Diag4-21 MO Reg Bits P-7 3-42B

"_IIIIj~Ml Reg Bits P-7 3-5 2C

M1 Regt-. . -Diag

Storage Address Assem Diag4-21 4-21

7

Trap Controls and

Addresses

1----...

Oiag 4-22,23

Legend

Read Call

----1---,

_Storage

Use Aux Storage

Controls and Clock Diag 4-27

3-5 4B A-Reg Bits P-7 (Byte

1)----r.S:t~o~rl

3-5 4C B-Reg Bits P-7 (Byte

0)---_

^Data

File Data P-7

---~

3-2 7B Diag Reg Bit 2

---1

Asm Diag 4-27

_ Bus

Data Control

Storage SAR Bits 0-1 4 _ Address Decode Diag 4-27

0 Star

Data Reg

7 PO 8 Diag 4-27 15 P1

o

I

^{18 Bits}

8 9

q28 X Lines

136

Y

Lines

STORAGE

....

(Main and Auxiliary) CIJ

:0

^en

:E ^c:CIJ

c (f.l

-Diag 4-27

Storage Data Out

w Cl

.i:a. ^05"

.,

3 ...

0')

w

!:..

- _r

A

(') Q) (f) r-+

.,

to CD

Cl

Q) r-+

11 0 ~

Dans le document This manual is intended for internal use only and may not be (Page 47-53)

The alternate method of determining which is

the shorted coil is by measuring the resistance from the output of the H D to the +60V return. A resistance of approximately 12 ohms is expected. A resistance of less than 10 ohms is probably a shorted coil

Diagram 1-300 P2

2025 FEMDM (1/69) 1-300

Form Y24-3S29-0 FES Y24-0086

A

B

c

o

E

F

G

H

2

3

• Diagram 1-300. Coil Protect Diagnostic Technique (Part 2 of 2)

1-300 (1/69)

4

2.

5

6

0 •

'"

a '"

m

0

a

-o

3

A

2 'Y 3 4

B

c

o

1

-E

t

I

y 5

I

I

6

...

I

1 R

T

t

-

7

I

- 1

~

8

9

-w 0

•

c.c "'"

3

m

en

A

"'"

"'"

•

0

"

:?!

B

c

o

E

2

3

x--.

o

4

5

.. 6

I

I

-w ₀

.. ⁶

~14, P1 ^~