GENERAL PROCESSOR HARDWARE
JUMPER CONFIGURATIONS
Several jumpers on the processor module provide user-selectable features. The following table lists the jumper configurations and the accompanying figure shows the location of these Jumpers. Jumpers not discussed are reserved for use by DIGITAL and should not be used.
Chapter 3-LS/-11 123 Processor
Jumper Configurations
Jumper Name In Out
W1 Master clock Enable Do not
internal remove.
master clock Manufactur-ing use only
W2 Reserved for Factory- Do not
DIGITAL use installed remove
W4 Event line Disabled Enabled
enable
W5,W6 Power-up See text See text
mode selector
W7 Halt/trap Trap to 108 Enter console
option on halt ODTon halt
W8 Conventional Power-up to Power-up to bootstrap bootstrap ad- bootstrap start address, dress 1730008
addressse-enable If lected by
power-up jumpers
W9-mode 2 Is W15
selected
W9-W15 User-selecta- See text See text ble bootstrap
starting address for power-up mode 2
W16 Reserved for Must be Do not
DIGITAL use Installed remove
W17 Reserved for Must be Do not
DIGITAL use Installed remove
W18 Reserved for Must be Do not
DIGITAL use Installed remove Master Clock - W1
The internal 13.8 MHz oscillator Is disconnected from the clock circuit-ry If W1 Is removed. This jumper Is used by DIGITAL manufacturing and Is not to be removed by the user.
59
Chapter 3-LS/-11 123 Processor
Power-Up Mode Selection - WS and W6
Four power-up modes are available for user selection. Selection is made by removal or insertion of jumpers W5 and W6 as shown in the following listing.
Mode Name W6* WS*
o
PC@24, PS@26 R R1 Console OOT R I
2 Bootstrap I R
3 Extended microcode I I
*R
=
jumper removed; I=
jumper installed.Only the power-up mode is affected, not the power-down sequence.
The following paragraphs describe the sequence of events after exe-cuting common power-up, when selecting each of the four modes. The state of bus signal BHAL T L is significant in power-up mode operation.
Power-Up Mode 0 (PC@24, PS@26)
This mode causes the microcode to fetch the contents of memory locations 248 and 268 and loads their contents into the PC and PS, respectively. The microcode then examines BHAL T L. If BHAL T L is asserted, the processor enters console OOT mode. If BHAL T L is not asserted, the processor begins program execution by fetching an in-struction from the location pOinted to by the PC. This mode is useful when power fail/auto restart capability is desired.
Power-Up Mode 1 (Console ODT)
This mode causes the processor to enter console OOT mode immediately after power-up regardless of the state of any service sig-nals. This mode is useful in a program development or hardware de-bug environment, giving the user immediate control over the system after power-up.
Power-Up Mode 2 (User Bootstrap Starting Address Shown by W8-W1S)
This mode causes the processor to internally generate a bootstrap starting address by looking at jumpers W8 through W15. This address is loaded into the PC. The processor sets the PS to 3408 (PS <07:05>
= 78 ) to inhibit Interrupts before the processor is ready for them. If BHAL
t
L is asserted, the processor enters console OOT mode. If not, the processor begins execution by fetching an instruction from the location pOinted to by the PC. This mode is useful for turnkey applica-tions where the system automatically begins operation without opera-tor intervention.60
Chapter 3-LS/-11 123 Processor Event Line - W4
The bus signal BEVENT L causes the event line flip-flop to be set.
When the processor enters the service state the request will be hon-ored if the PS <07:05> is 5 or less. (BEVENT is a level 6 interrupt.) This causes the microcode to clear the request flip-flop and trap to the line clock vector (location 100. ). If W4 Is inserted, the request flip-flop is disabled and therefore the BEVENT signal is disabled. Users would disable BEVENT, which is normally used as a 60 Hz real-time clock, if they have a programmable clock on the LSI-11 bus.
NOTE
The LSI-11 and LSI-11 /2 processors treat a BEVENT interrupt at a different priority level than the LSI-11/23.
G
I i W18
0---0
~
I-z C1 Z - I -«-0 0 ...J"-u. _0 «0:: 1-1-«z 00 ...J (,)I~
W17o--oW15 W140---0
o---oW13 W120--0
o---oWl1 Wl0~W9
W80--0 O--OW7
W60--0 W4
o--oW5 0---0
KDF11-AA Jumper Locations
IWl
0---0 W2
B
B
Chapter 3-LS/-11 123 Processor Power-Up Mode 3 (Microcode - For Future Use)
This mode causes the microcode to jump to optional control chip 37 a , location 76a , and begin microcode execution. This mode is reserved for future DIGITAL use and is not recommended for customer usage. If it is erroneously selected, the processor will treat It as a reserved instruction trap to location 108 •
Halt/Trap Option - W7
If the processor is in kernel mode and decodes a HALT instruction, BPOK H is tested. If BPOK H is negated, the processor will continue to test for BPOK H. The processor will perform a normal power-up sequence if BPOK H becomes asserted sometime later. If BPOK H is asserted after the HALT instruction decode, the halt/trap jumper (W7) is tested. If the jumper is removed, the processor enters console ODT mode. If the jumper is Installed, a trap to location 10a will occur.
NOTE
In user mode a HALT instruction execution will al-ways result In a trap to location 10a .
This feature is intended for situations, such as unattended operation, where recovery from erroneous HALT instructions is desirable.
Starting Address 1730008 -W8
When power-up mode 2 is selected, the processor examines jumper W8 to determine the starting address for program execution. If W8 and a compatible bootstrap module such as BDV-11 are installed in the system, the microcode will begin execution at 1730008 (conven-tional starting address for DIGITAL systems). If W8 Is removed, a trap to 48 (nonexistent address) will occur. If W8 is removed, the processor looks at jumpers W9 through W15 for the starting address.
Selectable Starting Address - W9 through W15
If the user wishes to start execution from an address other than 1730008 , jumpers W9 through W15 can be used to specify the high byte <15:09> of the starting address. Jumpers W15 through W9 cor-respond to address bits <15:09>, respectively. Bits <08:00> of the starting address are set to 0 by the processor. Jumpers are installed for logic 1, removed for logic O. The starting address can reside on any 256-word boundary in the lower 32K of memory address space.
MODULE CONTACT FINGER IDENTIFICATION
DIGITAL plug-In modules, including the KDF11-AA, all use the same contact finger (pin) identification system. The LSI-11 bus is based on the use of double-height modules that plug into a 2-slot bus connec-tor. Each slot contains 36 lines (18 each on component and solder sides of circuit board).
62
Chapter 3-LSI-11 123 Processor
Slots, shown as row A and row 8 In the figure below, Include a numeric Identifier for the side of the module. The component side Is designated side 1 and the solder side Is designated side 2. Letters ranging from A through V (excluding G, I, 0, and Q) Identify a particular pin on a side of a slot. A typical pin Is designated as follows.
ROW A
ROW B
PIN BV1
PIN BV2
Double-Height Module Contact Finger Identification
Slot (Row) Identifier
"Slot 8"
BE2
Pin Identifier
"PinE"
Module Side Identifier
"Side 2" (solder side)
The positioning notch between the two rows of pins mates with a protrusion on the connector block for correct module positioning.
BACKPLANE PIN ASSIGNMENTS AND LSI-11/23 UTILIZATION