BACKPLANE PIN ASSIGNMENTS AND LSI-11/23 UTILIZATION When configuring a system with the LSI-11/23, the module may be

Inserted In one of several available backplanes. Using a typical back-plane as an example, the accompanying figure shows the backback-plane pin Identification. Individual connector pins shown are viewed from the underside (wiring side). Only pins for one bus location (two slots) ,are

63

Chapter 3-LS/-11 123 Processor

shown in detail. This pin pattern is repeated eight times on this back-plane, allowing the user to install several double-height modules.

POWER AND SIGNAL CONNECTIONS

ROW IDENTIFIER

,000'01 0 C

0..£2.0~ - - - 0 - 1 - 0 - -

-I

0 0 1 0

t-:~ -- ^---o~t-~-

---I

⁰⁰ 1

10

0 ,

-Lo~

_ _ _ _ _

~

_ _ _ _ _ _

~_

I 0:

^{I I}

u _______

~---~--1

Typical Backplane Pin Identification (Pin Side View Shown) HARDWARE OPTIONS

PDP-11/23 systems can be configured using a variety of backplanes, power supp~ies, enclosures, memories, peripherals, etc.

Backplanes

Any of the following LSI-11 bus-compatible backplnnes can be used with the LSI-11/23.

• H9270 - Accepts quad- or double-height modules

• H9273-A - Accepts quad- or double-height modules

• H9281 - Accepts double-height modules only

• DDV11-B - Accepts quad- or double-height modules

H9270 Backplane - The H9270 consists of anS-slot backplane with a card guide assembly. This backplane is designed to accept up to eight double-height modules (Including processor), four quad modules, or a combination of quad- and double-height modules. When used for bus expansion in multiple backplane systems, the H9270 provides space for up to six option modules, plus the required expansion cable connector module(s) and/or terminator module.

64

Chapter 3-LSI-11 123 Processor

VIEW FROM MODULE SIDE OF BACKPLANE PROCESSOR

PROCESSOR OR OPTION 1 (HIGHEST PRIORITY LOCATION)

OPTION 3 OPTION 2

OPTION 4 OPTION 5 3

OPTION 7

(LOWEST PRIORITY LOCATION) OPTION 6 4

H9270 Options Positions

H9273-A Backplane - The H9273-A backplane logic assembly con-sists of a 9 X 4 backplane (nine rows of four slots each) and a card frame assembly. Power and signals are supplied to the backplane through connectors J7 and J8.

The H9273-A backplane is designed to accept both double-height and quad-height modules with the exception of the MMV11-A core memo-ry module. The backplane structure is unique in that it provides two distinct buses: the LSI-11 bus signals (slots A and B) and the CD bus (slots C and D). The connectors that comprise this backplane are arranged in nine rows. Each connector has two slots, each of which contains 36 pins, 18 on either side of the slot.

Three jumpers (W1, W2, and W3) are shown in the following figure.

Jumper W1 enables the line-time clock when inserted and disables it

when removed. .

NOTE

Only one BA 11-N mounting box in any system may have the line-time clock enabled.

65

PROCESSOR MODULE OPTION 1 (HIGHEST PRIORITY) OPTION 2

OPTION 3

OPTION 4

OPTION 5

OPTION 6

OPTION 7

OPTION 8 (LOWEST PRIORITY)

Chapter 3-LSI-11 123 Processor

CONNECTOR 1 CONNECTOR 2

~---~A---~"r---~'~---~

SLOT A SLOT B SLOT C SLOT D

ROW 1

ROW 2

ROW 3

ROW4

ROW 5

ROW6

ROW7

ROW8

ROW 9

VIEW IS FROM MOOULE SIDE OF BACKPLANE

H9273-A Option Positions

When inserted, jumpers W2 and W3 allow the LSI-11 quad-height CPU to run in row 1. Jumpers W2 and W3 are removed when the backplane is used as an expansion backplane in a system.

The connectors designated "Connector 1" are wired according to the LSI-11 bus specification. Slots A and B carry the LSI-11 bus signals and are termed the lSI-11 bus slots. The connectors deSignated

"Connector 2" are wired for +5 V and ground, and have no connec-tions to the LSI-11 bus; instead, C- and O-slot pins on side 2 of each row are connected to the C- and O-slot pins on side 1 in the next lower row.

H9281 Backplane - The H9281 backplanes aq>e designed to accept double-height modules only. The H9281 2-slot backplane is available in six options as listed below. These backplanes allow the user to configure compact lSI-11 bus systems that most efficiently utilize available system space.

66

Chapter 3-LSI-11 123 Processor

120 OHM BUS TERMINATION RESISTORS

o 0 0 0 0 0 0 .--.,

L.._-'

I

~Q~

"¥

1200HM E "S TERMINATION RESISTORS

1 . PROCESSOR MODULE

1· PROCESSOR MODULE 2 - OPTION 1 IHIGHEST PRIORITYI

OPTION 11 CLOWEST PRIORITY I

H9281 Option and Connector Locations (Module Side) Backplane

4-module backplane and card cage assembly 8-module backplane and card cage assembly 12-module backplane and card cage assembly

67

Chapter 3-LS/-11 123 Processor NOTE

Some options are too large to be Installed In an H9281 backplane.

Bus Terminations

Backplane models H9281-AB, -BB, -AC, and -Be include 120 ohm bus termination resistors at the electrical end of the bus; therefore, it is not necessary to install a separate 120 ohm bus terminator module in these backplanes.

DDV11-B Backplane - The DDV11-B is an optional LSI-11 bus ex-pansion backplane for use when additional logic space is required.

The DDV11-B is a 9

x

6, 54-slot backplane with a 9 X 4 slot section (18 individual double-height or 9 quad-height module slots) prebused specifically for LSI-11 bus signal and power and ground connections.

The remaining 9 X 2 slot section is provided with +5 Vdc, GND. and -12 Vdc power connections only; this leaves the remaining pins free for use with any special double-height logic modules to be used in conjunction with the LSI-11 family of modules and bus requirements.

Module Slot Assignments

The slot location assignments of the DDV11-B are illustrated in the accompanying figure. Rows A, B, C, and D are dedicated to the LSI-11 bus. Any module that conforms to the LSI-11 bus specifications may be used in this portion of the DDV11-B. The position numbers indicate the bus grant wiring scheme with respect to the processor module.

The bus grant signals propagate through the slot locations in the posi-tion order shown in the figure below until they reach the requesting device. To provide bus grant signal continuity, any unused slots must be jumpered or unused locations must occur only In the highest posi-tion-numbered locations.

Rows E and F contain the 18 user-defined slots with power and ground connections provided.

Device Priority Within Backplanes - All LSI-11 bus backplanes are priority-structured. Daisy-chained grant signals for DMA and interrupt requests propagate away from the processor from the first (highest priority device) to successively lower priority devices.

68

Chapter 3-LSI-11 123 Processor

f'-

2-

3-'1 ^PROCESSOR PROCESSOR OR OPTION 1 I

~ POSITION 3 OPTION POSITION 2

1

POSITION 4 POSITION 5

4- ~ POSITION 7 POSITION 6

POWER 5-

i

POSITION 8 POSITION 9

TERMINAL

BLOCK 6-

- 1

POSITION 11 I POSITION 10 I

7- ~ POSITION 12 1 POSITION 13

I

l'-

^9-

¹

POSITION 15

I

POSITION 14

I

-~ POSITION 16

I

POSITION 17

I

ROW_ A C : 0

MODULE INSERTION SIDE

USER DEFINED SLOTS

MODULE (COMPONENTS MOUNTED ON OPPOSITE SIDEI

BACKPLANE ~ _ _ ... ' -_ _ ... ' -_ _ - ' ~ _ _ ---I,

PC'~ROrr:==============~C=====~=======:~1C=============:J

o

11111 A 111111 .... 11'"-_ ... 111 " .... 1;11"-1 _C

_II~IIII

⁰ III 11111 E

III~IIII 7;7~

\ \ WIRE WRAP PINS

TERMINAL STRIP POWER SIGNAL PINS

DDV11-B Module Installation and Slot ASSignments Power Supplies

Both the H780 and the H786 power supplies can be used when confi-guring a LSI-11/23 system. The H786 is not available separately, only as part of the BA 11-N enclosure.

Enclosures

The BA11-M mounting box, which includes an H9270 backplane and an H780 power supply, or the BA11-N mounting box, which includes an H9273 backplane and an H786 power supply, can be used in a system with the LSI-11/23 processor.

69

Chapter 3-LS/-11 123 Processor Memory Modules

Several memory modules are available for use with the PDP-11/23 systems. However, modules such as MSV11-C or MSV11-D that perform memory refresh locally are required, since the LSI-11/23 does not perform memory refresh itself. MSV11-C memories will work if provision is made for refresh with some other bus option such as REV11; however, this will degrade system performance and is not recommended.

Peripheral Options

All LSI-11 bus-compatible peripheral devices may be used In PDP-11/23 systems. DMA peripherals should be Installed with the faster throughput devices physically closest to the processor and slower ones farther away. You must insure that faster devices have adequate access to the bus; otherwise, data drop errors may occur.

Interrupt-driven peripherals can be installed in one of the following ways. If all peripherals use the single-level scheme, they must be installed with faster interrupting devices physically closest to the proc-essor. All current DIGITAL LSI-11 bus peripheral devices must use this method. Future peripheral devices, or customer-designed de-vices, can take advantage of the new 4-levellnterrupt scheme. With this scheme, peripherals that are designed to perform distributed in-terrupt arbitration, and that are on different inin-terrupt levels, can be installed in any order. Multiple peripherals on the same request level and peripherals that do not perform distributed arbitration must be installed with the highest priority, or faster, devices closest to the proc-essor.

SYSTEM DIFFERENCES

A number of minor differences exist between the LSI-n/23 (KOF11-AA) processor and the LSI-11 (KD11-F) or LSI-11/2 (KD11-HA) processor. The following is a list of system differences that exist due to the LSI-11 /23's advanced design.

LSI-11/23 has no boot loader in microcode.

Console OOT functions are different In the LSI-11 /23.

LSI-11/23 does not perform memory refresh.

The EVENT line Is on level 6 In LSI-11/23; LSI-11 and LSI-11/2 have it on level 4.

In systems that used the LSI-11, the OOT command "L" could be used to automatically enter the bootstrap loader. Console OOT in the LSI-11/23 does not contain a bootstrap loader command. Users who are down-line loading to LSI-11/23s must change their host software to enter the 14 memory-word bootstrap loader via console ODT. The

70

Chapter 3-LSI-11 123 Processor

REV11 refresh/boot module cannot be used to boot a LSI-11/23 sys-tem. However, the refresh portion of the REV11 can be used to per-form refresh for older MSV11-8 type memories. This will cause a degradation of system performance and is not recommended. If this method of refreshing memories is employed, the bootstrap/diagnostic functionality of the REV11 must be disabled be removing/installing the appropriate jumpers. The 8DV11 bootstrap/diagnostic module may be employed for automatic bootstrap function. The "L" command in the LSI-11 also aut)matically sizes memory. LSI-11/23 users whose memory size varies will have to create a program to self-size the sys-tem or will have to use console ODT.

For improved performance the LSI-11/23 was designed without mem-ory refresh (as was the LSI-11/2). The newer memories such as MSV11-C and MSV11-0 perform refresh locally.

In the LSI-11/23, as in all other multi-level interrupt PDP-11 systems, the event line is on level 6. In the LSI-11 it is on level 4. Users whose own software locked 'out the event line by just setting PS <07:05> to 4 (priority level 4) will have to modify their software to set PS<07:05> to 6 (priority level 6) when installing a LSI-11/23 into their present sys-tem. DIGITAL software is unaffected.

MODULE INSTALLATION PROCEDURE

Dans le document CORPORATE PROFILE (Page 73-81)