Interface Circuits

There are several types of circuits that have been developed for interfacing with capacitive sensors. The two most commonly used with pressure sensors are switched-capacitor charge amplifiers and capacitance-to-frequency converters.

Switched-capacitor charge amplifiers generally offer high sensitivity and immunity from parasitic capacitance. They are based upon charge integrators. A charge integrator can be made using operational amplifiers, as illustrated in Figure 3.17a. For this, the output voltage is given nominally by:

V_out 冕_t0^{t vi(t)dt (3.52)}

The sensor interface (Figure 3.17b) utilizes a two-phase clock to compare the variable sense capacitor (C_X) to a reference capacitor (C_R) [Park and Wise, 1983]. A reset pulse initially nulls the output (Figure 3.17c).

Subsequently, when the clock switches, a charge proportional to the clock amplitude and the difference between the reference and variable capacitor is forced into the feedback capacitorC_F, producing an output voltage given by:

V_out (3.53)

Since this scheme measures the difference between two capacitors, it is unaffected by parasitic capacitance (C_P) values that are common to both.

One concern related to the switched capacitor interface circuit is the switching noise caused by the downward transition of the reset signal. Because the upward transition occurs after the output is sampled, and causes the output to be nulled, it is not critical. The difficulty with the downward transition is that since it is rapid, the charge stored inC_gs, the capacitance between the gate and source of the reset transis-tor, cannot immediately change in response to it, and this is reflected as a spike in the output signal. One solution is to introduce a dummy transistor as shown in Figure 3.18. This transistor is sized to have a net capacitanceC_dummy, that is the same as C_gs. Its source and drain are shorted, so that it does not interfere with the signal transmission. It is switched by a complement of the reset line, so that the downward spike

Vp(C_XC_R)

CX1> CX2 CX2 > CX3 CX3

t

FIGURE 3.17 (a) A simple integrator using an operational amplifier; (b) A switched capacitor charge integrator.

(Reprinted with permission from Park, Y.E., and Wise, K.D. [1983] “An MOS Switched Capacitor Readout Amplifier for Capacitive Pressure Sensors,”Record of the IEEE Custom IC Conference); (c) A timing diagram for control and out-put signals used in (b).

onC_gs appears as an upward spike across C_dummy, and they effectively cancel each other out. If properly designed, the dummy transistor can reduce the reset noise by an order of magnitude.

It is evident from the preceding discussion that despite the general simplicity and robustness of the switched capacitor charge amplifier, it is (as any other interface circuit) susceptible to multiple sources of electronic noise. Switched capacitor circuits, in general, suffer from switching noise that appears as spikes in the voltage waveform at pulse edges (i.e., clock noise). One of the approaches used to combat this is correlated double sampling (CDS), which is also commonly used as a signal processing method in CCD image sensors [Hynecek, 1992]. This technique samples the input to the signal processing circuit block at two different points in time, and produces a signal that is proportional to the difference between them. If the input is switched between a reference null value and the actual signal value, noise components that are common to both intervals will be automatically subtracted away. In this sense, the noise that can be eliminated must be correlated between the two sample times. Generally, noise due to the power supply, clock noise, and even kT/Cnoise can be cancelled in this manner. A simplified representation of the CDS circuit is shown in Figure 3.19. It basically consists of a non-inverting amplifier of gain A, a unity gain buffer, three sampling switches, and two storage capacitors. Initially, switches φ1 and φ2 are pulsed on, whileφ3 is not. This charges up capacitor C1 to a reference value V_s1, whileV_out is held at ground. The noise voltage is then stored in C1. In the second sample period,φ1 and φ3 are pulsed on, while φ2 is not.

If the input is stable at V_s2during this period, then V_outsettles at A(V_s2V_s1), and the noise components that are common to both sampling periods are cancelled out.

V_p

FIGURE 3.18 Cancellation of reset switching noise by using a dummy transistor in a switched capacitor interface circuit.

FIGURE 3.19 Correlated double-sampling used to reduce noise, particularly in conjunction with the switched capacitor charge amplifier interface circuit.

Interface circuits that convert capacitance to frequency are attractive because they offer pseudo-discretized outputs for which exact values are not important and the useful information is carried in the time between signal transitions. This was true of the oscillator for piezoresistive sensors previously described in this chap-ter, but may certainly be used for capacitive interfaces as well. A simple capacitance-to-frequency converter is illustrated in Figure 3.20(a) [Ko, 1986]. This uses two op amps: one in the integrator, which serves as the variable delay element; and the other in the inverting amplifier, which serves as a comparator and switches between high and low saturated output values. The weakness of this approach is that it is susceptible to par-asitic capacitances and resistances, temperature drifts, and other sources of variation in the nominal oscil-lation frequency. A differential approach that compares the measured capacitance to a reference value is generally more robust. Figure 3.20(b) shows an oscillator interface circuit that is switched between the sen-sor and a reference capacitor by a periodic waveform [Wise and Najafi, 1989]. Within each such sampling period, the output oscillates at a frequency that is related to the capacitance, which presents a variable load-ing to one of the elements. The circuit is basically a Schmitt oscillator with an element that has hysteresis in its transfer function. The timing diagram in Figure 3.20(b) explains how the circuit operates. Assume that V_ais descending. As it passes the transition levelV_IL,V_bswitches low, causingV_cto switch high. This causes V_ato start ascending. As it passes the transition levelV_IH, the various outputs switch to the opposite state.

Thus, ifI_Lis the current available to discharge the capacitanceCXof the sensor during the descent ofV_a, then the duration of the descent is nominally t₁CX(V_IHV_IL)/I_L. Similarly, ifI_His the current available for charg-ing up CX, then the duration of the ascent is t₂CX(V_IHV_IL)/I_H. The period if the waveform is Tt₁t₂. Figure 3.20(c) shows how a Schmitt trigger, the element that provides hysteresis in the oscillator dis-cussed above, can be implemented using an operational amplifier. The input voltage to this circuit is com-pared to a reference value, which is simply generated by a voltage divider connected to the output. The output generally remains saturated at the upper or lower limit of the dynamic range, thereby providing two reference values. The transfer characteristics of the circuit are shown in the same figure. Figure 3.20(d) shows a CMOS implementation of the Schmitt trigger. In this, transistors M3 and M6 are small, and oppose the switching of the ouput as it transitions from low to high and high to low, respectively. It should be noted that the circuits shown in Figures 3.20(c) and (d) areinvertingstages, while the one used in Figure 3.20(b) is non-inverting.

Despite their advantages of simplicity and accuracy, capacitance-to-frequency converters are not with-out compromise, and represent a rather slow method of reading with-out the signal. For example, to achieve 10-bit accuracy it is necessary to count 2¹¹(i.e., 2048) pulses. (The last bit provides a resolution of only1/2 of the least significant bit.) For a differential measurement, the circuit would have to switch between the sensor and the reference, taking twice as long.

One of the most highly integrated pressure sensors that has been reported is described in Chavan and Wise (2000). It offered 15-bit resolution over a 300 Torr range, which was achieved by using an on-chip 3-bit multiplexing circuit to select between five diaphragms that were all on the same device. Each of the diaphragms used a center boss. One diaphragm covered the full dynamic range with reduced sensitivity, and its output was used to select between the others for high-resolution output over a narrow range, which was tailored by varying the overall diameters from 1000µm–1100µm. The cavities were sealed in vacuum, which caused a diaphragm deflection of about 9.8µm at atmospheric pressure, leaving a capac-itive gap of 0.5µm between the sense electrodes and resulting in a nominal capacitance of 8–10 pF. The circuit(Figure 3.21) incorporated a buffered analog output with a three-stage programmable switched capacitor amplifier using polysilicon capacitors for reference. The front end was a differential charge inte-grator with a folded cascode amplifier. Correlated double-sampling was used to lower the 1/f noise and the amplifier offset. The circuit also offered separate calibration and operation modes. The fabrication was accomplished using a 20-mask process using one silicon wafer and a glass substrate: 15 for the on-chip p-well circuitry, three for the transducers, and two for the glass processing. The circuitry was fab-ricated in recessed cavities 2.5µm deep, and the transducers in cavities 8µm deep, allowing the bonding anchors to be the highest points on the silicon wafer. Then a 2µm thick level of polysilicon was deposited for electrical feed-throughs, followed by chemical mechanical polishing to make the device flat for bonding to the glass wafer. Unprotected silicon was then dissolved to expose the diaphragm.

C_X

C_X

C_R

V_a

V_a

V_b V_c

V_b V_c V_out

V_out

V_out

V_out

Gain V_in

V_in M4

M1 M2

M3

M6 M5

V_in

V_IL V_IH

V_IH V_IL

R₂ R₁

R₃

R₁

R₂

V_o

CK

CL

CK

− +

− +

+

+

−

(a)

(b)

(c)

(d)

FIGURE 3.20 Capacitance-to-frequency converters are often used for interfacing with capacitive sensors: (a) an implementation using op amps [Ko, 1986]; (b) an implementation that incorporates a reference capacitor, permitting differential measurements; (c) an inverting Schmitt trigger implemented with an operational amplifier; (d) a CMOS implementation of an inverting Schmitt trigger.