4.2 Signal Description
4.2.24 INT ICSS (INTERRUPT ICODE-SIZE EIGHT BITS)
This input, like the BERR input, allows interruption of the current instruction stream. The processor sam-ples INT as instruction boundaries. If interrupts are enabled (1M set in psr) when INT is sampled active, the i860 XP microprocessor fetches the next instruc-tion from virtual address OxFFFFFFOO. INT is level triggered. To assure that an interrupt is recognized, INT should remain asserted until the software ac-knowledges the interrupt (by executing an interrupt-acknowledge cycle, for example). The interrupt may be ignored by the processor if the INT signal does not remain active.
Interrupt latency (the maximum time between asser-tion of INT and execuasser-tion of the first instrucasser-tion of the trap handler) depends both on the internal con-text and on the external system. After INT is assert-ed, the i860 XP microprocessor finishes all instruc-tions currently being executed, including any out-standing bus cycles, before starting the trap handler.
The following instruction sequence is an example of the worst case:
intei®
i860TM XP MICROPROCESSOR If INT is asserted during the execution stage of thelast Idol instruction, the execution of the trap handler may have to wait for:
• Two 2-transfer bursts (the pfld instructions)
• Two data cache line fills (misses by the Idol extended by inquiry cycles and associated write-backs initiated by an external cache or bus control-ler.
Besides the bus-related delays, the i860 XP micro-processor has internal freeze conditions that can de-lay interrupt response by up to 10 additional clocks.
During a locked sequence, the INT pin is ignored, and the INT bit of epsr reflects the value on the INT pin. To limit the time that INT is ignored, the lock instruction can assert LOCK # for only 30-33 in-structions before trapping.
This input is asynchronous, but appropriate setup and hold times must be met to insure recognition on
any specific clock. .
If INT is asserted for at least the last three clock periods before the falling edge of RESET, the i860 XP microprocessor enters eight-bit code-size (CS8) mode. code fetch cycles, and write-backs. External hard-ware can use these signals to observe changes to cache blocks.
4.2.26 KEN # (CACHE ENABLE)
The i860 XP microprocessor samples KEN # to de-termine whether the data being read for the current cache-miss cycle is to be cached. When the i860 XP
microprocessor generates a read cycle that can be cached (CACHE # output active) and KEN # is ac-tive, the cycle is transformed into a burst line fill. By activating KEN #, the memory system commits to a four-transfer burst. The entire 64 bits of the data bus are used for the read, regardless of the state of the
byte-enable pins. .
If KEN # is sampled inactive, code fetches are not transferred in bursts, but 128-bit data items may still be transferred with a burst length of two. 4-transfer bursts for reads and ,writes.
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LEN is inactive if the internal request is for64 bits or less. If LEN is active, the internal request is for 128 auto-matically converted to a four-transfer burst regard-less of LEN by assertion of KEN # .
Table 4.4 summarizes different cycle lengths as they are calculated from the LEN and CACHE # signals.
LEN has the same timing as the address.
4.2.28 LOCK # (ADDRESS LOCK)
This signal is used to provide atomic (indivisible) read-modify-write sequences in multiprocessor sys~
tems. The address to be locked is the one being driven on A31-A3 when LOCK# is aCtivated. A mUl-tiprocessor bus arbiter must permit only one proces-sor a locked read, locked write, or unlocked write to that address and must maintain the lock of that loca-tion across cycle boundaries until LOCK # deacti-vates. The simplest arbitration hardware can just lock the entire bus against all other accesses during LOCK # assl3rtion; however, software must never assume that this implementation is being used.
i860™ )(P MICROPROCESSOR
The i860 XP microprocessor coordinates the exter-nal LOCK # sigexter-nal with the loclt and unlock instructions. Programmers do not have to be con-cerned about the fact that bus activity is not always synchronous with instruction execution. LOCK # is asserted with ADS # for the address operand of the first load or store instruction executed after the loclt instruction.
After an unloclt instruction, LOCK # is deasserted with the next load or store. The i860 XP microproc-essor deactivates LOCK # one clock after ADS # for the last locked bus cycle. Unlike the i860 XR however. The unlocking function is performed by the processor's trap logic.)
The i860 XP microprocessor also asserts LOCK # during TLB miss processing for updates of the ac-cessed bit in page-directory and page-table entries.
The maximum time that LOCK # can be asserted in this case is the time required to perform a nonpipe-lined, four-byte, read-modify-write sequence.
Between locked sequences, at least one cycle of no LOCK # is guaranteed by the behavior of the unloclt instruction.
Between loclt and unloclt instructions, the INT pin is ignored.
Instruction fetches do not alter the LOCK# signal.
4.2.29 M/IO# (MEMORY-liD)
M/IO# specifies whether the current cycle is for the memory address space or for the 1/0 address space. M/IO# is one of the bus cycle definition pins.
Tables 4.2 and 4.3 show the types of bus cycle gen-erated. The value of this pin changes only when i860 XP microprocessor. (If the system does not im-plement pipelining, NA# must not be activated.) The i860 XP microprocessor samples NA# every clock, starting one clock after the activation of ADS #. If the i860 XP microprocessor has a new cycle pend-ing internally when NA # is activated, it initiates that cycle in the clock after NA # is asserted. Up to three bus cycles can be outstanding simultaneously.
NA# is latched internally; the i860 XP invoke write-back of a modified line during outstand-ing bus cycles.
The i860 XP microprocessor determines the DRAM page size by inspecting the software-controlled DPS field in the dirbase register. The page size can
PCD provides a cacheability indication on a page by page basis. This signal, together with PWT, is set to an attribute bit in the page table entry for the current cycle. When paging is enabled, peD corresponds to the eo bit (bit 4) of the page table entry. The i860 XP microprocessor does not perform a cache fill to any page for which CD of the page table entry is set.
When paging is disabled, or for any cycle that is not paged (Idio, stio, Idint, seye) , the i860 XP micro-processor drives PCD inactive.
During TLB miss processing, PCD is inactive while the address translation hardware is accessing the first level page directory. During accesses to the
i860™ XP MICROPROCESSOR
asserted for one clock when incorrect parity has been detected. It reflects the parity status for the entire data bus.
PCHK# does not terminate outstanding bus cycles, so the system must still activate BRDY# a sufficient number of times or activate BOFF # for those cy-cles. PCHK # is always inactive after any code fetch in CS8 mode.
4.2.34 PCYC (PAGE CYCLE)
The page cycle line is active during memory read or write cycles to distinguish page-table accesses from other accesses. The types of bus cycle generated are indicated in Tables 4.2 and 4.3. The value of this pin changes only when ADS# is asserted.
4.2.35 PEN# (PARITY ENABLE)
The i860 XP microprocessor samples this signal for read cycles on the same clock edge at which BRDY # is found asserted. If sampled active, the i860 XP microprocessor feeds the parity check re-sult into the interrupt logic. If a parity error is encoun-.
tered, the i860 XP microprocessor vectors to the trap handler. The BEAR register latches the offend-ing address, as described with the BERR signal.
This interrupt is not masked by the 1M bit of the PSR, nor is it masked during lock cycles.
The system should deassert PEN # any time the DP7 - DPO pins are known not to reflect the parity of the full eight-byte bus (for example, reads from 1/0 devices or ROMs that are not parity protected).
The system should deassert PEN # during code clocks before RESET deactivates. Otherwise, these pins are configured as high-current mode (large out-put buffers).
4.2.36 PWT (PAGE WRITE-THROUGH)
PWT provides a write-back/write-through indication on a page by page basis . .This signal, together with microprocessor drives PWT inactive.
During TlB miss processing, PWT is inactive while the address translation hardware is accessing the
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first level page directory. During accesses to the second-level page-table entry, PWT reflects the WT value taken from the first level page-table entry.
The value of this pin changes only when ADS# is asserted.
4.2.37 RESET (SYSTEM RESET)
Asserting RESET for at least ten ClK periods caus-es initialization of the i860 XP microproccaus-essor. On power up, RESET should remain active at least one millisecond after Vee and ClK have reached their proper DC and AC specs. RESET is synchronous with ClK.
After the RESET signal goes inactive the processor remains in the· RESET state for three more clocks. (5 K!l). The spare input should be left unconnected.
4.2.39 TCK (TEST CLOCK)
This is the clock input for the TAP (test access port).
If the TAP is to be used, this signal must be connect-ed to a clock synchronous to ClK. If the TAP is not used, TCK can be tieqlow. TCK does not need to be kept running when boundary scan is not active.
The rising edge of TCK must be externally synchro-nized to ClK. The boundary scan latches retain their state when TCK is stopped at either logic zero or driving continuous HIGH signals.
4.2.41 TOO (TEST DATA OUTPUT)
This is the serial output of the TAP. The contents of TAP registers are shifted out through TDO on the falling edge of TCK. The data is moved from TDI to TDO without inversion, which allows easy serial cas-cading of different components for scanning.
TDO is held in high-impedance· state,. except while scanning is in progress. This allows parallel connec-tion of these outputs for several components.