ELECTRICAL DATA Maximum Ratings

Table 5-1 is a stress rating only, and functional operation at the maximums is not guaranteed. Functional operat-ing conditions are given in the DC and AC Characteris-tics (Tables 5-2, 5-3, 5-4, and 5-5).

Exposure to the Maximum Ratings may affect device reliability. Furthermore, aithough the 827500B con-tains protective circuitry to resist damage from static electrical .. discharge, always take precautions to avoid high static voltages or electric fields.' Taible 5~1. Absolute Maximum Requlreinents

Condition "Maximum

Requirement

Case Temperature under Bias -65·C to 110·C

Storage Temperature - '65·C to 11 O·C

Voltage on Any Pin with Respect to Ground ':'O.5Vto Vce

+

0.5V Supply Voltage with Respect to Vss -'0.5V to

+

^6.5V

DC

Characteristics

Table 5-2. DC Characteristics Vcc = 5V ±10%,TcASE ;':' O°C to 95°C

Symbol Parameter Min Typ Unit Notes

V1L Input LOW Voltage -0.3 V

VIH InputHIGH Voltage V

VOL Output LOW Voltage "V ^IOL

=

^4.0.mAIII

VOH Output HIGH Voltage V IOH

=

-1.0 mAIII

IlL Input Leakage Current ~ VSS<'-"N<VCC

loz Output Leakage Current +10 ~ VSS<'-"N<VCC

ICCT Power Supply Current 250 mA ^{28 MHzl21}

ICCNT 190 .rnA ^{28 MHzl'l}

ICCT Power Supply Cur 280 375 ... ' mA 45 MHzI2)

ICCNT 215 285 mA 45 MHzl'1

CIN Input CapaCitance 10.0 pF Fc

=

1 MHzl'l

COUT Output Capacitance 12.0 pF ,Fe

=

1 MHzl'l

CFREQIN FREQIN Input Capacitance 20.0 pF Fc

=

1 MHzl'l

NOTES:

1. Measured with FREQIN = 7 MHz.

2. Typical current value measured under typical conditions with the Digital Outputs (DGY, DRV, and DBU) toggling. Maximum current value guaranteed with 50 pF maximum output loading. Analog Outputs disabled.

3. Typical current value measured under typical conditions with the Digital Outputs (DGY, DRV, and DBU) not toggling.

Maximum current value guaranteed with 50 pF maximum output loading. Analog Supply Current IACC not incllided, 4. Not 100% tested.

1-44

intel"

^8275008

AC Characteristics

Table 5-3. AC Characteristics at 28 MHz Vee

=

5V ± 10%, TeAsE

=

O°C to 95°C, CL

=

50 pF

Symbol Parameter Min Max Unit Figure Notes

Frequency 7 28 MHz lXClock

t1 FREQIN Period 35 140 ns 5-1

t2 FREQIN High Time 12 23 ns 5-1 (Note 1)

t3 FREQIN Low Time 12 23 ns 5-1 (Note 1)

t4 FREQIN Fall Time 4 ns 5-1

t5 FREQIN Rise Time 4 ns 5-1

tsa HSYNC,VSYNC,CSYNC,BG,

FCO Valid Delay

24 ns 5-2

tSb VBUS[3:0] Valid Delay 26 ns 5-2

t7 RESETB#, VRESET#, HRESET#, DISDIG, TESTACT Setup

0 ns 5-3

t8 RESET #, VRESET#, HRESET#, DISDIG, TESTACT Hold

13

t9 SCLK[l :0] Valid Delay High 1X Mode

t10

SCLK[l :0] Valid Delay Low 1X Mode

t11 SCLK[1 :0] Valid Delay 1/2X, 1/3X Mode

t12 DATAIN[31 :0] Setup t13 DATAIN[31 :0] Hold

t14 5-7 (Note 2)

t15 ns 5-7 (Note 3)

t1S ns 5-8

t17 DR 1~DBU[7: , ₁₅ ns 5-8 ALPHA[7: DIS, CB, BPP[O],

BPP[1] Output Hold t18 VBUS[3.0], SCLK[1.0], FCO,

HSYNC,VSYNC,CSYNC,CB,BG,

30 ns 5-9 (Note 4)

PIXCLK, DRV[7:0], DGY[7:0], DBU[7:0], ALPHA[7:0], ACTOIS, BPP[O], BPP[1] Float Delay t19 DISDIG, DRV[7:0], DGY[7:0],

DBU[7:0], Digital Output

3t1 ns 5"10

Disable Delay

t20 DISDIG, DRV[7:0], DGY[7:0]!

DBU[7:0], Digital Output

3t1 ns 5-10

Enable Delay

t21 DISDAC, RV, GY, BU Analog 19 ns 5c11 (Note 6)

Output Disable Delay t22 DISDAC, RV, GY, BU Analog

Output Enable Delay

19 ns 5-11 (Note 6)

. . .

InTel~ 8275008

NOTES:

1. This assumes a 35 ns period. For other speeds, the FREQIN High and Low Times should fall within a 40% to 60% duty cycle.

2. For integer pixel times t14 is the Valid Delay on all assertions of PIXCLK duringaclive display time.

3. For non-integer pixel times t15 is the Valid Delay on alternating assertions of PIXCLK during active display time.

4. Not 100% tested.

5. All A.C. specifications are measured at the 1.5V crossing point with a 50 pF load.

6. Analog output delay is measured at the 50% level of the full scale transition with RL " 750 and CL = 25 pF.

AC Characteristics

Table 5-4. AC Characteristics at 45 MHz Vcc = 5V ± 10%, TCASE = O°C to 95°C, C_L = 50 pF

Symbol Parameter Min Max Unit Figure Notes

.Frequency 7 45 MHz 1 XC lock

tl FREQIN Period 22 140 ns 5-1

t2 FREQIN High Time 7 15 ns 5-1 (Note 1)

t3 FREQIN Low Time 7 15 ns 5-1 (Note 1)

t4 FREQIN Fall Time 4 5-1

ts FREQIN Rise Time 5-1

t6a HSYNC, VSYNC, CSYNC, BG,. 5-2

FCO Valid Delay

t6b VBUS[3:0] Valid Delay 5-2

t7 RESETB#, VRESET#, HRESET#, 5-3

DISDIG, TESTACT Setup

ts RESET B#, VRESET#, HRESET#, 5-3

DISDIG, TESTACT Hold

t9 SCLK[1 :0] Valid Delay High 5-4 1X Mode

t10 SCLK[1 :0] Valid Delay Low 5-4 1X Mode

tll SCLK[1 :0] Valid Delay . ns 5-5,5"6 1/2X, 1/3X Mode

t12 DATAIN[31:0] Setup ns 5-4, 5-5, 5-6

t13 DATAIN[31:0] Hold ns 5-4, 5-5, 5-6

t14 1/2tl +20 ns 5-7 (Note 2)

t15 . PIXCLK Valid Delat 20 ns 5-7 (Note 3)

t16 DRV[7:0], DGY[ ns 5-8

ALPHA[7:0], A.

BPP[1]NUG

t17 DRV[7:0], DQY[7:0], D [7:0], 10 ns 5-8

ALPHA[7:0], ACTOIS, CB, BPP[O], BPP[1]NUGR Output Hold

t18 VBU8[3.0], SCLK[1.0], FCO, 30 ns 5-9 (Note 4)

HSYNC, VSYNC, DRV[7:0], DGY[7:0], ALPHA[7:0], ACTOIS, BPP[O], BPP[1]NUGR Float Delay t19 DISDIG, DRV[7:0], DGY[7:0],

DBU[7:0], Digital Output

3t1 ns ~ 5-10.

Disable Delay

1-46

D8il~.

^8275008

AC Characteristics (Continued)

Table 5-4. AC Characteristics at 45 MHz Vcc = 5V ± 10%,.TcASE = O°C to 95°C, CL = 50 pF

Symbol Parameter Min Max .. ····'·Unit Figure Notes

t20 DISDIG, DRV[7:0], DGY[7:0], DBU[7:0], Digital Output

5-10 Enable Delay

t21 DISDAC, RV, GY, BU Analog 5-11 (Note 6)

Output Disable Delay

t22 DISDAC, RV, GY, BU Analog ns 5-11 (Note 6)

Output Enable Delay NOTES:

1. This assumes a 22 ns period.~?f.oih:\~gye s, FREQIN High and Low Times should fall within a 40% to 60% duty

cycle. .'.'.. ....; ...

2. For integer pixel times t14 is the Valid Qefay on all assertions of PIXCLK during active display time.

3. Fo~ non-integer pixel times t15 is the Valid Delay on alternating assertion's of PIXCLK during active display time.

4. Not 100% tested.

5. All A.C. specifications are measured at the 1.5V crossing point with a 50 pF load.

6. Analog output delay is measured at the 50% level of the full scale transition with RL = 75Q and CL = 25 pF.

FREQIN

i<f-:-t2

, 2.0V: ,

1.sy I O.8V , _ _ - , I '

~15!~

''--__ 0/:

4-- '

,

,

:<t'{'--- ----»1

Figure 5-1. Clock Waveforms

1.5V

lea,16b i

:<t--- ....

^'

,---_ ,---_ ,---_ ,---_ ,---_

~~~_1._5V

_ _ _ _ _ _ _ _ _ ___

Figure 5-2. Output Waveforms

'--_--I:

~:181~ , ,

-,"--', 17 ,~ i

---~~~~~~.~~---1.5V7\\.. _ _ ---JJ'\\.. _ _ _ _ _ _ _ _ _

Figure 5-3. Input Waveforms

240855-20

240855-21

240855-22

8275008

FREOIN

SCLK[l :OJ

DATAIN[31 :OJ

240855-23 Figure 5·4. 1X SCLK Mode

FREOIN

SCLK[1:0J

I

DATAIN[31 :OJ

tl1: : t12 : t13

-:

^{'-- ~}

... ---~~--- ....

240855-24 Figure 5·5. 1/2X SCLK Mode

FREOIN - - I

A h / \

- I - - . . . " " - - "

^I

I

SCLK[l :OJ

DATAIN[31 :OJ

I ' , . . . _ _ _ _ _ ""

--.3-

^{1.5V : \ , ,} ________________

,..,t

I I I I t12: t 13

- : : -t11 _~ ^{: - tl1} ;...:..:---.:

--- ... ~

^240855-25

Figure 5·6. 1I3X SCLK Mode

1-48

int'e t

FREQIN

PIXCLK

8275008

:_t1--;

~

_I ^1.5V

^{' ,}

_•

J\.-T'

_{I I}

,

^"

~

^I:: , , 1.5V ,

J-FPLI,

'

I'

,

L t i t I I

- ' ' - - 15, _{I ' I} ' t ' _1..- 14 ----.J - ' '-- t" 15

:-+-

t14~ "

Figure 5-7. PIXCLK Waveforms

PIXCLK

,

________

1_.5_V~---­

~,--'

'tHi t17'

Figure 5-8. Output Setup and Hold

TESTACT#

~

^,

I-

^, _,

=t) ^, , ⁽ ,

'--' '--'

't_{18 '} 't18 '

240855-27 240855-26

240855-28 Figure 5-9. TESTACT# Float Delay

8275008

fREQIN

DISDIG ) 1.5V

\\---....;.-.--DRV[7:01 DGY[7:01

DBU[7:01 X X X \ 1 . 5 V _,

IXX'!

_,

'----'19---. : - t

^{20 - :}

Figure 5·10. DIS DIG to Digital Output Delay

DISDAC

---f- _I

^{1.5V \ :}

I~---RV

GY BU

~

INDICATES HIGH-IMPEDANCE STATE

240855-39 Figure 5·11. DISDAC to Analog Output Delay

Digital to Analog Converter Electrical Characteristics

Table 5·5. DAC D.C. Characteristics AVec = 5V ± 10%;

Symbol Parameter Min Typ

Iref Reference Current

lIs Output Current* 0.93 *(255/18.5) * Iref (Full Scale)

VIs Output Voltage (Full Scale) INL Integral

Nonlinearity DNL Differential

Nonlinearity

IACC Analog Supply 3' Ifs + 8

Current

DOTR OAC to OAC 5.0

Tracking at Full Scale

Cout Output 12

Capacitanc NOTES:

1. Maximum Its allowed = 22 mA.

2. Maximum IACC allowed = 74 mA. Typical value 01 IACC = 3 • lIs + 6

3. Maximum deviation between RV. GY and BU outputs at fullscale output voltage.

4. Not 100% tested.

5. All DAC testing done with Iref = 1500 >tA. 1-50

Unit

~A

mA V LSB LSB mA

%

pF

240855-38

Notes

(Note 1)

(Note 2) (Note 3)

(Note 4)

int:e ^L

^8275008

Table 5-6. DAC A.C. Characteristics

Symbol Parameter Min Typ ft4~.)!; ^{Unit Notes}

tr, tf Rise/Fall Time ns (Note 1)

ClkF Clock Feedthrough dB (Note 2)

GlEn Glitch Energy pV-sec (Notes 2, 3)

Skew Output Skew ns

Xtlk Crosstalk pV-sec (Note 2)

NOTES:

1. Maximum value is for RL = 750 and CL = % to 90% fuliscale transmission.

2. Assumes an 80 MHz filter on output.

3. Glitch energy generated from the il)!l.

4. DISDIG must be tied high.<;;t

5. Assumes the use of 0.1 IlF capacitor be n VGCS and AVcc and 0.1 IlF and 10 IlF capacitors between IREFIN and AVcc.

IRE FIN VGCS

8275008 Avss

Avec

R G 8

Ground

f-~~---+---+---+5V (AveC>

tis = 255 * Iref 18.5 Vb = If II * RL where:

R, = 750 RL = Load Resistance C, =0.1 ~F

CL :::: Load Capacitance

o <lout < If II o ~Vout ~ Vfll

Ground

Figure 5-12. Typical Output Configuration

240855-29 To Monitor

82750DB

Dans le document MULTIMEDIA AND SUPERCOMPUTING (Page 55-63)