S3 Incorporated
Table 3-1. Pin Descriptions - LPB Mode IContinued) Symbol Type Pin Numberls) Description
Memory Control
RAS[1:0] 0 50. 84 Row Address Strobes. RASl is output on pin 50 when bit 6 of SRA is set to 1 for a PCI configuration. RASl is used to select the upper 2 MBytes of a 4-MByte memory configuration. It is not available for LPB VL-Bus configurations, limiting memory to 2 MBytes.
CAS[7:4] 0 52,51,49,48 Column Address Strobe Lines 7:4]. These signals are not driven when the Tri064-compatible feature connector is enabled by setting bit 0 of SRD to 1 and bit 1 of SRD to O. This prevents contention on the multiplexed PD lines.
CAS[3:0] 0 82, 83, 85, 86 Column Address Strobe Lines 3:0.
WE 0 125 Write Enable.
OE[1:0] 0 50, 124 Output Enable. OEl is output on pin 50 when bit 2 of CR36 is cleared to 0 (EDO memory). If the feature connector is disabled (bit 0 of SRD cleared to 0). this output is the same as OEO (for 64-bit PD bus operation). If the Tri064-compatible VAFC feature connector is enabled (bit 0 of SRD set to 1 and bit 1 of SRD cleared to 0). OEl is held high (not asserted). This ensures that EDO memory data is not driven on the multiplexed PD lines when the Tri064-compatible feature connector is enabled. OE 1 is never generated in fast page mode operation. Instead, if bit 6 of SRA is cleared to 0 (default). a second OEO signal is output on pin 50. This allows the same board to use either fast page or EDO memory in 2-MByte designs with no additional hardware. OEl is not available for LPB VL-Bus configurations. Memory designs requiring use of jJin 50 as a memory control signal cannot be used.
VIDEO INTERFACE
PDOWN I 165 Power Down. Asserting this signal tums off the RGB analog output from the DACs.
VREF 162 Voltage Reference. This pin is tied to Vss through a 0.1
~F capacitor.
RSET 166 Reference Resistor. This pin is tied to Vss through an external resistor to control the full-scale current value.
AR 0 168 AnalogHed. Analog red output to the monitor.
AG 0 171 Analog Green. Analog green output to the monitor.
AB 0 172 Analog Blue. Analog blue signal to the monitor.
PINS 3-7
Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
Table 3-1. Pin Descriptions - LPB Mode (Continued) Symbol Type Pin Number(s) Description
ENFEAT 0 151 Enable Feature Connector. Setting SRD_O to 1 drives this signal low when SRl C_l-0 are OOb. This also enables all feature connector operations.
BLANK B 191,206 Video Blank. The BLANK function is on pin 191 when LPB feature connector operation is enabled in PCI VFCBLANK B 115 configurations. It is on pin 206 for LPB VL-Bus
configurations. It is on pin 115 when Tri064-compatible VAFC operation is enabled and is called VFCBLANK.
When ESYNC is high, BLANK is a feature connector output. When ESYNC is low, BLANK is a feature connector input that, when driven low, turns off the video output.
ESYNC I 183,205 External SYNC. The ESYNC function is on pin 183 when LPB feature connector operation is enabled in VFCESYNC I 109 PCI configurations. It is on pin 205 for LPB VL-Bus
configurations. It is on pin 109 when Tri064-compatible VAFC operation is enabled and is called VFCESYNC.
When ESYNC is driven low, HSYNC, VSYNC and BLANK become inputs. When ESYNC is high, HSYNC, VSYNC and BLANK become outputs.
EVIDEO I 203 External Video. The EVIDEO function is on pin 203 when LPB feature connector operation is enabled. It is VFCEVIDEO I 111 on pin 111 when Tri064-compatible VAFC operation is
enabled and is called VFCEVIDEO. When this input is asserted low, PA[15:0] (or VFCPA[15:0]) are inputs and are sampled by VCLKI. When this input is high, PA[15:0] (or VFCPA[15:0]) are outputs to the feature connector.
EVCLK I 204 External VCLK. The EVCLK function is on pin 204 when LPB feature connector operation is enabled. It is VFCEVCLK 113 on pin 113 when Tri064-compatible VAFC operation is
enabled and is called VFCEVCLK. When this input is asserted low, VCLK is an input to the internal RAMDAC. When this input is high, VCLK is output to the feature connector.
VCLK B 148 Video/Pixel Clock. The VCLK function is enabled on pin 148 when feature connector operation is enabled.
When EVCLK (or VFCEVCLK) is high, this signal is an output to the feature connector. When EVCLK is low, this becomes an input used only for testJ)urposes.
VCLKI I 106 VCLK Input. The VCLKI function is enabled when LPB VAFC (16-bit) feature connector operation is enabled.
Setting bit 1 of SRB to 1 causes VCLKI to be used to clock in feature connector pixel data to the internal RAMDAC.
3-8 PINS
S3 Incorporated
Table 3-1. Pin Descriptions - LPB Mode (Continued) Symbol Type Pin Number(s) Description
HSYNC B 149 Horizontal Sync. When ESYNC (or VFCESYNC) is high, this is the horizontal sync output. When ESYNC is low, this is an input from the feature connector.
VSYNC B 150 Vertical Sync. When ESYNC (or VFCESYNC) is high, this is the vertical sync output. When ESYNC is low, this is an input from the feature connector.
PA[15:0] B 201-199,189- Pixel Address Lines [15:0]. The PA[15:0] function is 185, 202, 184, enabled on the pins indicated for PCI configurations 175, 174, 155, when LPB feature connector operation is enabled.
154,147,146 Only PA[7:0] are enabled for VL-Bus configurations.
The PA function is on the pins indicated for
VFCPA[15:0] B 144,142,140, VFCPA[15:0] when Tri064-compatible VAFC operation 138,134,132, is enabled. When EVIDEO (or VFCEVIDEO) is high, PA 130,128,127, signals are outputs to the feature connector. When 129, 131, 133, EVIDEO is low, PA signals are inputs and are sampled 136, 139, 141, by VCLKI if bit 1 of SRB is set to 1.
143 MISCELLANEOUS FUNCTIONS
General Data, I/O and Serial Ports
GA[15:0] 0 105, 103, 101, (PCI) General Address Bus. These signals provide the 98, 95, 93, 91, address for BIOS ROM reads. They are multiplexed 89, 88, 90, 92, with PD signals. Programmers must ensure that the 94,97,100, memory bus is inactive when reading the ROM.
102, 104
GD[7:0] I 53, 55, 57, 59, (PCI) General Data Bus. These signals carry data for 63, 65, 67, 69 BIOS ROM reads. They are multiplexed with PD
signals. Programmers must ensure that the memory bus is inactive when reading the ROM.
GPIOSTR 0 151 (VU General Input/Output Port Write Strobe. If SRl C_l-0 are 01 b, this is asserted whenever a
Trio64V+ Integrated Graphics/Video Accelerator
53 Incorporated
Table 3-1. Pin Descriptions - LPB Mode (Continued) Symbol Type Pin Number(s) Description
STWR 0 190 (PCI) Strobe Write. If SR1 C_1 is cleared to 0, this signal is asserted whenever a write is made to CR5C.
It is used to enable a General Output Port latch.
SPCLK I/O 205 Serial Port Clock. This is the clock for serial data transfer, either for 12C or DDC2 monitor data communications. As an output, it is programmed via MMFF20_0. As an input, its status is read via MMFF20_2. In either case the serial port must be enabled by setting MMFF20_ 4 to 1. PD[26:25] can be strapped to allow I/O (E2H or E8H) access to the Serial Port reqister while the Trio64V+ is disabled.
SPD I/O 206 Serial Port Data. This is the data signal for serial data transfer, either for 12C or DDC2 monitor data communications. As an output, it is programmed via MMFF20_1. As an input, its status is read via MMFF20_3. In either case the serial port must be enabled by setting MMFF203 to 1. PD[26:25] can be strapped to allow I/O (E2H or E8H) access to the Serial Port register while the Trio64V+ is disabled.
LOCAL PERIPHERAL BUS Scenic/MX2 Mode
LD[7:0] I/O 202, 184, 175, LPB Data. This is the Scenic Highway data bus and 174,155,154, carries compressed data to the Scenic/MX2 and video 147.146 data from the Scenic/MX2.
LCLK I 148 LPB Clock. This clock controls transactions between the Trio64V+ and Scenic Hiqhwav peripherals VREO/VRDY 0 203 Video Request/Ready. This signal is part of the the
Scenic Highway data transfer protocol between the Trio64V+ and the Scenic/MX2.
CREQJCRDY I 204 Scenic/MX2 Request/Ready. This signal is part of the the Scenic Highway data transfer protocol between the Trio64V+ and the Scenic/MX2.
ENFEAT 0 151 Enable Feature Connector. This signal is connected to the Scenic/MX2 chip enable input such that the Scenic/MX2 is disabled when feature connector operation is enabled.
3-10 PINS
53 Incorporated
Table 3-1. Pin Descriptions - LPB Mode (Continued) Symbol Type Pin Number(s) Description Video 8 in and Video 16 (PCI only) Modes
LD[7:0J I 202, 184, 175, LPB Data Bus [7:0]. This is the Scenic Highway data 174, 1 55, 154, bus and carries video data input.
147. 146
LD[15:8J I 201-199,189- (PCI) LPB Data Bus [15:8J. Scenic Highway video data 185 input for the upper data byte in Video 16 mode.
HS I 203 HSYNC. HSYNC input signaling the transition from one line to the next.
VS I 204 VSYNC. VSYNC input signaling the transition from one frame to the next.
HD[7:0J 0 201-199,189- Host Data. CL-480 compressed data.
185
HSEL[2:0J 0 178-176 Host Select. These signals select one of five CL-480 host interface registers.
Video 8 InlOut Mode (CL-480) (PCI only)
LD[7:0J I 202, 184, 175, LPB Data Bus [7:0]. This is the Scenic Highway data 174, 1 55, 154, bus and carries video data input.
147.146
OS 179 Data Strobe. The Trio64V+ asserts this signal to select the CL-480 for a read or write operation.
RNJ 0 180 ReadNJrite. The Trio64V+ drives this signal high to specify a CL-480 read cycle and low to specify a write cvcle.
DTACK I 181 Data Acknowledge. The CL-480 asserts this signal when it latches compressed data from the Trio64V+ or when it has placed video data on LD[7:0J. This is an open drain signal.
CFLEVEL I 182 Compressed Data FIFO Level. When this signal is low, the CL-480 FIFO has room for at least 44 bytes of compressed data. This is an open drain siqnal.
POWER AND GROUND
VDD I 12,37,62,81, Digital power supply 96,137,192
AVDD I 164,169,170 Analoq power supplv (RAMDAC)
CLKAVDD[l :2J I 158, 160 Analog power supply (clock synthesizer) VSS I 9, 22, 32, 47, Digital ground
60,71,87,99, 114, 123, 126, 135,145, 195
AVSS I 159, 161, 163, Analog ground 167,173
PINS 3-"