This mode is selected by setting bits 7-4 of CR67 to 1101b. One pixel is transferred to the DACs each VCLK cycle via the LUT bypass.
8.3 RAMDAC REGISTER ACCESS
The standard VGA RAMDAC register set (3C6H -3C9H) is used to access the internal RAMDAC registers.8.4 RAMDAC SNOOPING
For PCI bus configurations, setting bit 5 of the Command configuration space register (Index 04H) to 1 causes the. Tri064V+ to snoop for RAM-DAC writes. This means that the Tri064V+ will write the data to its local RAMDAC but will not claim the cycle by asserting DEVSEL. This allows the ISA controller to also generate a write cycle to a secondary RAMDAC. The Tri064V+ always provides the data for RAMDAC reads.
If bit 5 of the PCI Command register is cleared to 0, the Tri064V+ claims all RAMDAC read and write cycles.
Bits 2-0 of CR34 allow handling of PCI master aborts and retries to be individually enabled or disabled during RAMDAC cycles.
If power-on strapping bit 12 (CR37, bit 4) is pulled low at resetfor a VL-Bus configuration, LOCA and SRDY are not generated by the Tri064V+ for RAMDAC write accesses. The Tri064V+ gener-ates write cycles to the local RAMDAC and the ISA controller also generates cycles to an off-board RAMDAC (mirroring). RAMDAC reads are always from the local RAMDAC.
If bit 7 of CR37 is set to 1, the Tri064V+ claims all RAMDAC read and write cycles (LOCA and SRDY are generated).
8.5 SENSE GENERATION
The internal RAMDAC contains analog voltage comparators. These drive the internal SENSE signal active low whenever the output on any of the AR, AG or AB pins exceeds 330 mV ± 20%.
The state of this internal signal can be read via bit 4 of 3C2H. This information can be used to detect the existence and type of monitor (color/mono) connected to the system.
8.6 POWER CONTROL
The Tri064V+ provides a PDOWN input pin.
When a logic 0 signal is driven to this pin, the RGB analog outputs are turned off.
RAMDAC FUNCTIONALITY 8-3
,I. Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorpora~ed
S3 Incorporated
Section 9: Clock Synthesis and Control
The Trio64V+ contains two phase-locked loop (PLL) frequency synthesizers. These generate the DCLK (video clock) and MCLK (memory clock) signals for the graphics controller block.
9.1 CLOCK SYNTHESIS
Each PLL scales a single reference frequency input on the XIN pin. By placing a parallel-reso-nant crystal between the XOUT output pin and the XIN pin, the reference frequency is generated by the Trio64V+'s internal oscillator. Alternately, a CMOS-compatible clock input can be con-nected to XIN to provide the reference frequency.
The frequency synthesized by each PLL is deter-mined by the following equation:
(M+2) four
=
R x fREF(N+2)x2
where R = 0,1,2 or 3
Programmed PLL M and PLL N values should be consistent with the following constraints:
1. 135MHz< (M+2)fREF < 270MHz - (N+2)
-2. min N;::: 1
Note that values used for the parameters are the integer equivalents of the programmed value. In particular, the R value is the code, not the actual frequency divisor.
The PLL M value can be programmed with any integer value from 1 to 127. The binary equivalent of this value is programmed in bits 6-0 of SR11 forthe MCLK and in bits 6-0 ofSR13 forthe DCLK.
The PLL feedback loop frequency from the volt-age controlled oscillator stvolt-age is scaled by divid-ing that frequency by (M+2).
The PLL N value can be programmed with any integer value from 1 to 31. The binary equivalent of this value is programmed in bits 4-0 of SR10 forthe MCLK and in bits 4-0 of SR12 forthe DCLK.
The reference frequency is divided by (N+2) be-fore being fed to the phase detector stage of the PLL.
The PLL R value is a 2-bit range value that can be programmed with any integer value from 0 to 3.
The R value is programmed in bits 6-5 of SR 10 for MCLK and bits 6-5 of SR12 for DCLK. This value codes the selection of a frequency divider for the PLL output. This is shown Table 9-1.
Table 9-1. PLL R Parameter Decoding R-Range Code Frequency Divider
00 1
01 2
10 4
11 8
The entire PLL block diagram is shown in Figure 9-1.
CLOCK SYNTHESIS AND CONTROL 9-1
II· Trio64V+ Integrated Graphics/Video Accelerator
53 Incorporated
KPLlBLK
Figure 9-1. PLL Block Diagram The following sequence may be followed to
3. Determine if the following constraint is met:
(Mt2) fREF
0.995 fOUT< m. < 1.005 fOUT (N1+2) 2
4. If the constraint in step 3 is met, the M and N values used will generate the desired frequency (within the specified tolerance).
If the constrain is not met, repeat steps 2 and 3 with N increased by 1 each time un-til the constraint in step 3 is met. Note that multiple combinations of M and N are pos-sible for a given output frequency.
9.2 CLOCK REPROGRAMMING
The Tri064V+ powers up with a DCLK frequency of 25.125 MHz (standard VGA) and an MCLK frequency of 45 MHz. The DCLK frequency can be changed to 28.322 MHz by setting bits 3-2 of3C2H to 01 b and can be changed back to 25.125 MHz by setting bits 3-2 of 3C2H to OOb. The loading of the DCLK frequency values requires that bit 1 of SR15 be set to 1.All other DCLK frequencies must be generated by re-programming SR12 and SR13. The new PLL parameter values can be loaded in one of two
9-2 CLOCK SYNTHESIS AND CONTROL
ways. If bit 5 ofSR15 is cleared to 0, the new DCLK frequency is loaded by setting bit 1 of SR15 to 1 and then setting bits 3-2 of 3C2H to 11 (if they are not already programmed to this value). Bit 1 of SR15 should be left at a value of 1. Actual loading will be delayed for a short but variable period of time.
The alternate approach to loading the new DCLK frequency is to program bits 3-2 of 3C2 to 11 (if they are not already programmed to this value).
Next, program SR12 and SR13 and then toggle bit 5 of SR15 by programming it to a 1 and then a
o.
This immediately loads the DCLK and MCLK frequencies (no variable delay). For example, pseudocode to change DCLK to the frequency other bits unchanged 3C5 <= RMW Use read/modify/write toclear bit 5 to 0 and leave other bits unchanged
Either loading approach should work. The sec-ond (immediate loading) approach helps with system testing since the timing of the load is predictable. The first approach (via bit 1 of SR 15) has the advantage of separating the loading of DCLK from that of MCLK.
S3 Incorporated
After power-up, all MCLK frequency changes must be made by re-programming SR10 and SR11. If bit 5 of SR15 is cleared to 0, the new frequency does not take effect until a 1 has been written to bit
°
of SR15. This bit must then be cleared to°
to prevent repeated loading. Actual loading will be delayed for a short but variable period oftime.As explained above for DCLK, toggling bit 5 of SR15 (0,1,0) immediately loads both the DCLK values in SR12 and SR13 and the MCLK values in SR10 and SR11.
9.3 DCLK CONTROL
DCLK is generated by the internal clock synthe-sizer. VCLK is the signal used to clock pixel data into the internal RAMDAC. For most modes of operation, VCLK is generated directly from DCLK and has the same frequency and phase (neglect-ing internal gate delays). Bit
°
of CR67 provides the option to invert DCLK before it becomes VCLK.In mode 8, the internal RAMDAC requires two clocks. The normal internal DCLK frequency is divided by two via bit 4 of SR15 to provide the standard VCLK input. Undivided DCLK provides the other input. This clock can be inverted via bit 6 of SR15.
Certain 4 bits/pixel modes require that DCLK be halved. This is the case for bit 6 of AR10 set to 1 and bit 4 of CR3A cleared to
°
and is enabled by setting bit4 or SR15to 1 and clearing bit3 ofCR33 to 0.CLOCK SYNTHESIS AND CONTROL 9-3