THE iAPX 286 INSTRUCTION SET - MANUAL PROGRAMMER'S iAPX 286

This section presents the iAPX 286 instruc-tion set using Intel's ASM286 notainstruc-tion. All possible operand types are shown. Instruc-tions are organized alphabetically according to generic operations. Within each operation, many different instructions are possible depending on the operand. The pages are of instructions which specify operands. These conventions are as follows:

In: (n is a digit from

°

through 7) A ModRM byte, plus a possible immediate and displace-ment field follow the opcode. See figure B-1 entry at the end of the row indicates whether the effective address operand is a register or memory; if memory, the entry indicates what kind of indexing and/or displacement is used.

Entries with D8 or D 16 signify that a one-byte or two-one-byte displacement quantity immediately follows the ModRM and optional immediate field bytes. The signed displace-ment is added to the effective address offset.

I r: A ModRM byte that contains both a register operand and an effective address

operand, followed by a possible immediate and displacement field. See figure B-2 for the encoding of the fields. The ModRM byte could be any value appearing in table B-1.

The column determines which register operand was selected; the row determines the form, of effective, address. If the row entry mentions D8 or D 16, then a one-byte or two-byte displacement follows, as described in the previous paragraph.

cb: A one-byte signed displacement in the range of -128 to

+

127 follows the opcode.

The displacement is sign-extended to 16 bits, and added modulo 65536 to the offset of the instruction FaLLa WIN G this instruction to obtain the new IP value.

cw: A two-byte displacement is added modulo 65536 to the offset of the instruction FOLLOWING this instruction to obtain the new IP value. ModRM bytes. The opcode determines if it is a signed value.

THE IAPX 286 INSTRUCTION SET

In Instruction Byte Format

imm. iow(1) imm. high(1) disp-high

7 6 5 4 3 2

o

"mod" Field Bit Assignments

mod Displacement

00 OISP = 0(2), disp-Iow and disp-high are absent

01 OISP = disp-Iow sign-extended to 16-bits, disp-high is absent 10 OISP = disp-high: disp-Iow

11 rim is treated as a "reg" field

"r 1m" Field Bit Assignments

+

^OISP

110 (BP)

+

^0ISp(2)

111 (BX)

+

^OISP

OISP follows 2nd byte of instruction (before data if required).

NOTES:

1. Opcode indicates presence and size of immediate value.

2. Except if mod=OO and r/m=110 then EA=disp-high: disp-Iow.

Figure B-1. In Instruction Byte Format

THE IAPX 286 INSTRUCTION SET

Table 8-1. ModRM Values

Rb = AL CL OL BL AH CH OH BH

Rw = AX CX OX BX SP BP SI 01

REG = 0 1 2 3 4 5 6 7

ModRM values: Effective address:

00 08 10 18 20 28 30 38 [BX + SI]

01 09 11 19 21 29 31 39 [BX + 01]

02 OA 12 1A 22 2A 32 3A [BP + SI]

03 OB 13 1B 23 2B 33 3B [BP + 01]

04 OC 14 1C 24 2C 34 3C [SI]

05 00 15 10 25 20 35 3D [01]

06 OE 16 1E 26 2E 36 3E 016 (simple var)

07 OF 17 1F 27 2F 37 3F [BX]

40 48 50 58 60 68 70 78 [BX + SI] + 08(1) 41 49 51 59 61 69 71 79 [BX + 01] + 08 42 4A 52 5A 62 6A 72 7A [BP + SI] + 08

43 4B 53 5B 63 6B 73 7B [BP + 01] + 08

44 4C 54 5C 64 6C 74 7C [SI] + 08

45 40 55 50 65 60 75 70 [01] + 08

46 4E 56 5E 66 6E 76 7E [BP] + 08(2)

47 4F 57 5F 67 6F 77 7F [BX] + 08

80 88 90 98 AO A8 BO B8 [BX + SI] + 016(3) 81 89 91 99 A1 A9 B1 B9 [BX + 01] + 016

82 8A 92 9A A2 AA B2 BA [BP +SI] + 016

83 8B 93 9B A3 AB B3 BB [BP + 01] + 016

84 8C 94 9C A4 AC B4 BC [SI] + 016

85 80 95 90 A5 AD B5 BO [01] + 016

86 8E 96 9E A6 AE B6 BE [BP] + 016(2)

87 8F 97 9F A7 AF B7 BF [BX] + 016

CO C8 DO 08 EO E8 FO F8 Ew=AX Eb=AL

C1 C9 01 09 E1 E9 F1 F9 EW=CX Eb=CL

C2 CA 02 OA E2 EA F2 FA Ew=OX Eb=OL

C3 CB 03 DB E3 EB F3 FB Ew=BX Eb=BL

C4 CC 04 DC E4 EC F4 FC Ew=SP Eb=AH

C5 CD 05 DO E5 ED F5 FO Ew=BP Eb=CH

C6 CE 06 DE E6 EE F6 FE Ew=SI Eb=OH

C7 CF 07 OF E7 EF F7 FF Ew=OI Eb=BH

NOTES:

1. 08 denotes an 8-bit displacement following the ModRM byte that is sign-extended and added to the index.

2. Default segment register is SS for effective addresses containing a BP index; OS is for other memory effective addresses.

3. 016 denotes the 16-bit displacement following the ModRM byte that is added to the index.

THE iAPX 286 INSTRUCTION SET

Ir Instruction Byte Format

imm.low(1) imm. high(1) disp-Iow disp-high

7 6 5 4 3 2

o

"mod" Field Bit Assignments

mod Displacement

00 OISP = 0(2), disp-Iow and disp-high are absent

01 DlSP = disp-Iow sign-extended to 16-bits, disp-high is absent 10 OISP = disp-high; disp-Iow

11 rIm is treated as a "reg" field

"r" Field Bit Assignments

16-Blt (w = 1) a-Bit (w = 0) Segment

000 AX 000 AL 00 ES

001 CX 001 CL 01 CS

010 OX 010 OL 10 SS

011 BX 011 BL 11 OS

100 SP 100 AH

101 BP 101 CH

110 SI 110 OH

111 01 111 BH

"r 1m" Field Bit Assignments

+

OISP

110 (BP)

+

DlSp(2)

111 (BX)

+

OISP

OISP follows 2nd byte of instruction (before data if required).

NOTES:

1. Opcode indicates presence and size of immediate field.

2. Except if mod=OO and r/m=110 then EA=disp-high: disp-Iow.

Figure B-2. Ir Instruction Byte Format

THE IAPX 286 INSTRUCTION SET

+rw: A register code from 0 through 7 which is added to the hexadecimal byte given at the left of the plus sign to form a single opcode byte. The codes are: AX=O, CX= 1, DX=2, BX=3, SP=4, BP=5, SI=6, and DI=7.

Instruction

This column gives the instruction mnemonic and possible operands. The type of operand used will determine the opcode and operand encodings. The following entries list the type of operand which can be encoded in the format shown in the instruction column. The Intel convention is to place the destination operand as the left hand operand. Source-only operands follow the destination operand.

In many cases, the same instruction can be encoded several ways. It is recommended that you use the shortest encoding. The short encodings are provided to save memory space.

cb: a destination instruction offset in the range of 128 bytes before the end of this instruction to 127 bytes after the end of this instruction.

cw: a destination offset within the same code segment as this instruction. Some instruc-tions allow a short form of destination offset.

See cb type for more information.

cd: a destination address, typically in a different code segment from this instruction.

Using the cd: address form with call instruc-tions saves the code segment selector.

db: a signed value between - 128 and

+

127 inclusive which is an operand of the instruc-tion. For instructions in which the db is to be combined in some way with a word operand, the immediate value is sign-extended to form a word. The upper byte of the word is filled with the topmost bit of the immediate value.

dw: an immediate word value which is an operand of the instruction.

eb: a byte-sized operand. This is e,ither a byte register or a (possibly indexed) byte memory variable. Either operand location may be encoded in the ModRM field. Any memory addressing mode may be used.

ew: a word-sized operand. This is either a word register or a (possibly indexed) word memory variable. Either operand location may be encoded in the ModRM field. Any memory addressing mode may be used.

m: a memory location. Operands in registers do not have a memory address. Any memory addressing mode may be used.

mb: a memory-based byte-sized operand. Any memory addressing mode may be used.

mw: a memory-based word operand. Any memory addressing mode may be used.

md: a memory-based pointer operand. Any memory addressing mode may be used.

rb: one of the byte registers AL, CL, DL, BL, AH, CH, DH, or BH.

rw: one of the word registers AX, CX, DX, BX, SP, BP,' SI, or DI.

xb: a simple byte memory variable without a base or index register. MOY instructions between AL and memory have this optimized form if no indexing is required.

xw: a simple word memory variable without a base or index register. MOY instructions between AX and memory have this optimized form if no indexing is required.

Dans le document MANUAL PROGRAMMER'S iAPX 286 (Page 196-200)