23 0
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9.1 INTERRUPT DESCRIPTOR TABLE Many different events may cause an inter-rupt. To allow the reason for an interrupt to be easily identified, each interrupt source is given a number called the interrupt vector. Up to 256 different interrupt vectors (numbers) are possible. See figure 9-1.
A table is used to define the handler for each interrupt vector. The Interrupt Descriptor Table (IDT) defines the interrupt handlers for up to 256 different interrupts. The IDT is in physical memory, pointed to by the contents of the on-chip IDT register that contains a 24-bit base and a 16-bit limit. The IDTR is normally loaded with the LIDT instruction by code that executes at privilege level 0 during system initialization. The IDT may be located anywhere in the physical address space of the iAPX 286.
Each IDT entry is a 4-word gate descriptor that contains a pointer to the handler. The
MEMORY
GATE FOR INTERRUPT I1n
GATE FOR INTERRUPT I1n-1
· ·
·
GATE FOR INTERRUPT # 1
GATE FOR INTERRUPT #0
"r"
II
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INTERRUPT DESCRIPTOR TABLE (lOT)
Figure 9-1. Interrupt Descriptor Table Definition
INTERRUPTS AND EXCEPTIONS
three types of gates permitted in the IDT are interrupt gates, trap gates (discussed in section 9.3), and task gates (discussed in section 8.5). Interrupt and task gates process interrupts in the same task, while task gates cause a task switch. Any other descriptor type in the IDT will cause an exception if it is referenced by an interrupt.
The IDT need not contain all 256 entries. A 16-bit limit register allows less than the full number of entries. Unused entries may be signaled by placing a zero in the access rights byte. If an attempt is made to access an entry outside the table limit, or if the wrong descriptor type is found, a general protection fault occurs with an error code identifying the invalid interrupt vector (see figure 9-2).
Exception error codes that refer to an IDT entry can be identified by bit 1 of the error code that will be set. Bit 0 of the error code is 1 if the interrupt was caused by an event external to the program (i.e., an external interrupt, a single step, a processor extension error, or a processor extension not present).
Interrupts 0-31 are reserved for use by Intel.
Some of the interrupts are used for
instruc-tion excepinstruc-tions. The IDT limit must be at least 255 to accommodate the minimum number of interrupts. The remaining 224 interrupts are available to the user.
9.2 HARDWARE INITIATED INTERRUPTS Hardware-initiated interrupts are caused by some external event that activates either the INTR or NMI input pins of the processor.
Events that use the INTR input are classified as maskable interrupts. Events that use the NMI input are classified as non-maskable interrupts.
All 224 user-defined interrupt sources share the INTR input, but each has the ability to use a separate interrupt handler. An 8-bit vector supplied by the interrupt controller identifies which interrupt is being signaled. To read the interrupt id, the processor performs the interrupt acknowledge bus sequence.
Maskable interrupts (from the INTR input) can be inhibited by software by setting the interrupt flag bit (IF) to 0 in the flag word.
The IF bit does not inhibit exceptions or interrupts caused by the INT instruction. The IF bit also does not inhibit processor exten-sion interrupts.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 lOT VECTOR 0 1
E X T
1 An event external to the program caused the exception (i.e, external interrupt, single step, processor extension error)
o An exception occurred while processing an instruction.
Figure 9-2. lOT Selector Error Code
INTERRUPTS AND EXCEPTIONS
The type of gate placed into the IDT for the interrupt vector will control whether other maskable interrupts remain enabled or not during the servicing of that interrupt. The flag word that was saved on the stack reflects the maskable interrupt enable status of the processor prior to the interrupt. The proce-dure servicing a maskable interrupt can also prevent further maskable interrupts during its work by resetting the IF flag.
Non-maskable interrupts are caused by the NMI input. They have a higher priority than the mask able interrupts (meaning that in case of simultaneous requests, the non-maskable interrupt will be serviced first). A non-maskable interrupt has a fixed vector (#2) and therefore does not require an interrupt further interrupted by other non-maskable interrupt requests until an IRET instruction is executed. Any further NMI requests are remembered by the hardware and will be serviced after the first IRET instruction. To prevent a maskable interrupt from interrupt-ing the NMI interrupt handler, the IF flag should be cleared either by using an interrupt gate in the IDT or by setting IF = 0 in the flag word of the task involved.
9.3 SOFTWARE INITIATED INTERRUPTS Software initiated interrupts occur explicitly as interrupt instructions or may arise as the result of an exceptional condition that prevents the continuation of program execu-tion. Software interrupts are not maskable.
Two interrupt instructions exist which explic-itly cause an interrupt: INT nand INT 3. The first allows specification of any interrupt vector; the second implies interrupt vector 3 (Breakpoint ).
Other instructions like INTO, BOUND, DIV, and IDIV may cause an interrupt, depending on the overflow flag or values of the operands.
These instructions have predefined vectors associated with them in the first 32 interrupts reserved by Intel.
A whole class of interrupts called exceptions are intended to detect faults or programming errors (in the use of operands or privilege levels). Exceptions cannot be masked. They also have fixed vectors within the first 32 interrupts. Many of these exceptions pass an error code on the stack, which is not the case with the other interrupt types discussed in section 9.2. Section 9.5 discusses these error codes as well as the priority among interrupts that can occur simultaneously.
9.4 INTERRUPT GATES AND TRAP GATES Interrupt gates and trap gates are special types of descriptors that may only appear in the interrupt descriptor table. The difference between a trap and an interrupt gate is whether the interrupt enable flag is to be cleared or not. An interrupt gate specifies a proced:ure that enters with interrupts disabled (i.e., with the interrupt enable flag cleared); structure as the call gates discussed in section 7.5.1. The selector and entry point for a code segment to handle the interrupt or exception is contained in the gate. See figure 9-3.
The access byte contains the Present bit, the descriptor privilege level, and the type identi-fier. Bits 0-4 of the access byte have a value of 6 for interrupt gates, 7 for trap gates. Byte
INTERRUPTS AND EXCEPTIONS
5 of the descriptor is not used by either of these gates; it is used only by the call gate, which uses it as the parameter word-count.
Trap and interrupt gates allow a privilege level transition to occur when passing control to a non-conforming code segment. Like a call gate, the DPL of the target code segment selected determines the new CPL. The DPL of the new non-conforming code segment must be less than or equal to CPL.
No privilege transition occurs if the new code segment is conforming. If the DPL of the conforming code segment is greater than the CPL, a general protection exception will occur.
As with all descriptors, these gates in the IDT carry a privilege level. The DPL controls access to interrupts with the INT n instruc-tion. For access, the CPL of the program must be less than or equal to the gate DPL. If the CPL is not, a general protection exception will result with an error code identifying the selected IDT gate. For exceptions and exter-nal interrupts, the CPL of the program is ignored while accessing the IDT.
Interrupts pointing to a trap or an interrupt gate are handled in the same manner as an iAPX 86 interrupt. The flags and return address of the interrupted program are saved on the stack of the interrupt handler. To return to the interrupted program, the inter-rupt handler executes an IRET instruction.
If a privilege transition is required for handling the interrupt, a new stack will be loaded from the TSS. The stack pointer of the old privilege level will also be saved on the new stack in the same manner as a call gate.
Figure 9-4 shows the stack contents after an exception with an error code (with or without a privilege level change).
If an interrupt or trap gate is used to handle an exception that passes an error code, the error code will be pushed onto the new stack after the return address (as shown in figure 9-4).
If an interrupt gate is used to handle an inter-rupt, it is assumed that the selected code segment has sufficient privilege to re-enable interrupts. The IRET instruction will not re-enable interrupts if CPL is numerically greater than IOPL.
+7 INTEL RESERVED' +6