Floating-Point Execution Models

All implementations of this architecture must provide the equivalent of the following execution models to insure that identical results are obtained.

Special rules are provided in the definition of the arithmetic instructions for the infinities, denormalized numbers and NaNs.

Although the double format specifies an 11-bit expo-nent, exponent arithmetic makes use of two additional bit positions to avoid potential transient overflow con-ditions. One extra bit is required when denormalized double-precision numbers are prenormalized. The second bit is required to permit the computation of the adjusted exponent value in the following cases when the corresponding exception enable bits is one:

• Underflow during multiplication using a denormal-ized factor.

• Overflow during division using a denormalized divisor.

Chapter 4. Floating-Point Processor 95

The IEEE standard includes 32-bit and 64-bit arith-metic. The standard requires that single-precision arithmetic be provided for single-precision operands.

The standard permits double-precision arithmetic instructions to have either (or both) single-precision or double-precision operands, but states that single-precision arithmetic instructions should not accept double-precision operands. The Power PC Architecture follows these guidelines: double-precision arithmetic·

instructions can have operands of either or both pre-cisions, while single-precision arithmetic instructions require all operands to be single-precision. . Double-precision arithmetic instructions produce double-precision values, while single-double-precision arithmetic instructions produce single-precision values.

For arithmetic instructions, conversions from double-precision to single-double-precision must be done explicitly by software, while conversions from single-precision to double-precision are done implicitly.

4.5.1 Execution Model for IEEE Operations

The following description uses 64-bit arithmetic as an example. 32-bit arithmetic is similar except that the FRACTION is a 23-bit field, and the single-precision Guard, Round, and Sticky bits (described in this section) are logically adjacent to the 23-bit FRACTION field.

IEEE-conforming significand arithmetic is considered to be performed with a floating-point accumulator having the following format:

FRACTION

o 1 52

Figure 31. IEEE 54-bit Execution Model The S bit is the sign bit.

The C bit is the carry bit that captures the carry out of the significand.

The L bit is the leading unit bit of the significand which receives the implicit bit from the operands.

The FRACTION is a 52-bit field which accepts the

The infinitely precise intermediate result of an opera-tion is the result normalized in bits L, FRACTION, G, R, and X of the floating-point accumulator.

Before the results are stored into an FPR, the significand is rounded if necessary, using the rounding mode specified by FPSCR_RN• If rounding results in a carry into C, the significand is shifted right one position and the exponent incremented by one.

This yields an inexact result and possibly also expo-nent overflow. Fraction bits to the left of the bit posi-tion used for rounding are stored into the FPR and low-order bit positions, if any, are set to zero.

Four rounding modes are provided which are double-precision and single-double-precision floating-point numbers.

Format Guard Round Sticky Double G bit R bit X bit

Single 24 25 26:52 G,R,X

Z1 and Z2, as defined on page 90, can be used to (result midway between closest repre-sentable values) then if the low-order bit specified precision, then the following action is taken:

Guard bit

=

Store infinity with the sign of the unrounded result.

Guard bit

=

Store the truncated (maximum magni-tude) value.

• Round toward Zero

Choose the smaller in magnitude of Z1 or Z2.

See "Rounding" on page 90 for the definitions of Z1 and Z2. If Guard, Round, or Sticky bit is non-zero, the result is inexact.

• Round toward +Infinity

Choose Z1. See "Rounding" on page 90 for the definition of Z1.

• Round toward -Infinity

Choose Z2. See "Rounding" on page 90 for the definition of Z2.

Where the result is to have fewer than 53 bits of pre-cision because the instruction is a Floating Round to Single-Precision or single-precision arithmetic instruc-tion, the intermediate result either is normalized or is placed in correct denormalized form before the result arithmetic is similar except that the FRACTION field is smaller.

The multiply-add operations produce intermediate results conforming to the following model:

FRACTION

IX'I·

o 1 105

Figure 34. Multiply-Add Execution Model

The first part of the operation is a multiply. The shift. The normalized result provides an intermediate result as input to the rounder which conforms to the model described in Section 4.5.1, "Execution Model for IEEE Operations" on page 96, where:

• The Guard bit is bit 53 of the intermediate result.

• The Round bit is bit 54 of the intermediate result.

• The Sticky bit is the OR of all remaining bits to the right of bit 55, inclusive.

The rules of rounding the intermediate result are the same as the described in Section 4.5.1, "Execution Model for IEEE Operations" on page 96.

If the instruction is Floating Negative Multiply-Add or Floating Negative Multiply-Subtract the final result is negated.

Chapter 4. Floating-Point Processor 97·

Status bits are set to reflect the result of the entire operation: e.g., no status is recorded for the result of the multiplication part of the operation.