Block Address Translation 174

The Block Address Translation (BAT) mechanism pro-vides a means for mapping ranges of virtual addresses larger than a single page onto contiguous areas of real storage. Such areas can be used for data that is not subject to normal virtual storage han-dling (paging), such as a memory-mapped display buffer or an extremely large array of numerical data.

12.7.1 Recognition of Addresses in

seg-mented address translation mechanism such that a particular Effective Address is within a BAT area and also is covered by page translation. When this happens, the BAT takes precedence over entries in the Segment Table or the content of a Segment Reg-ister (including the T bit).

Programming Note - - - , segment overlaid by the BAT.

The BAT areas are defined by pairs of SPRs. These SPRs can be read or written by the mfspr and mtspr instructions; see page 79 .. Access to these SPRs is privileged. The layout of the BAT registers is shown in figure 63 for 64-bit implementations and in figure 64 for 32-bit implementations.

Four pairs of BAT registers are provided for trans-lating instruction addresses ~the IBAT registers), and four pairs are provided for translating data addresses (the DBAT registers). registers such that an Effective Address is translated by more than one IBAT pair or by more than one address of a BAT area in Effective Address space, the length of the area, and the start of the corresponding area in Real Address space. If an Effective Address is within the range of EAs defined by a pair of BAT registers that is valid (see below) for the access, its Real Address is developed by (conceptually)

sub-BAT area defined is 256 MB (2²⁸ bytes). The starting address of a BAT area in both EA space and RA space must be a multiple of the area's length.

12.7.2 BAT Registers

See section "Move To Special Purpose Register XFX-form" on page 79 for a list of the SPR numbers for the BAT registers. See Appendix C, "Assembler Extended Mnemonics" on page 221 for a list of extended mnemonics for use with the BAT registers.

The equation for determining whether a BAT entry is valid for a particular access is:

BAT_entry_valid = (Vs &

~MSRpR)

I (Vp & MSRpR)

If a BAT entry is not valid for a given access, it does not participate in address translation for that access.

Two BAT entries may not map an overlapping effec-tive address range and be valid at the same time.

Programming Note - - - , Entries that have complementary settings of V s and V p may map overlapping effective address blocks. Complementary settings would be:

BAT entry A: Vs = 1, Vp = e

BAT entry B: Vs

=

8, Vp

=

1

The BL field in the upper BAT register is a mask that encodes the length of the BAT area.

BAT Area

Only the values shown are valid for BL The rightmost bit of BL is aligned with bit 46 {14} of the EA.

An Effective Address is determined to be within a BAT area if EA matches BEPI. The boundary between the

Protection bits for BAT area All other fields are reserved.

Figure 63. BAT Registers, 64-bit implementations BEPI: bits in EA corresponding to 1s in BL are forced to 0 for this comparison.

Bits in EA corresponding to 1 s in BL, concatenated with the 17 bits of EA to the right of .BL, form the offset within the BAT area.

0

30 Vs Supervisor state valid bit 31 Vp Problem state valid bit Lower 0:14 BRPN Block Real Page Number

25:28 WIMG Storage access controls Bit 28 is reserved in IBATs.

30:31 PP Protection bits for BAT area All other fields are reserved.

Figure 64. BAT Registers, 32-bit implementations

Chapter 12. Storage Control 175

~---36~---EA

BL

36 BRPN

~

T

36 11

1]

RA

Figure 65. Formation of Real Address via BAT, 64·bit implementations

12.7.2.1 BAT storage Protection

If an Effective Address is determined to be within a BAT area that is valid for the access, the access is next validated by the storage protection scheme described in section 12.10.2, "BAT Protection" on page 180. If this protection mechanism rejects the EA, a page fault (Data Storage interrupt or Instruction Storage interrupt) is generated.

12.7.2.2 BAT Real Address

If the protection mechanism accepts the access, then a Real Address is formed as shown in figure 65 for 64-bit implementations, and figure 66 for 32·bit imple-mentations.

Access to the real memory of the BAT area is made according to the storage mode defined by the "WIMG"

bits in the lower BAT register. These bits apply to the entire BAT area rather than to an individual page.

See 12.8.2, "Supported Storage Modes" on page 177

EA

BL

4 BRPN

~

T

4 11

1]

RA

Figure 66. Formation of Real Address via BAT, 32·bit implementations.

12.8 Storage Access Modes

When address relocation is enabled and the effective address generated by a storage access is translated by the Segmented Address Translation mechanism or by the Block Address Translation mechanism, the access is performed under the control of the Page Table Entry or BAT entry used to translate the effec-tive address. Each Page Table Entry or DBAT entry contains four mode control bits, W, I, M, and G, that specify the storage mode for all accesses translated by the entry. The IBAT entry contains the W, I, and M bits, but not the G bit. The Wand I bits control how the processor executing the access uses its own cache. The M bit specifies whether the processor executing the access must use the storage coherence protocol to ensure that all copies of the addressed storage location are made consistent. The G bit con-trols whether or not speculative data and instruction fetching is permitted. For an access translated by an IBAT entry, G is assumed to be O.

The mode control bits only have meaning when an

effective address is translated and have no direct relation to data in the cache, processors responding to the coherence request are able to respond without knowledge of the state of these bits.

12.8.1 W, I, M and G bits

Store combining optimizations are allowed except when the store instructions are con-troller to be written into the target RAM.

• I/O Adapter Card accessed location is not brought into the cache nor is the location allocated in the cache. It is

Load/store combining optimizations are allowed except when the accesses are kept consistent by hardWare, and in which soft-ware is able to enforce the required consist-ency. When the mode is off (M

=

0), the hardware need not enforce data coherence.

When the mode is on (M

=

1), the hardware must enforce data coherence. Because instruction storage need not be consistent with data storage, it is permissible for an imple-mentation to ignore the M bit for instruction fetches.

G Guarded Storage

If G

=

1, accesses to storage must conform to the restrictions described in Section 12.2.5,

"Speculative Execution" on page 157.

12.8.2 Supported Storage Modes

The combinations of the Write Through bit, the accesses and consistency operations for the block may be ignored when fetching the block, storing it back, or changing its state from shared to exclusive.

• W1M

=

001 use of the block before storing into it.

• WlM

=

⁰¹⁰

Caching is inhibited. The storage access goes to storage bypassing the cache. Hardware enforced storage consistency is not required.

Chapter 12. Storage Control 177

• WlM

=

⁰¹¹

Caching is inhibited. The storage access goes to storage bypassing the cache. Storage consist-ency is enforced by hardware.

• WlM

=

¹⁰⁰

1. Data may be cached.

2. Loads for which the target location is in the cache may use that copy of the location.

3. Stores must be written to main storage. The target location of the store may be cached and must be updated if there.

4. Exclusive ownership of the block containing the target location is not required for store accesses and consistency operations for the block may be ignored when fetching the block, storing it back, or changing its state from shared to exclusive.

• WlM

=

¹⁰¹

1. Data may be cached.

2. Loads for which the target location is in the cache may use that copy of the location.

3. Stores must be written to main storage. The target location of the store may be cached and must be updated if there.

4. Exclusive ownership of the block containing use of the block before storing into it.

• WlM

=

¹¹⁰

This mode would represent memory that is Write Through, Caching Inhibited, and Memory Coher-ence Not Required. This mode is not supported.

• WlM

=

¹¹¹

This mode would represent memory that is Write Through, Caching Inhibited, and Memory Coher-ence Required. This mode is not supported.

12.8.3 Mismatched WIMG Bits

Accesses to the same storage location using two effective addresses for which the Write Through mode (W bit) differs must meet the Memory Coherence requirements described in Part 2, "PowerPC Virtual Environment Architecture" on page 117.

12.9 Reference and Change

translation. Reference and change recording is not performed for translations due to BAT or for direct-store (T

=

1) segments.

The Rand C bits are set automatically by hardware or by software assist in conjunction with normal Page Table processing as follows:

Reference bit

As a result of page table processing for a storage access (load, store, or cache instruc-tion, or instruction fetch), the Reference bit may be set to 1 immediately or its setting may be because a reservation does not exist.

~hange Bit

Whenever a data store is executed successfully, as part of the TLB look-up procedure the executed and is allowed by the storage

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