Fixed-Point Processor Registers 151

Part 3. PowerPC Operating

11.3 Fixed-Point Processor Registers 151

The Special Purpose Registers are read and written via the mfspr (page 79) and mtspr (page 79) instructions. The descriptions of these instructions list the valid encodings of SPR numbers. Encodings not listed are reserved for future use or for use as implementation-specific registers.

Most SPRs are defined in other parts of this book; see the index to locate those definitions. Some SPRs are specific to an implementation. See Appendix

M,

"Implementation-Specific SPRs" on page 273 and Book IV, PowerPC Implementation. Features.

11.3 Fixed-Point Processor Registers

11.3.1 Data Address Register

The Data Address Register (DAR) is a 32-bit or 64-bit register depending on the version of the architecture implemented. See Sections 13.5.3, "Data Storage Interrupt" on page 194, and 13.5.6, "Alignment Interrupt" on page 196 ..

When an interrupt that uses the DAR occurs, the DAR is set to the effective address associated with the interrupting instruction. If the interrupt occurs in

32-bit mode, the high-order 32 bits of the DAR are set to O.

DAR

o 63 {31}

Figure 44. Data Address Register

11.3.2 Data Storage I nterrupt Status

·Register

The Data Storage Interrupt Status Register (DSISR) is a 32-bit register that defines the cause of Data Storage and Alignment interrupts. See Sections 13.5.3, "Data Storage Interrupt" on page 194 and 13.5.6, "Alignment Interrupt" on page 196.

DSISR

o 31

Figure 45. Data Storage Interrupt Status Register

11.3.3 Software-use SPRs

SPRGO through SPRG3 are 64-bit {32-bit} registers provided for operating system use.

SPRGO SPRG1 SPRG2 SPRG3

o 63 {31}

Figure 46. Software-use SPRs

The following list describes the conventional uses of SPRGO through SPRG3.

SPRGO

Software may load a unique real address in this register to identify an area of storage reserved for use by the first level interrupt handler. This area must be unique for each processor in the system,

Chapter 11. Fixed-Point Processor 151

SPRG1

This register may be used as a scratch register by the first level interrupt handler to save the content of a GPR. That GPR then can be loaded from SPRGO and used as a base register to save other GPR's to storage.

SPRG2

This register may be used by the operating system as needed.

SPRG3

This register may be used by the operating system as needed.

11.4 Fixed-Point Processor Privileged Instructions

11.4.1 Move To/From System Registers Instructions

The Move To Special Purpose Register and Move From Special Purpose Register instructions are described in Part 1, "PowerPC User Instruction Set Architecture" on page 1, but only at the level avail-able to an application programmer. In particular, no mention is made there of registers that can be accessed only in privileged state. A complete description of these instructions appears below.

Extended mnemonics

A set of extended mnemonics is provided for the mtspr and mfspr instructions so that they can be coded with the SPR name as part of the mnemonic rather than as a numeric operand. See Appendix C,

"Assembler Extended Mnemonics" on page 221.

Move To Special Purpose Register XFX-form

mtspr SPR,RS

I.

³¹

I.

^RS

I"

^spr ⁴⁶⁷

n = sp r S:9

II

^{Sp r O:4}

length(SPREG(n» 64 then SPREG(n)

(RS)

else

SPREG (n)

(RS

h2:63{O:31)

The SPR field denotes a Special Purpose Register, encoded as shown in Figure 47 on page 153. The contents of register RS are placed into the designated Special Purpose Register. For Special Purpose Regis-ters that are 32 bits long, the low-order 32 bits of RS are placed into the SPR.

For this instruction, SPRs TBl and TBU are treated as separate 32-bit registers; setting one leaves the other unaltered.

spro= 1 if and only if writing the register is privileged.

Execution of this instruction specifying a defined and privileged register when MSR_pR=1 will result in a Privileged Instruction type Program interrupt.

Additional values of the SPR field, beyond those shown in Figure 47 on page 153, may be defined in Book IV, PowerPC Implementation Features for the implementation (see also Appendix M,

"Implementation-Specific SPRs" on page 273). If the SPR field contains any value other than one of these implementation-specific values or one of the values shown in the Figure, the instruction form is invalid.

However, if MSRpR

=

1 then the only effect of exe-cuting an invalid instruction form in which spro= 1 is to cause either a Privileged Instruction type Program interrupt or an Illegal Instruction type Program inter-rupt.

Special Registers Altered:

See Figure 47 on page 153

Compiler and Assembler Note - - - , For the mtspr and mfspr instructions, the SPR number coded in assembler language does not appear directly as a 10-bit binary number in the instruction. The number coded is split into two 5-bit halves that are reversed in the instruction,

SPR1 Register

1 Note that the order of the two 5-bit halves of the SPR number is reversed.

2 64-bit implementations only.

Figure 47. SPR encodings for mtspr

Programming Note - - - . For a discussion of software synchronization requirements when altering certain Special.

Purpose Registers, please refer to Appendix L,

"Synchronization Requirements for Special Registers" on page 269.

Compatibility Note - - - , For a discussion of Power compatibility with respect to SPR numbers not shown in the instruc-tion descripinstruc-tions for mtspr and mfspr, please refer to the "Incompatibilities with the Power Architec-ture" appendix of Part 1, "PowerPC User Instruc-tion Set Architecture" on page 1. For compatibility with future versions of this architec-ture, only SPR numbers discussed in these instruction descriptions should be used.

Move From Special Purpose Register XFX-form

contents of the designated Special Purpose Register are placed into register RT. For Special Purpose Reg-isters that are 32 bits long, the low-order 32 bits of RT receive the contents of the Special Purpose Register and the high-order 32 bits of RT are set to zero.

spro

=

1 if and only if reading the register is

PrIVI-leged. Execution of this instruction specifying

a

defined and privileged register when MSR_pR

=

1 will result in a Privileged Instruction type Program inter-rupt.

Additional values of the SPR field, beyond those shown in Figure 48 on page 154, may be defined in Book IV, PowerPC Implementation Features for the implementation (see also Appendix M,

However, if MSR_pR= 1 then the only effect of exe-cuting an invalid instruction form in which spro= 1 is to cause either a Privileged Instruction type Program interrupt or an Illegal Instruction type Program inter-rupt.

Special Registers Altered:

None

Compiler/Assembler/Compatibility Notes See the Notes that appear with mtspr.

Chapter 11. Fixed-Point Processor 153

SPR1 Register Privi-decimal spr 5:9 spr 0:4 name leged

1 0000000001 XER no

8 0000001000 LR no

9 0000001001 CTR no

18 00000 10010 DSISR yes

19 00000 10011 DAR yes

22 00000 10110 DEC yes

25 00000 11001 SDR1 yes

26 00000 11010 SRRO yes

27 00000 11011 SRR1 yes

272 01000 10000 SPRGO yes

273 01000 10001 SPRG1 yes

274 01000 10010 SPRG2 yes

275 01000 10011 SPRG3 yes

280 01000 11000 ASR 2 yes

282 01000 11010 EAR yes

287 01000 11111 PVR yes

528 10000 10000 IBATOU yes

529 10000 10001 IBATOL yes

530 10000 10010 IBAT1U yes

531 10000 10011 IBAT1L yes

532 10000 10100 IBAT2U yes

533 10000 10101 IBAT2L yes

534 10000 10110 IBAT3U yes

535 10000 10111 IBAT3L yes

536 10000 11000 DBATOU yes

537 10000 11001 DBATOL yes

538 10000 11010 DBAT1U yes

539 10000 11011 DBAT1L yes

540 10000 11100 DBAT2U yes

541 10000 11101 DBAT2L yes

542 10000 11110 DBAT3U yes

543 10000 11111 DBAT3L yes

1 Note that the order of the two 5-bit halves of the SPR number is reversed.

264-bit implementations only.

Moving from the Time Base (TB and TBU) is accomplished with the mftb instruction, descri bed in Book II.

Figure 48. SPR encodings for mfspr

Move To Machine State Register X-form

mtmsr RS

10

³¹

Is

^RS

¹¹¹

^III

I

^III

I

• " 16 21

146

1:,1

MSR

(RS)

The contents of register RS are placed into the MSR.

This instruction is privileged and execution synchro-nizing.

In addition, alterations to the EE and RI bits are effec-tive as soon as the instruction completes. Thus if MSR_{EE =}0 and an External or Decrementer interrupt is pending, executing an mtmsr instruction that sets MSR_EEto 1 will cause the External or Decrementer interrupt to be taken before the next instruction is executed.

Special Registers Altered:

MSR

Programming Note - - - . . . , For a discussion of software synchronization requirements when altering certain MSR bits, please refer to Appendix L, "Synchronization Requirements for Special Registers" on page 269.

Move From Machine State Register X-form

mfmsr RT

10

³¹

Is

^RT

¹¹¹

^III

I

^III

I

• • 16 21

RT

MSR

The contents of the MSR are placed into RT.

This instruction is privileged.

Special Registers Altered:

none

1 :,1

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