FIGURE 3-44. PULSE WIDTH MODULATION

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3-51

3.4.11 Index PCB

INDX detects pack index, and provides outputs used in data precompensa-tion and VFO operaprecompensa-tion, as described below.

3.4.11.1 Detecting Index

Index is a fixed pattern of gaps in the servo data. Each gap consists of two missing dipulses. Referring to the timing chart in Figure 3-45 and the logic block diagram in Figure 3-46, index is detected as follows:

• Gaps are detected by two latches that comprise the Gap Detector. Both are reset by the NORed result of POS DET and NEG DET, and clocked by the ORed result of GATE POS and GATE NEG. If the first latch is set, the second is set. A positive output from the second latch indicates detection of two misSing dipulses, which defines a single index gap.

• When an index gap is detected, a zero is shifted into a 6-bit Shift Register.

• The index pattern is decoded (INDEX is true) by Index Decode in the index window. If not decoded in the index window, or if decoded outside the index window, INDEX ERROR is generated.

3.4.11.2 Block TK SW

Block TK SW is used to prevent inverting the output of the Servo Preamp (controlled by the cylinder even latch on the SVTL PCB) and to prevent current switching in the velocity mode during the time the index gaps are being detected by the servo head.

3.4.11.3 Generating PLO Outputs

PlO and Clock Circuits (Figure 3-46) generate outputs used in write precompensation and VFO operation, as described in paragraph 3.3.5.1.

3.4.11.4 Checking for Power Failure

Power Fail Logic (Figure 3-46) generates an indication of unsafe voltage if present, as described in paragraph 3.3.5.2.

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FIGURE 3-45. SERVO CLOCKING FOR INDEX

3.4.11.5 INDX Performance Requirements

Index requirements are presented below (refer to figure 3-46).

a. When either on track or seeking between tracks using a standard disc pack, INDEX is detected and INDEX ERROR is false.

b. INDEX is true every 16.67 ± 0.33 msec. Duration of INDEX true is 620 ± 100 nsec.

c. SECTOR CLOCK true has a nominal period of 1.24 J.J.sec, and occurs 13,440 times between true transitions of INDEX.

d. INDEX ERROR is true when the heads are retracted.

e. If INDEX does not occur during INDEX WINDOW TP, or occurs outside of INDEX WINDOW TP, INDEX ERROR becomes true and remains true until INDEX occurs during INDEX WINDOW TP.

3-52

IPUT

3.4.12 Servo Control PCB

Using indicators of Servo System status, control panel status, and DCL commands of the drive, SVTL provides for a logical progression of servoing events as needed to control system operations. It enables seek or recalibrate operations and the servo power amp, detects an incomplete seek or servo error, permits velocity or position control, terminates velocity control, and, depending on system status, either initiates, delays, or resets the system ready-to-operate indication. In addition, SVTL sends system status in-dicators to data safety circuits (DSHS), spindle control circuits (SEOU), and the DCL (via OPUT).

Figure 3-47 shows the sources of inputs to SVTL (left side of figure), destinations of outputs generated (right side), and SVTL logic divided into nine functional segments (middle portion of figure). Dividing the logic into segments, each defining a particular control state of the system, provides the basis used to organize the description of SVTL which follows. This figure allows orientation to the servo control states, and provides a single reference for all SVTL inputs and outputs.

As shown m Figure 3-47, segments of logic receive inputs from external and internal sources, the latter including timers in most cases. Six timers are used; they are described in Figure 3-48. All are retriggerable one shots.

Since a false-to-true transition in the input logic to each one shot restarts its timing cycle, input conditions cannot be ignored (may change) during timeout of anyone shot. AddreSSing changing conditions in the design allows servoing in the shortest time. (For this reason, mechanical events occurring at the end of the six timeout periods, while the system progresses from one control state to another, are variable to the degree that a discussion would have little general value.)

In the following paragraphs, each segment of logic shown in Figure 3-47 is described, addressing the outputs generated (except timer outputs, which are addressed above) while the system progresses from one control state to another.

3.4.12.1 Enabling Servo Logic

Seek Enable Logic (Figure 3-47) generates SERVO LOGIC ENABLE, which must be true to enable all other segments of servo control logic to operate.

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As shown in Figure 3-49, SERVO LOGIC ENABLE is latched true when the drive is prepared for normal operation (SEEK ENABLE is true), and Timers T2 and T6 have been tested.

The system can arrive at a disable state from any other state by dropping SEEK ENABLE. It can leave the disable state only by the logic raising SEEK ENABLE. When raised, the system enters a test state. At this time, T1, T2, and T6 are started. After T2 and T6 have timed out, correct timer operation is assured.

3.4.12.2 Enabling Rezeroing

Rezero Logic generates DO REZERO, which must be true to enable a recalibrate operation. Referring to Figure 3-47, this operation can be executed by enabling the power amp, enabling the velocity servo, and completing a seek to track 000.

As shown in Figure 3-49, DO REZERO is latched true when a head load is initiated, the LAP plug is removed and replaced, a rezero start is received, or a servo error is detected.

3.4.12.3 Enabling Velocity Control

Velocity Servo Enable Logic (Figure 3-47) generates VELOCITY ENABLE.

As shown in Figure 3-50, DO REZERO being true starts T1 and T2, setting the Velocity Enable latch. VELOCITY ENABLE is latched true when T6 is additionally started (servo logic is enabled), provided the difference count is not zero and the latch is not reset by STOP VELOCITY.

VELOCITY ENABLE may be true with heads retracted or extended.

3.4.12.4 Stopping Velocity Control

Velocity Stop Logic (Figure 3-47) generates STOP VELOCITY, which becomes true when the carriage has effectively stopped, and stopping terminates the Velocity Control mode.

Refer to Figure 3-50. Unless blocked by T3 or T4, STOP VELOCITY is latched true when carriage motion is so slow (0.5 in/sec) that switching to the Position Control mode is indicated (SW VEL DET is true).

3-54

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