M In 0 0
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M In 0 0
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absolute maximum ratings
(V+
-Supply Voltage and V ) ±18V
Gate Input Voltage (V6 and V7 ) ±20V
Analog Input Voltage (V4 ) ±15V
Input Current (Is and Is) ±10 mA
Power Dissipation l,5W
Output Short Circuit Duration Continuous
Operating Temperature Range
LH0053 -55°C to +125°C
LH0053C -25°C to +85°C
Storage Temperature Range -65°C to +150°C
Lead Temperature (Soldering, 10 seconds) 300°C
electrical cha racteristics
(Note 1)LIMITS
PARAMETER CONDITIONS lH0053 lH0053C UNITS
MIN TYP MAX MIN TYP MAX
Sample (Gate "0") 05 0.5 V
Input Voltage
Sample (Gate "0 'I V6 ~ O.SV, T A = 25°c 5.0 -5.0 "A
Input Current Vs = 0.5 -100 -100 "A
Hold (Gate "1 ") 4.5 45 V
Input Voltage
Hold (Gate "1") Vs = 4.5V, T A '" 2SoC 10 10 "A
Input Current Vo '" 4.5V 10 10 "A
Analog Input .±10 ' I I ±1O ± 11 V
Voltage Range
Supply Current V4 = OV 13 18 13 18 mA
V6 '-'D.5V
Input Bias Current V 4 = OV, T A = 25°C 120 250 150 500 "A
11.1
Input Resistance 9.0 10 11 9.0 10 11 k£l
Analog Output RL = 2.0k +10 +12 '10 ±12 V
Voltage Range
Output Offset V4 '" OV, Vs = O.SV, TA = 25°C 5.0 7.0 5.0 10 mV
Voltage V4 = OV, Vs '" O.SV 10 15 mV
Sample Accuracy V4 = ±lOV, Vs = O.5V, T A = 2S"C 01 0.2 01 0.3 %
(Note 2)
Aperture Time !J.V6 = 4.5V, T A = 2SoC 10 25 10 25
n,
Sample Acquisition V4",±lOV, TA .;2S"C, 5.0 10 80 15
"'
Time CF "" 1000 pF
Sample Acquisition V4 =±lOV, TA """ 2SoC, 4.0 4.0
"'
Time CF = 100 pF
Output Slew Rate ilV1N =±10V, TA = 25"C, 20 20 V/jJ.~
CF = 1000 pF
Large Signa) V4 ::: ±10V, TA "" 25"C, 200 200 kHz
Bandwidth CF = 1000 pF
Leakage Current V4 =±10V, TA = 25°C, 6.0 30 10 50 pA
(pin 5) V4 = ±10V 30 30 "A
Drift Rate V4=±10V,TA:"·25"C, 6.0 30 10 50 mV/s
C, " 1000 pF
Drift Rate V4=±10V,CF =1000pF 30 30 Vis
Q2Switch ON V7 "'O.5V, 18 ==1.0mA.TA :::25"C 100 300 100 300 1/
Resistance
Note 1: Unless otherwise noted, these specifications apply for Vs = ±15V, pin 9 grounded, a 1000 pF capacitor between pin 5 and pin 11, pin 3 shorted to pin 11, over the temperature range -55°C to +125"C for the LH0053 and -25"C to +-85"C for the LH0053C. All typical values are for T A = 25°C.
Note 2: Sample accuracy may be nulled by inserting a potentiometer in the feedback loop. This compensates for source impedance and feedback resistor tolerances.
typical performance characteristics
Power Dissi pation
I"\.
STilL AIR~'TH
I _I nput Bias Current
J
s = ~'5~V3=OV
,
r--!-
-Supply Current vs Temperature 15 TEMPERATURE rCI
Drift
TEMPERATURE reI TEMPERATURE re)
Sample Acquisition Time Output Slew Rate
+1D
typical applications
- - - ,
5Increasing Output Drive Capability
20
Output Current Limiting
f-J,=1±15~
Leakage Current at Pin 5 FVs -'15V
V
f-25
25 50 75 100 125
TEMPERATURE ("el
Acquisition Time vs Temperature
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3-12
typical applications (con't)
"
5 IOOUpl
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Sample and Hold with Reset
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Preset Integrator
applications information
SOURCE IMPEDANCE COMPENSATION The gain accuracy (linearity) of the LH00531 LH0053C is set by two internal precision resistors.
Circuit applications in which the source impedance is non-zero will result in a closed loop gain error, e.g. if Rs = lOn, a gain error of 0.1% results.
Figure 1 and 2 show methods for accommodating non-zero source impedance.
DRIFT ERROR MINIMIZATION
In order to minimize drift error, care in selection CF and layout of the printed circuit board is required. The capacitor should be of high quality teflon, polycarbonate or polystyrene construction.
Board layout and clean lines are critical particularly at elevated temperature.
A ground guard (shield) surrounding pin 5 will minimize leakage currents to and from the summing junction, arising from extraneous signals. See AN-63 for detailed recommendations.
CAPACITOR SELECTION
The size of the capacitor is determined by the required drift rate usually at the expense of acquisition time.
The drift is dictated by leakage current at pin 5 and is given by:
dv IL
dt CF
Where I L is the leakage current at pin 5 and CF
is the value of the capacitance. The room tempera·
ture leakage of the LH0053 is typical 6.0 pA, and a 1000 pF capacitor will yield a drift rate of 6.0 mV per second.
For values of CF below 1000 pF acquisition for the LH0053 is primarily governed by the slew rate of the input amplifier (200V Ills) and the setting time of output amplifier (:= 1.0Ils). For values above CF = 1000 pF, acquisition time is given by:
Where:
CF = The value of the capacitor f1 V = The magnitude of the input step;
e. g. 20V
loss = The ON current of switch Ql := 5.0 mA
tS2 = The setting time of output amplifier := 1.01ls
applications information (con't)
r- ,,---
JFIGURE 1. Non-Zero Source Impedance Compensation
FIGURE 2. Non-Zero Source Impedance Buffering
GATE INPUT CONSIDERATIONS 5.0V TTL Applications
The LH0053 Gate inputs Gate 1 (pin 61 and Gate 2 (pin 71 will interface directly with 5.0V TTL.
However, TTL gates typically pull up to 2.5V in the logic "1" state. It is therefore advisable to use a 1 Ok pull·up resistor between the 5.0V, Vee, and the output of the gate as shown in Figure 3.
'"
(iATE 54/14
I HOU53
FIGURE 3. TTL Logic Compatibility CMOS Applications
The LH0053 gate inputs may be interfaced directly with 74C, CMOS operating off of Vee's from 5.0V to 15V. However transient currents of several milliamps can flow on the rising and falling edges of the input signal. It IS, therefore, advisable to parallel the outputs of two 54C174C gates as shown in Figure 4.
It should be noted that leakage at pin 5 in the hold mode will be increased by a facto! of 2 to 3 when operating into 15V logic levels.
Unused Switch, Q2
In applications when switch Q2 is not used the logic input (pin 71 should be returned to +5.0V (or +15V for HTL applicationsl through a 10kD resistor. Analog Input, preset (pin 81 should be grounded.
IIcc 5_011 TO 15V
FIGURE 4. CMOS Logic Compatibility
HEAT SINKING
The LH0053 may be operated over the military temperature range, -55°C to +125°C, without incurring damage to the device. However, a clip on heat sink such as the Wakefield 215 Series or Thermolloy 2240 will reduce the internal tempera·
ture rise by about 20°C. The result is a two·fold improvement in drift rate at temperature.
3·13
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3-14
applications information (con't)
Since the case of the device is electrically isolated from the circuit, the LH0053 may be mounted directly to a grounded heat sink.
POWER SUPPLY DECOUPLING
Amplifiers Aland A2 within the LH0053 are very wide band devices and are sensitive to power supply inductance. It is advisable to by-pase V I (pin 121 and V- (pin 101 to ground with O.lf.1F disc
capacitors in order to prevent oscillation. Should this procedure prove inadequate, the disc capacitors should be paralled with 4.7f.1F solid tantalum electrolytic capacitors.
DC OFFSET ADJUST
Output offset error may be adjusted to zero using the circuit shown in Figure 5. Offset null should be accomplished in the sample mode (V6 -:<::: O.5V) and analog input (pin 41 equal to zero volts.
FIGURE 5. Offset Null Circuit
definition of terms
Voltage, V4 : The voltage at pin 4, i.e., the analog input Voltage.
Voltage, V6: The voltage at pin 6, i.e., the logic control signal. A logic "1" input, V 6 -:<::: 4.5V, places the LH0053 in the HOLD mode; a logic
"0" input (V 6 -:<::: 0.5VI places the device in sample mode.
Acquisition Time: The time required for the output (pin 111 to settle within the rated accuracy after a specified input change is applied to Analog Input 1
(pin 4) with logic inpu't, Gate 1, (pin 61 in the logic "0" state.
Aperture Time: The time indeterminacy when switching from the "sample" mode to the HOLD mode measured from time the logic input passes through it's threshold (2.OV) to the time the device actually enters the HOLD mode.
Sample Accuracy: Difference between Input volt-age and outp~t voltage while in the sample mode, expressed as a petcent of input Voltage.