CONTROL STORE

Figure 9·1 shows the format of the KDl l·B control store (eS) word.

^Th~re

are 256 such words. each having the same fields. The fields, the possible values they may contain, and the significance of each value are described in

Table 9·1. The CS is shown on prints CONF and CONGo .

An explanation of the notation will aid in relating the es word to the reset of the print set. Each field within the C8 has been given a name (e.g., BUT, BRG, ALG, ..• ,ALU, NXT). These field names are -used throughout documentation of the microprogram.

The signal coming from each bit is named according to the convention used in the print set. Note that several signals may be associated with a single field (e.g., the BUT field controls four signals: CONG BUT 01 L, eONG BUT 00 L, CONG BUT 02 L, and eONG BUT 03 L).

9·1

CONG ALLOW BYTE L

Figure 9·1 Control Store Word Bit and Field Format

Table 9·1

KDll·B Control Store Fields

Description

Branch on microtest. The BUT field has two uses: a) specify microprogram con·

ditional branches, and b) as an encoded miscellaneous field. The values this field can assume are grouped by these two uses.

Branching within the microprogram is accomplished by wiring conditional signals with the open·collector outputs of the NXT field of the CS. Each BUT condition has the minimum number of control bits required. This makes the range of branch·

ing restrictive, but it minimizes logic (print CONE). Table 9·2 lists the microstep in which each BUT is performed, the possible conditions, and resulting destination of the microprogram branch.

Microprogram conditional branches:

No effect

9·2

Field

BUT JSRMP

(Cont)

IRD

BYT

DST MOV

INT UNY

SW NMD

SRV

CON INI SVS ENO IRC BRG

H L SR SL ALG

Table 9-1 (Cont) KDII-B Control Store Fields

Description Microprogram branch on JMP or JSR instruction

Microprogram branch on results of Instruction Register Decode

Microprogram branch to distinguish: a) byte and non-byte instructions, and b) odd/even byte references

Microprogram branches on destination mode IR (5 :3)

Microprogram branch to distinguish both MOV and MOVB from other in-structions

Microprogram branch on interrupt to be processed Microprogram branch to distinguish unary instructions Microprogram branch dependent on console switch action

Microprogram branches to distinguish non-modifying instructions (e.g., eMP, TST, etc.)

Microprogram branch at end of instruction sequence to determine if any condition requires service before going off to fetch next instruction

Miscellaneous encoded field:

Enable the constants ROM on the A-leg

Trigger BUS IN IT L during the RESET instruction Set SSYN on Unibus during the interrupt sequence Enable the stack overflow detection logic

Clock data into the instruction register Control the B register

Hold, do not modify.

Load.

Shift right once.

Shift left once.

A-leg control; determines what is enabled onto the A-inputs of the ALU

9-3

Field

ALG ^SP

(Cont)

NUL SPR PSW TNS

NON

o

IP ABT

NO YES CKO

OFF ON SPA

SPF

REA WRI BLG

Table 9·1 (Cont) KDll·B Control Store Fields

Description Scratch pad

Nothing

Low orders eight bits (right half) of the scratch pad Program Status Word

Initiation of Unibus transfer No effect

Initiate DATI Initiate DATO Initiate DATIP

Allow byte reference on current Unibus transfer.

Inhibit the processor clock until pending Unibus transfer is complete.

No effect

Scratch pad address. This field is physically split in the control store word. It is made up of:

SPA = SPO = CS (I 8) SPl

=

^{CS (22)}

SP2 = CS (12) SP3 = CS (21)

Scratch pad address (RO through R17) Scratch pad control function

Scratch pad contents not modified Write into scratch pad

B.leg control. Determines what is enabled onto the B-input of the ALU. This field is physically split in control store word.

94

Field BLG

(Cont)

BRG SEX

+1

BAR

H L SAM

ROM

IRS

IRD

BAR

PSW

H L

AUX

OFF ON CRI

OFF ON

Table 9-1 (Cont) KDll-B Control Store Fields

Description BLG

=

BTP (B Top - Upper Byte)

=

^{CS (14)}

BBT (B Bottom - Lower Byte) = CS

(16)

B register

B register sign extended. Bit

7

of the B register is propagated from bit

7

to bit

15.

The constant

Bus Address Register Control Hold, do not modify.

Load.

Scratch pad address multiplexer control. This field is physically split in the control store word.

SAM

=

^SMO

⁽¹⁹⁾

SMt (17)

Scratch pad address taken from control 'store word (see SPA field)

Scratch pad address taken from source register bits of Instruction Register, IR (8:6).

Scratch pad address taken from destination register bits of Instruction Register, IR (2:0).

Scratch pad address taken from Bus Address Register low order three bits, BA (2:0).

Program Status Word control Hold

Load

Auxiliary ALU control enabled

Enable carry in to ALU

9-5

Table 9-1 (Cont) KD11-B Control Store Fields

Field Description

ALU ALU function

AL A logical

AA A arithmetic

AB AandB

ABBAR A and ones complement of B

ZERO Output zero

AORB AorB

BL B logical

A+B A plus B

AXORB A exclusive or B

A-B-l A minus B minus 1

BBAR 1 's complement of B

-1 Output the constant minus one

A-I A minus one

ABAR 1 's complement of A

ASL Arithmetic shift B left

These are used during shift and

ROL Rotate B left rotate instructions to control

the serial shift inputs to the

ASR Arithmetic shift Bright B register.

ROR Rotate Bright

A field may contain anyone of a number of different alternative bit patterns. To facilitate microprogramming, these alternatives have been given symbolic names, making it possible to work with the microprogram at a symbolic level rather than in binary. For example (Table 9-1), one of the alternative values that can be assigned to the ALU field is OR (A or B). This value corresponds to a bit pattern of 01001 [CS (37:33) = 01001] .

The data word output from the CS is determined by the contents of the MPC registers (E091 and E I 02 shown on print CONF).

9-6

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