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8.10 Bus Arbitration
The SH microprocessor can release the bus to external devices when they request the bus. It has two internal bus masters, the CPU and the DMAC. Priorities for releasing the bus for these two are as follows.
Bus request from external device> DMAC > CPU
Thus, an external device has priority when it generates a bus request, even when the DMAC is doing a burst transfer.
Note that when a refresh request is generated while the bus is released to an external device, BACK becomes high level and the bus right can be acquired to perform the refresh upon receipt of a BREQ
=
high level response from the external device. Input all bus requests from external devices to the BREQ pin. The signal indicating that the bus has been released is output from the BACK pin. Figure 8.35 illustrates the bus release procedure.SH microprocessor External device
Bus request BREQ received
Strobe pin:
High-level output
'-_A_d_d_re_s,,-s'_d_a.,.ta_, _st_ro_b_e_p_in_:...J BACK / _ _ BA_C_K_a_ck"",n_o_W,,-le_d_g_e_.
High Impedance / r
Bus release response
Bus released
Figure 8.35 Bus Release Procedure
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8.10.1 The Operation of Bus Arbitration
This LSI has the bus arbitration function which can give bus ownership to an extemal device when the device requests the bus ownership. When BREQ is input and the bus cycle being executed by the CPU or DMAC is completed, BACK becomes low and a bus is released for an external device.
At this time, the following operates when bus arbitration conflicts with refresh.
1. If DRAM refresh is requested in this LSI when a bus is released and BACK is low, BACK becomes high and the occurrence of the refresh request can be informed externally. At this time, the external device may generate a bus cycle when BREQ is low even if BACK is high.
Therefore, a bus remains released to the external device. Then, when BREQ becomes high, this LSI gets bus ownership, and executes refresh and the bus cycle of the CPU or DMAC.
After the external device gets bus ownership and BACK is low, refresh is requested when BACK becomes high even if the low level of BREQ is input. Therefore, tum BREQ high immediately to release a bus for this LSI to hold DRAM data (See figure 8.36).
2. When BREQ changes from high to low and internal refresh is requested at the timing of the bus release of this LSI, BACK may remain high (do not become low). A bus is released to the external device since the low level of BREQ is input. This operation is based on the above specification (1). To hold DRAM data, tum BREQ high and release a bus to this LSI immediately when the external device detects that BACK does not change to low during a fixed time this LSI (See figure 8.37). When a refresh request is generated and BACK returns to high, as shown in figure 8.37, a momentary narrow pulse-shaped spike may be output where BACK was originally supposed to become low.
j
{
'-.\~_-....J~
- Refresh execution ~
Refresh damand
Figure 8.36 BACK Operation by Refresh Demand (1)
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In case BACK does not become low level during a fixed period, {
return BREQ to high level once.}
.... .
----
,...---t V______
BACK = does not become low level.Refresh dam and
Figure 8.37 BACK Operation by Refresh Demand (2)
8.11 Usage Notes
8.11.1 Usage Notes on Manual Reset
Condition: When DRAM (long-pitch mode) is used and manual reset is performed.
The low width of RAS output may be shorter than usual in reset (2.5 tcyc ~ 1.5 tcyc), causing the specified value (tRAS) of DRAM not to be satisfied.
Corresponding DRAM conditions: long pitch/normal mode
long pitchlhigh-speed page mode There are no problems regarding operations except for the above conditions.
There are the following four cases (Figure 8.38 to Figure 8.41) for the output states of DRAM control signals (RAS, CAS, and WR) corresponding to RES latch timing. Actual output levels are shown by solid lines (not by dashed lines).
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CK
RES
AOto A21
RAS CAS WR ADO to AD15
CK
RES
AO to A21
WR ADO to AD15
Tp Tr Tc1 Tc2
I I
Data
oufpuT---Figure 8.38 Long - pitch Mode Write (1)
' .. _______ I'
---, I I - - - - "
---4C)r---~(~\_-_-
__ -_-__ -_-_- __
-)r---Data output
Figure 8.39 Long ~ pitch Mode Write (2)
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Tp Tr Tc1 Tc2
CK RES
AOtoA21---~·r---~~--~~~--~~,r---4---\
---, '
'----I. _________ }
Figure 8.40 Long - pitch Mode Read (1)
CK
RES Manual reset
AO to A21
RAS
,
-'
CAS \
---, '
RD
J , ,
' .. _
.. ----
- ---- --'
Figure 8.41 Long - pitch Mode Read (2)
For the signal output shown by solid lines, DRAM data may not be held. Therefore, when DRAM data must be held after reset, take one of the countermeasures described as follows.
1. When resetting manually, do this in watchdog timer (WDT) condition.
2. Even if the Low width of RAS becomes as short as 1.5 tcyc as shown above, use with a frequency that satisfies the DRAM standard (tRAS).
3. Even in case the Low width of RAS has become 1.5 tcyc, proceed by using the external circuit so that a RAS signal with a Low width of 2.5 tcyc is input in the DRAM (in case the Low width of RAS is higher than 2.5 tcyc, operate so that the current waveform is input in the DRAM).
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The countermeasures are not required when DRAM data is initialized or loaded again after manual reset.
8.11.2 Usage Notes on Parity Data Pins DPH and DPL
The following specifies the setup time tos of the parity dada DPH and DPL to CAS signal rising when the parity dada DPH and DPL are written to DRAM in long-pitch mode (early write).
Table 8.12 Setup time of Parity Data DPH and DPL
Hem Symbol Min
Data setup time to CAS tos -5ns
(for only DPH and DPL in long-pitch mode)
Therefore, when writing parity data DPH and DPL to the DRAM in long-pitch mode, delay the WRH and WRL signals of this LSI and write with delayed writing. Normal data is also delay-written, causing no problems.
SH Micro- RAS computer CAS
AD
WRHorWRL
--[:>o{:>o-
DCK
,..
"
p*2Notes: 1. For preventing signal racing 2. Negative edge latch
a
DWRHorDWRLa P
Figure 8.42 Delayed-Write Control Circuit
RAS DRAM
CAS OE WE
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