~ space iiOn chip
8.4 Accessing External Memory Space
In external memory space, strobe signal is output based on the assumption of a directly connected SRAM. The external memory space is allocated to the following areas:
• Area 0 (when MD2-MDO are 000 or 001)
• Area 1 (when the DRAM enable bit (DRAME) of the BCR is 0)
• Areas 2-4
• Area 5 (space where address A27 is 1)
• Area 6 (when the multiplexed 110 enable bit (IOE) bit of the BCR is 0, or space where address A27 is 0)
• Area 7 (space where address A27 is 0) 8.4.1 Basic Timing
The bus cycle for external memory space access is 1 or 2 states. The number of states is controlled with the wait states by the settings of wait state control registers 1-3 (WCR l-WCR3). For details, see section 8.4.2., Wait State Control. Figures 8.11 and 8.12 illustrate the basic timing of external memory space access.
~ T1
•
CK
A21-AO
X X
CSn
\ /
RD
\ /
(Read)
)
AD15-ADO
<
(Read)
Figure 8.11 Basic Timing of External Memory Space Access (I-state read timing)
128 HITACHI
CK
A21-AO
Read {
AD15-ADO
{
WRH.WRL Write
AD15-ADO
T1 ~ .... T2
~ ______ ~ __ ~ ____ ~x~ __ __
\~-'---:--~/
. When RDDTY=O
• 1'\ •
When \ _______Y
~. _ _ ;--_ _ --'-_ _ _ _ i----'./
RDDTY=1
\~-_/
Figure 8.12 Basic Timing of External Memory Space Access (2-state read timing) High-level duties of 35% and 50% can be selected for the RD signal using the RD duty bit (RDDTY) ofthe BCR. When RDDTY is set to I. the high-level duty is 35% of the T1 state, enabling longer access times for external devices. Only set to 1 when the operating frequency is a minimum of 10 MHz.
8.4.2 Wait State Control
The number of external memory space access states and the insertion of wait states can be controlled using the WCRI-WCR3 bits. The bus cycles that can be controlled are the CPU read cycle and the DMAC dual mode read cycle. The bus cycle that can be controlled using the WCR2 is the DMAC single-mode read/write cycle.
Table 8.8 shows the number of states and number of wait states in the access cycles to external memory spaces.
HITACHI 129
Table 8.8 Number of States and Number of Wait States in the Access Cycles to External Memory Spaces
CPU read cycle, DMAC dual mode read cycle, CPU Write Cycle and _ _ _ D_M_A_C_s_in_g_l_e_m_o_d_e_r_e_a_dJ_w_r_it_e_c_y_cl_e _ _ _ DMAC Dual Mode Write
Corresponding Bits in Corresponding Bits in Cycle (Cannot be Area WCR1 and WCR2
=
0 WCR1 and WCR2=
1 controlled by WCR1 )*2 1,3-5,7 1 cycle fixed; WAIT signal 2 cycles fixed + wait state from WAIT signalignored
0,2,6 (long 1 cycle + long wait state, 1 cycle + long wait state*l + wait state from WAIT
wait available) WAIT signal ignored signal .
Notes: 1. The number of long wait states is set by WCR3.
2. When DRAME
=
1, short pitch/long pitch is selected with the WW1 bit of the WCR1.3. Pin wait cannot be used for the CS7 and WAIT pins of area 3 because they are multiplexed.
For the CPU read cycle, DMAC dual mode read cycle and DMAC single mode read/write cycle, the access cycle is completed in 1 state when the corresponding bits of WCR 1 and WCR2 for areas 1, 3-5, and 7 are cleared to 0 and the WAIT pin input signal is not sampled. When the bits are set to 1, the WAIT signal is sampled and the number of states is 2 plus the number of wait states in the WAIT signal. The WAIT signal is sampled at the rise of the system clock (CK) directly preceding the second state of the bus cycle and the wait states are inserted as long as the level is low. When a high level is detected, it shifts to the second state (final state). Figure 8.13 shows the wait state timing when accessing the external memory spaces of areas 1, 3, 4, 5, and 7.
130 HITACHI
..
T1.. lw
(wait state) .. .. T2..
CK
A21-AO
=>< X
CSn
\
~~!
RD
\ n I
A .. d{
AD15-ADO
==>
~~( )
{WAH.WAL \
~~I
Write
AD15-ADO
( )
e
WAIT
\ e I I \
Figure 8.13 Wait State Timing for External Memory Space Access (2 states plus wait states from WAIT signal)
Areas 0, 2 and 6 have long wait functions. When the corresponding bits in WCR I and WCR2 are cleared to 0, the access cycle is I state plus the number oflong wait states (set in WCR3,
selectable between 1 and 4) and the WAIT pin input signal is not sampled. When the bits are set to I, the WAIT signal is sampled and the number of states is I plus the number of long wait states plus the number of wait states in the WAIT signal. The WAIT signal is sampled at the rise of the system clock (CK) directly preceding the last long wait state and the wait states are inserted as long as the level is low. When a high level is detected, it shifts to the final long wait state. Figure 8.14 shows the wait state timing when accessing the external memory spaces of areas 0, 2, and 6.
HITACHI 131
CK
Wait states set in WCR3
Wait state Wait from WAIT states set signal input in WCR3
•• •• •
>C
A21-AO
==><~_-'-- _______ -'--___
~_"-_:"'-r
;
-
l--{
RD
\'----'---~____'____'
Read ADl5-ADO
~r---'---'----'---'---'---1
/
Write
>-{
WRH' WRL
AD15-ADO
---~(~_~
_______________,._-~-~
Figure 8.14 Wait State Timing for External Memory Space Access (1 state plus long wait state (when set to insert 3 states) plus wait states from WAIT signal) .
For CPU write cycles and DMAC dual mode write cycles to external memory space, the number of states and wait state insertion cannot be controlled by WCR1. In areas 1,3,4,5, and 7, the WAIT signal is sampled and the number of states is 2 plus the number of wait states in the WAIT signal (figure 8.13). In areas 0, 2 and 6, the number of states is 1 state plus the number of long wait states plus the number of wait states in the WAIT signal (figure 8.14). Never write
°
in bits 7-2and 0 ofWCRl; only write l. When area 1 is being used as external memory space, never write 0 to bit 1 (WWl); always write 1.
8.4.3 Byte Access Control
The upper byte and lower byte control signals when 16-bit bus width space is being accessed can be selected from (WRH, WRL, AO) or (WR, HBS, LBS). When the byte access select bit (BAS) of 132 HITACHI
the BCR is set to 1, the WRH, WRL, and AO pins output WR, LBS and HBS signals. Figure 8.15 illustrates the control signal output timing in the byte write cycle.
..
CK
AO
BAS=O WRH
WRL
HBS
~
BAS = 1
LBS
J
WR
Upper byte access T1
..
:..
T2\
Lower byte access T1
.. ...
T2\,---,1
..
\~-Figure 8.15 Byte Access Control Timing For External Memory Space Access (Write Cycle)