A Display Interface Module (DIM) is mounted to the bottom of the 98770A or 98780A display to interface the lOP bus from the processor with the display. The DIM is described in the following paragraphs.
Figure 2-20 is a block diagram of the DIM. DIM translates the general lOP interface from the computer mainframe into the specialized alphanumeric bus required by the display. DIM contains a full screen buffer of alphanumeric characters along with refresh sequencing hardware. DIM also buffers the 1/0 bus before sending it to the graphics sections of the display. DIM's primary function is to refresh the alphanumeric display. DIM contains sufficient memory to store all the alphanumeric data for one full frame. Only characters which are changed need to be written to DIM.
IOPBUS
Connectors Jl and J3 interface DIM to the display, and connectors J2 and J4 interface DIM to the computer mainframe_ The connectors are as follows:
Jl - 36-pin; alpha data to the display J2 - 50-pin; power to the DIM
J3 - 36-pin; graphics data to the display J4 - 50-pin; lOP bus to the DIM
Interface Buffers
The interface buffers between the lOP bus and the combined alpha/graphics minimize capacitive loading on the lOP signal lines. Data and control signals from the buffers split into an alpha path and a graphics path.
Graphics data and control information are transferred directly to the display. Alpha data is gated into the alpha data buffer.
Control signals are also exchanged between the interface buffers and the controller. The output-status-flag-enable (OSFE) signal enables Status and Flag to the lOP bus.
The lower 8 lines of the data bus provide an 8-bit-wide data path between the interface buffers and the controller. This path is used to transfer address, control, and data information.
Alpha Data Buffer
The alpha data buffer provides isolation between the interface buffers and the frame buffer when the display is being refreshed or the line buffer is being loaded.
With DIR, the controller determines the direction of data through the buffer. Data is normally written to the buffer from the lOP. However, the lOP bus can read data from frame buffer memory via the alpha data and interface buffers to test data integrity.
The G signal is a disable signal that isolates the output of the alpha data buffer from the frame buffer.
Frame Buffer
The frame buffer is composed of four static RAM chips that provide 2480 16-bit words. This allows storage of 31 rows of 80 alphanumeric characters, or one full display data frame. The frame buffer is normally written from the lOP, but can be read for diagnostic purposes. Data transfer can occur both in DMA or direct 110 modes.
The controller accesses frame buffer locations with 12 address lines. The location may be accessed to load updated information from the lOP or to transfer data to the line buffer.
The WE line is a write-enable that is high for a write to the frame buffer, and low when a buffer read is required.
OE is the output-enable and is high when the frame buffer is being written or when data is being transferred to the line buffer.
Line Buffer
The line buffer is an NMOS-II chip that provides a dual line buffer function. It consists of a word counter, two 80-character shift registers, self-test circuitry, and support logic. Although there are 16 data paths on the chip, the display requires that only 15 be used.
The line buffer transfers an 80-character row from shift register 1 to the display while loading shift register 2 with another 80-character row from the frame buffer. When the transfer is complete, the buffer toggles the registers and begins shifting the contents of shift register 2 to the display while reloading shift register 1 from the frame buffer. This process continues until an entire frame has been transferred to the display.
Timing signals from the display control the loading and shifting of the line buffer registers. NW (new word) signifies next character, NL (new line) signifies next row, and NP (new page) signifies next frame. NP controls the address counters in the controller to ensure that the frame buffer is correctly accessed.
LD is a clock from the controller that enables data into the appropriate shift register from the frame buffer during load times.
The test signal (TST) puts the line buffer into self-test mode when it goes true. Self-test mode can be entered in two ways: 1) by pressing switch Sl, a momentary pushbutton switch mounted on DIM and accessible at the bottom of the display, or 2) by software diagnostics. If the switch is used, the manual test signal (MTST) goes true. In either case, the TST line goes true. The line buffer has a counter that generates a self-test pattern to the display in response to TST. An error in the test pattern Clln be easily detected. The ERR line to the controller goes true when a line buffer error is detected.
Controller
The controller regulates the entire interface between the lOP bus and the display. The controller operates in two basic nl0des: display mode and lOP mode. In display mode, the controller transfers data from the frame buffer to the line buffer. Display mode occupies the controller approximately 12% of the time. For about 88% of the time the controller is in lOP mode, responding to the lOP, requesting frame buffer updates, and controlling the updates.