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HIGH FREQUENCY BASE RESISTANCE AND THE REPRESENTATION OF TWO AND
THREE-DIMENSIONAL AC AND DC EMITTER AND BASE CURRENT FLOW OF BIPOLAR
TRANSISTORS
F. Hébert, D. Roulston
To cite this version:
F. Hébert, D. Roulston. HIGH FREQUENCY BASE RESISTANCE AND THE REPRESENTATION OF TWO AND THREE-DIMENSIONAL AC AND DC EMITTER AND BASE CURRENT FLOW OF BIPOLAR TRANSISTORS. Journal de Physique Colloques, 1988, 49 (C4), pp.C4-379-C4-382.
�10.1051/jphyscol:1988479�. �jpa-00227977�
JOURNAL DE PHYSIQUE
Colloque C4, suppl6ment au n09, Tome 49, septembre 1988
HIGH FREQUENCY BASE RESISTANCE AND THE REPRESENTATION OF TWO AND THREE-DIMENSIONAL AC AND DC EMITTER AND BASE CURRENT FLOW OF BIPOLAR TRANSISTORS
F.
HEBERT*
and D.J. ROULSTONElectrical Engineering Department, University of Waterloo, Waterloo.
Ont
.
N2L-3G1, Canada"~vantek Inc., Advanced Bipolar Products, 39201 Cherry Street , Newark, CA 94560, U.S.A.
~ 6 s u m d
-
La rgsistance de base et 11imp6dance dlentre'e 3 haute frgquence de transistors bipolaires sont simule'es en utilisant une reprgsentation h trois dimensions (3D). On observe que la rsduction de la ryistance de base ainsi que les courants 3D de transistors non-mures ne peuvent stre correctement representees par des circuits Gquivalents standards. Une reprgsentation parallele d~ transistor est proposge pour mieux modeler les transistors non-mure's a hautefrgquence.
Abstract
-
The high frequency base resistance, input impedance and current flows of bipolar transistors are simulated using a quasi three- dimensional (3D) representation of the device. It is found that the reduction in base resistance as well as the 3D current flows of non-walled transistors cannot be properly simulated using standard distributed equivalent circuits. A parallel connected equivalent circuit is proposed for improved high frequency modeling of non-walled devices.1
-
INTRODUCTIONThe base resistance (Rbb) and input impedance of bipolar transistors will effectively reduce at high frequencies due to ac current crowding within the intrinsic and extrinsic regions, since the capacitances and resistances are distributed. In this paper, a three-dimensional (3D) technique
required for the simulation of the ac base resistance based on a 2D distributed network representation of the layout of transistors [I], with all the parasitic capacitances added, is described. The quasi 3D
simulation of the input impedance of a poly emitter transistor is 6arried out to demonstrate the effect of ac current crowding. It is also found that the standard distributed equivalent circuit does not properly represent the two dimensional current flow of non-walled transistors; a parallel equivalent circuit is proposed as an alternative.
2
-
QUASI THREE-DIMENSIONAL SIMULATIONSIn order to study the 3D ac behaviour of a transistor, the 2D distributed network representation of the transistor layout, as used in [I], is
modified to include the vertical capacitive current: the peripheral (side) and plane capacitances of the base and emitter diffusions are distributed, and the current sources under the emitter, which represent the vertical base current flow [I], are replaced by a resistance (R*.), shunted by a capacitance (C*) as per the hybrid-l equivalent circuit representation.
This is shown in Fig. 1. C w is the parallel combination of the diffusion (CD) and the emitter-base capacitances (plane, Ce
,
and sidewall, Ces).Ccs and Cc are the sidewall and plane collector-Ease junction capacitances respectiveyy
.
This representation permits simulation of the input impedance and of the intrinsic and extrinsic base resistances (Rb i and Rbbx, from power dissipation considerations, [I]) at various trequencles. The operating current is defined by the value of R,, and CD used in the analysis.
Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988479
JOURNAL DE PHYSIQUE
Fiuure 1
-
2D layout representation [I] modified to take into account the vertical ac current flow. The component values are indicated in the 4cross-sections shown.
It is assumed that. the collector is an ac ground and that dc current crowding is negligible. The sheet capacitances, specified in Farads per unit area, and the sidewall (edge) capacitances, specified in Farads per unit length, are represented by grounded capacitors at each node of the equivalent circuit., as shown in the various cross-sections of Figure 1.
The capacitive values required for the analysis may be obtained from measurements or from device simulators, such as BIPOLE [2], for the bias voltage of interest.
3
-
HIGH FREQUENCY SIMULATIONSThe ac input impedance has been simulated for a single base contact transistor with the characteristics listed in Table I. The transistor considered is an oxide isolated device with a non-walled poly emitter and an ft of 3 GHz. 'I'he resulting "input impedance circlew [3] is shown in Figure 2. A semi-circle if formed by curve-fitting of the low frequency data points (as expected [ 3 ] ) and the extrapolated high-frequency
intercept (1400 ohms) yields exactly the low-frequency base resistance.
JZ
E
REAL INPUT IMPEDANCE (ohms)
1400 2 m 3000 3800 4600 5
FREQUENCY IN GHz 0.5
!-
2
-1400z
> -1800
u
S - ,
3 I
Fiuure 2
-
Input impedance of a non-walled poly emitter bipolar transistor.Half of the layout view shown in Fig. 1 was simulated.
Table I
-
Poly emitter transistor characteristics ParameterEmitter area Base area Ext. sheet res.
Int. sheet res.
Current density Rlr
c ,
Ces Ccs C c ~
Value 2 x 2 4 x 7 548 3020 151 1.28x105 1.40x10-~*
7. 77x10-l6 2.7 5x10-l7 1. 75x10-l7
Units
'-lm;
P m
ohms/square ohms/square amps/pm2 ohms pm2 F/P~
6
F/rm F / P 2 F/pm
The divergence of the input impedance from the semi-circle at very high frequencies is a result of ac current crowding which effectively reduces the base resistance. Both Rbbi and Rbbx are observed to reduce, and the reduction in Rbbi is greater than that of Rbbx due to the larger
capacitance in the intrinsic region.
4
-
EOUIVALENT CIRCUITSThe variation of the input impedance of non-walled emitter transistors cannot be properly simulated using a standard distributed equivalent circuit (as shown in Figure 3) due to the multi-dimensional current flows.
To illustrate this, the surface potential over the emitter of walled (Fig. 4) and non-walled (Fig.5) devices have been computed using the quasi 3D technique described above. The base current flow in the walled device is clearly one-dimensional (from a layout view) and the equivalent circuit of Fig. 3 may be used to accurately model the variation of the input
impedance with bias or frequency. In the case of the non-walled structure, since the base current flows around the emitter, current crowding first occurs at the emitter edge which is farthest away from the base contact.
Also, the emitter-base voltage at the emitter periphery will vary with current which results in 2D variations of the emitter-base capacitance This does not occur when the device is walled since the base current is one-dimensional in the layout plane.
Fiqure 3
-
Standard distributed equivalent circuit showing the plane and sidewall capacitances. 5 intrinsic and 2 extrinsic sections are shown.C4-382 JOURNAL DE PHYSIQUE
Fiuure 4
-
Potential (z-axis) over Fisure 5-
Potential (z-axis) over the surface of a walled emitter one half the surface of a non-walled base contact bipolar transistor. emitter single base contact device.In order to better represent the distribution of the emitter-base voltage over the emitter surface and the 3D currents, the parallel distributed circuit of Fig. 6 is used. Each of the three transistors shown (device "A"
represents the quadrant near the base contact, device "CU represents the quadrant farthest away from the base contact and device "BI1 represents the remaining two quadrants) may be represented by the distributed equivalent circuit of Fig.
?.
RbA, Rb and RbC are the extrinsic resistances along the paths shown in Flg. 6a. ~ R e s e are computed using a 2D simulator [I] with the following requirements: RbA is the minimum value of Rbbx (when most of the current flows in quadrant "AM) and the sum of Rb,
RbB and RbC is equal to the total extrinsic base resistance computed at low currents and low frequencies [I].Fiaure 6
-
Parallel equivalent circuit of non-walled emitter transistor.a) layout view showing the base current paths. b) equivalent circuit.
The four emitter quadrants are assumed to carry equal currents. The area of the "BW transistor is twice that of the "Aw and "CW devices.
REFERENCES
[I] F. ~Qbert and D.J. Roulston, Solid-State Elec., 3 l , (1988), 283.
[2] D.J. Roulston, Proc. CICC, (1980), 2.
[3] W.M.C. Sansen, R.G. Meyer, IEEE J. Solid-State Cir.,
w ,
(1972), 492.\
