Hassan HARB1, Emmanuel BOUTILLON1 and Bertrand LE GAL2
1 LAB-STICC, UMR 6295, Université de Bretagne Sud, Lorient, France
2 IMS Laboratory, UMR 5218, Bordeaux INP, Université de Bordeaux, France
Real-time evaluation of NB-LDPC codes thanks to HLS-based hardware emulation
Implementation results
Conclusion and Perspectives NB-LDPC codes
Hardware emulation system Introduction
DASIP’18 : the Conference on Design and Architectures for Signal and Image Processing, Porto, Portugal, October 2018.
Applicability of the approach
Encoder Modulator Channel sc_quantizer In wrapper NB-LDPC
decoder Out wrapper Box-Muller
Random
Statistics
{BER & FER}
{failures}
{throughput}
{sigma}
Fig. 1. R´epr´esentatin sch´ematique de la chaine de communication implant´ee pour test´e le d´ecodeur LDPC-NB
the design time of test platforms and also increases their reusability.
In order to adapt the test platform to another type of LDPC- NB code, it is necessary to modify the wrappers around the decoder in order to adapt to the I/O protocol of the latter. It is also necessary to update the encoder at the input of the chain so that the information produced is in adequacy with the LDPC- NB code. This information can be set using configuration files.
III. HARDWARE EMULATION AND COMPLEXITY
The complete test platform described above associated with the LDPC-NB decoder described manually in VHDL language [?] were synthesized, placed and routed on a DIGILENT Genesys 2 FPGA platform (Kintex-7 XC7K325T-2FFG900C).
For simplicity reasons the targeted operating frequency during HLS synthesis and logical synthesis is 100 MHz. In order to achieve low error rates, 8 parallel sample generation chains were deployed to saturate the decoder with a maximum bit rate of 1600 Mbps. In practice, the speed reached by the communication chain and the decoder reaches a maximum of 500 Mbps. This is explained by the loss of flow coming from wrappers that have not yet been optimized.
Thanks to these high simulation performances, it was pos- sible to validate the hardware behavior of the decoder in real situation, but also to draw the performance curves down to an FER of 10 10 as presented in Figure 2. Thus it is possible to observe the emergence of an error floor related to the code- structure. This phenomenon was impossible to observe without a hardware prototype because of the prohibitive simulation times to obtain these last points.
For the design of this prototype platform, the HLS played a key role in validating overall system performance. Thus it was used to design all the non-critical blocks, thus accelerating the development of the test environment.
From a factual point of view, the system currently operating on board uses 43% of the FPGA’s available resources with about 30.3% for the LDPC-NB decoder and 12.7% for the simulation environment. To improve the simulation speed it is possible to duplicate the simulation chain in the FPGA device. An improvement of a factor 2 is then obtained for the Kintex-7 FPGA device and enables throughputs of 1 Gbps.
The approach is also applicable to bigger FPGA device such as Ultra-scale+ FPGA where multi-Gbps throughputs should be easily obtained.
IV. CONCLUSION
In conclusion, this demonstrator first demonstrates that LDPC-NB code design with good theoretical and practical characteristics is possible. Indeed, the hardware architec- ture of decoding is high speed and its performances up to F ER 10 9 do not show any error-floor. In addition, this demonstrator, which is the second stage of a larger project [?], demonstrates that the generation of flexible, high-speed 500 Mbps test environments is possible using high-level tools and methodology. This greatly simplifies the validation and characterization of digital communication systems. In the future the automatic generation of high efficiency NB-LDPC decoders using HLS methodology will be investigated.
ACKNOWLEDGMENT
The authors would like to thank the GdR 720 ISIS and the french CNRS institution for the fundings that where used for this study.
REFERENCES
[1] H. Kopka and P. W. Daly, A Guide to LATEX, 3rd ed. Harlow, England:
Addison-Wesley, 1999.
[2] R. G. Gallager. Low-density parity-check codes. PhD thesis, MIT, Cam- bridge, Mass., September 1960.
[3] D. J. C. MacKay and R. M. Neal. Near shannon limit performance of low density parity check codes. Electron. Lett., 32(18) :1645-1646, August 1996.
[4] M.C. Davey and D. MacKay. Low-density parity check codes over gf(q).
Communications Letters, IEEE, 2(6) :165-167, 1998.
[5] A. Voicila, D. Declercq, F. Verdier, M. Fossorier, and P. Urard. Low- complexity, low-memory EMS algorithm for non-binary LDPC codes. In Communications, 2007. ICC 07. IEEE International Conference on, pages 671-676, 2007.
0.5 1.5 2.5 3.5 4.5 5.5 6.5 10 6
10 4 10 2 100
snr (Eb/N0)
ber
0.5 1.5 2.5 3.5 4.5 5.5 6.5 10 6
10 4 10 2 100
snr (Eb/N0)
fer
Fig. 2. BER and FER performance measured on board for the NB-LDPC decoder depending on the number of decoding iterations.
Encoder Modulator Channel sc_quantizer In wrapper NB-LDPC
decoder Out wrapper Box-Muller
Random
Statistics
{BER & FER}
{failures}
{throughput}
{sigma}
Fig. 1. Digital communication toolchain implemented using Vivado HLS in order to test the NB-LDPC decoder described in VHDL.
the decoder in order to adapt the I/O protocol of the latter.
It is necessary to update the encoder so that the information produced is consistent with the new NB-LDPC code. This information is set using configuration files.
III. HARDWARE EMULATION AND COMPLEXITY
The complete test platform described above associated with the NB-LDPC decoder described manually in VHDL language was synthesised, placed and routed on a DIGILENT Genesys 2 FPGA platform (Kintex-7 XC7K325T-2FFG900C). For sake of design simplicity, the frequency is adjusted to 100 Mhz in both HLS and logical synthesis. In order to achieve low error rates, 8 parallel sample generation chains were employed to saturate the decoder with a maximum bit rate of 1600 Mbps.
In practice, the speed reached a maximum of 500 Mbps by the communication chain and the decoder. This is explained by the loss of flow coming from wrappers that have not yet been optimized.
Thanks to these high simulation performances, it was pos- sible to validate the hardware behavior of the decoder in real situation, but also to draw the performance curves down to an FER of 10 8 as presented in Figure 2. Thus it is possible to observe the emergence of an error floor related to the code- structure. This phenomenon was impossible to observe without a hardware prototype because of the prohibitive simulation times to obtain these last points.
For the design of this prototype platform, the HLS played a key role in validating overall system performance. Thus it was
0.51.52.53.54.55.56.57.5 10 9
10 6 10 3
Eb/N0 (db)
BER
0.51.52.53.54.55.56.57.5 10 7
10 5 10 3 10 1
Eb/N0 (db)
FER
Fig. 2. BER and FER performance measured on board for the NB-LDPC decoder depending on the number of decoding iterations.
used to design all the non-critical blocks, thus accelerating the development of the test environment.
From a factual point of view, the system currently operating on board uses 43% of the FPGA’s available resources with about 30.3% for the NB-LDPC decoder and 12.7% for the simulation environment. To improve the simulation speed it is possible to duplicate the simulation chain in the FPGA device. An improvement of a factor 2 would be then obtained in Kintex-7 FPGA device and enables throughputs of 1 Gbps.
The approach is applicable to bigger FPGA device (e.g. Ultra- scale+) where multi-Gbps throughputs should be obtained.
IV. CONCLUSION
In conclusion, this demonstrator first demonstrates that NB- LDPC code design with good theoretical and practical charac- teristics is possible. Indeed, the hardware architecture of de- coding is high speed and its performances up to F ER 10 7 do not show any error-floor. In addition, this demonstrator, which is the second stage of a larger project [8], demonstrates that the generation of flexible, high-speed 500 Mbps test envi- ronments is possible using high-level tools and methodology.
This greatly simplifies the validation and characterization of digital communication systems. In the future the automatic generation of high efficiency NB-LDPC decoders using HLS methodology will be investigated.
ACKNOWLEDGMENT
The authors thank the GdR 720 ISIS from the french CNRS institution and the French ANR institution (ANR-15-CE25- 0006-01) for the fundings used for this study.
REFERENCES
[1] R. G. Gallager. Low-density parity-check codes. PhD thesis, MIT, Cam- bridge, Mass., September 1960.
[2] D. J. C. MacKay and R. M. Neal. Near shannon limit performance of low density parity check codes. Electron. Lett., 32(18) :1645-1646, 1996.
[3] M.C. Davey and D. MacKay. Low-density parity check codes over gf(q).
Communications Letters, IEEE, 2(6) :165-167, 1998.
[4] A. Voicila, D. Declercq, F. Verdier, M. Fossorier, and P. Urard. Low- complexity, low-memory EMS algorithm for non-binary LDPC codes. In Communications, 2007. In Proceedings of ICC, pp. 671-676, 2007.
[5] E. Boutillon, L. Conde-Canencia and A. Ghouwayel. Design of a GF(64)- LDPC Decoder Based on the EMS Algorithm. IEEE TCAS-I, 60 (10), pp. 2644-2656, 2013.
[6] B. Le Gal and C. Jego, Low-latency software LDPC decoders for x86 multi-core devices. IEEE SiPS Workshop, October 2017.
[7] Z. Liu, R. Liu, Y. Hou and L. Zhao, High-Throughput Multi-Codeword Decoder for Non-Binary LDPC Codes on GPU. IEEE Communications Letters, vol. 22 (3), pp. 486-489, 2018.
[8] E. Boutillon, C. Marchand, H. Harb, T. Gendron, A. Derrien, L. Conde- Canencia and B. Le Gal, Construction of good Non-Binary Low Density Parity Check codes. IEEE SiPS Workshop, October 2017.
System inside the FPGA device
