February2018 MatthieuMoy Transaction-LevelModelsofSystems-on-a-ChipCantheybeFast,CorrectandFaithful?
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(2) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. About me. 2005. • Ph.D: formal verification of SoC models (ST/Verimag). 2006. • Post-doc: security of storage (Bangalore, Inde). 2006 2014. • Assistant professor, Verimag / Ensimag Work on SoC models & abstract interpretation • HDR: High-Level models for Embedded Systems. 2017. • New CASH team leader, LIP / UCBL. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 2 / 70 >.
(3) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. Compilation of SystemC/TLM. 3. Verification of SystemC/TLM. 4. Extra-Functional Properties in TLM. 5. Conclusion. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 3 / 70 >.
(4) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. Compilation of SystemC/TLM. 3. Verification of SystemC/TLM. 4. Extra-Functional Properties in TLM. 5. Conclusion. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 3 / 70 >.
(5) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Modern Systems-on-a-Chip. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 4 / 70 >.
(6) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Modern Systems-on-a-Chip Software. Hardware. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 4 / 70 >.
(7) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Hardware/Software Design Flow Traditional Design-Flow Specification, Algorithm RTL Design. Time. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 5 / 70 >.
(8) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Hardware/Software Design Flow Traditional Design-Flow Specification, Algorithm RTL Design. Synthesis. Time. cost > 1,000,000 $ ! Factory Software Development Integration. Validation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 5 / 70 >.
(9) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Time. Hardware/Software Design Flow Traditional Design-Flow. Transaction-Level Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. Synthesis. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 5 / 70 >.
(10) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Hardware/Software Design Flow Traditional Design-Flow. Transaction-Level Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design Software Development. Time. Synthesis. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 5 / 70 >.
(11) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Hardware/Software Design Flow Traditional Design-Flow. Transaction-Level Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. TLM Model. Software Development. Time. Synthesis. Synthesis. Factory Software Development Integration. Validation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 5 / 70 >.
(12) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Hardware/Software Design Flow Traditional Design-Flow. Transaction-Level Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. TLM Model. Software Development Synthesis. Synthesis. Factory. Factory. Time. Integration. Software Development. Validation. Integration. Validation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 5 / 70 >.
(13) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Hardware/Software Design Flow Traditional Design-Flow. Transaction-Level Model based. Specification, Algorithm. Specification, Algorithm. RTL Design. RTL Design. TLM Model. Software Development Synthesis. Synthesis. Factory. Factory. Time. Integration. Software Development. Validation. gain. Integration. Validation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 5 / 70 >.
(14) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. The Transaction Level Model: Principles and Objectives A high level of abstraction, that appears early in the design-flow. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 6 / 70 >.
(15) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. The Transaction Level Model: Principles and Objectives A high level of abstraction, that appears early in the design-flow A virtual prototype of the system, to enable I I I I. Early software development Integration of components Architecture exploration Reference model for validation. Abstract implementation details from RTL I I. Fast simulation (' 1000x faster than RTL) Lightweight modeling effort (' 10x less than RTL). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 6 / 70 >.
(16) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Content of a TLM Model A first definition. Model what is needed for Software Execution: I I I. Processors Address-map Concurrency. ... and only that. I I I I I. No micro-architecture No bus protocol No pipeline No physical clock .... Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 7 / 70 >.
(17) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. An example TLM Model. CPU process = C++ code. ITC. Timer. VGA. TLM Bus. Data RAM. Matthieu Moy (LIP). Instruction RAM. Transaction-Level Models of SoCs. GPIO. February 2018. < 8 / 70 >.
(18) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Performance of TLM. Pure RTL. 1 hour. RTL + cosimulation. TLM. x20. 3 minutes. x60. 3 seconds x3. HW emulation. 1 second. Simulation time (second) logarithmic scale 1. Matthieu Moy (LIP). 10. 100. Transaction-Level Models of SoCs. 10000. February 2018. < 9 / 70 >.
(19) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Uses of Functional Models Reference for Hardware Validation. SPEC. Virtual Prototype for Software Development. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 10 / 70 >.
(20) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Uses of Functional Models Reference for Hardware Validation. SPEC. ?. =. RTL. Virtual Prototype for Software Development. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 10 / 70 >.
(21) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Uses of Functional Models Reference for Hardware Validation. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. Virtual Prototype for Software Development. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 10 / 70 >.
(22) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Uses of Functional Models Reference for Hardware Validation. Virtual Prototype for Software Development. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Matthieu Moy (LIP). Instruction RAM. GPIO. Transaction-Level Models of SoCs. February 2018. < 10 / 70 >.
(23) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Uses of Functional Models Reference for Hardware Validation. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. Unmodified Software Virtual Prototype for Software Development. CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Matthieu Moy (LIP). Instruction RAM. GPIO. Transaction-Level Models of SoCs. February 2018. < 10 / 70 >.
(24) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Uses of Functional Models Reference for Hardware Validation. CPU process = C++ code. SPEC ITC. VGA. Timer. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. ?. =. RTL. Unmodified Software Virtual Prototype for Software Development. CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Matthieu Moy (LIP). Instruction RAM. GPIO. ?. ⊇. Transaction-Level Models of SoCs. February 2018. < 10 / 70 >.
(25) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Content of a TLM Model A richer definition. Timing information I I. May be needed for Software Execution Useful for Profiling Software 60 50 40 30. Power and Temperature I I. 20 10 0 10. Validate design choices Validate power-management policy. Matthieu Moy (LIP). Transaction-Level Models of SoCs. 20 30. February 2018. < 11 / 70 >.
(26) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Use of Extra-Functional Models Timing, Power consumption, Temperature Estimation. CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Matthieu Moy (LIP). Instruction RAM. GPIO. Transaction-Level Models of SoCs. February 2018. < 12 / 70 >.
(27) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Use of Extra-Functional Models Timing, Power consumption, Temperature Estimation. CPU ITC. process = C++ code. Timer. VGA. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. 60. 60. 50. 50. 40. 40. 30 20 10 0 10 20 30. ?. 20 10. ≈. Estimated Matthieu Moy (LIP). 30. 0 10 20 30. Actual Transaction-Level Models of SoCs. February 2018. < 12 / 70 >.
(28) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Use of Extra-Functional Models Timing, Power consumption, Temperature Estimation. Unmodified Power/Temperature-Aware Software. CPU ITC. process = C++ code. Timer. VGA. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. 60. 60. 50. 50. 40. 40. 30 20 10 0 10 20 30. ?. 20 10. ≈. Estimated Matthieu Moy (LIP). 30. 0 10 20 30. Actual Transaction-Level Models of SoCs. February 2018. < 12 / 70 >.
(29) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Summary: Expected Properties of TLM Programs. SystemC/TLM Programs should Simulate fast, Satisfy correctness criterions, Reflect faithfully functional and extra-functional properties of the actual system.. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 13 / 70 >.
(30) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. Compilation of SystemC/TLM. 3. Verification of SystemC/TLM. 4. Extra-Functional Properties in TLM. 5. Conclusion. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 13 / 70 >.
(31) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SystemC: Simple Example N1 SC_MODULE(not_gate) { sc_in<bool> in; sc_out<bool> out; void compute (void) { // Behavior bool val = in.read(); out.write(!val); } SC_CTOR(not_gate) { SC_METHOD(compute); sensitive << in; }. N2 int sc_main(int argc, char **argv) { // Elaboration phase (Architecture) // Instantiate modules ... not_gate n1("N1"); not_gate n2("N2"); sc_signal<bool> s1, s2; // ... and bind them together n1.out.bind(s1); n2.out.bind(s2); n1.in.bind(s2); n2.in.bind(s1); // Start simulation sc_start(100, SC_NS); return 0;. }; } Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 14 / 70 >.
(32) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Compiling SystemC. $ g++ example.cpp -lsystemc $ ./a.out ... end of section?. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 15 / 70 >.
(33) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Compiling SystemC. $ g++ example.cpp -lsystemc $ ./a.out. But ... C++ compilers cannot do SystemC-aware optimizations C++ analyzers do not know SystemC semantics. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 15 / 70 >.
(34) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. This section. 2. Compilation of SystemC/TLM Front-end Optimization and Fast Simulation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 15 / 70 >.
(35) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SystemC Front-End In this talk: Front-end = “Compiler front-end” (AKA “Parser”). SystemC. Front end. Intermediate Representation. Back end. Intermediate Representation = Architecture + Behavior. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 16 / 70 >.
(36) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SystemC Front-Ends When you don’t need a front-end: I I. Main application of SystemC: Simulation Testing, run-time verification, monitoring. . .. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 17 / 70 >.
(37) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SystemC Front-Ends When you don’t need a front-end: I I. Main application of SystemC: Simulation Testing, run-time verification, monitoring. . .. ⇒ No reference front-end available on http://www.accellera.org/. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 17 / 70 >.
(38) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SystemC Front-Ends When you don’t need a front-end: I I. Main application of SystemC: Simulation Testing, run-time verification, monitoring. . .. ⇒ No reference front-end available on http://www.accellera.org/ When you do need a front-end: I I I I I. Symbolic formal verification, High-level synthesis Visualization Introspection SystemC-specific Compiler Optimizations Advanced debugging features. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 17 / 70 >.
(39) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Challenges and Solutions with SystemC Front-Ends 1. C++ is complex (e.g. clang ≈ 200,000 LOC). 2. Architecture built at runtime, with C++ code. SC_MODULE(not_gate) { sc_in<bool> in; sc_out<bool> out; void compute (void) { // Behavior bool val = in.read(); out.write(!val); } SC_CTOR(not_gate) { SC_METHOD(compute); sensitive << in; } };. int sc_main(int argc, char **argv) { // Elaboration phase (Architecture) not_gate n1("N1"); not_gate n2("N2"); sc_signal<bool> s1, s2; // Binding n1.out.bind(s1); n2.out.bind(s2); n1.in.bind(s2); n2.in.bind(s1); // Start simulation sc_start(100, SC_NS); return 0; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 18 / 70 >.
(40) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Challenges and Solutions with SystemC Front-Ends 1. 2. C++ is complex (e.g. clang ≈ 200,000 LOC) ; Write a C++ front-end or reuse one (g++, clang, EDG, . . . ) Architecture built at runtime, with C++ code ; Analyze elaboration phase or execute it. SC_MODULE(not_gate) { sc_in<bool> in; sc_out<bool> out; void compute (void) { // Behavior bool val = in.read(); out.write(!val); } SC_CTOR(not_gate) { SC_METHOD(compute); sensitive << in; } };. int sc_main(int argc, char **argv) { // Elaboration phase (Architecture) not_gate n1("N1"); not_gate n2("N2"); sc_signal<bool> s1, s2; // Binding n1.out.bind(s1); n2.out.bind(s2); n1.in.bind(s2); n2.in.bind(s1); // Start simulation sc_start(100, SC_NS); return 0; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 18 / 70 >.
(41) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Challenges and Solutions with SystemC Front-Ends 1. 2. C++ is complex (e.g. clang ≈ 200,000 LOC) ; Write a C++ front-end or reuse one (g++, clang, EDG, . . . ) Architecture built at runtime, with C++ code ; Analyze elaboration phase or execute it. SC_MODULE(not_gate) { sc_in<bool> in; sc_out<bool> out; void compute (void) { // Behavior bool val = in.read(); Static Approaches out.write(!val); } SC_CTOR(not_gate) { SC_METHOD(compute); sensitive << in; } };. int sc_main(int argc, char **argv) { // Elaboration phase (Architecture) not_gate n1("N1"); Dynamic Approaches not_gate n2("N2"); sc_signal<bool> s1, s2; // Binding n1.out.bind(s1); n2.out.bind(s2); n1.in.bind(s2); n2.in.bind(s1); // Start simulation sc_start(100, SC_NS); return 0; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 18 / 70 >.
(42) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with the architecture When it becomes tricky. . .. int sc_main(int argc, char **argv) { int n = atoi(argv[1]); int m = atoi(argv[2]); Node array[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { array[i][j] = new Node(...); ... } } sc_start(100, SC_NS); return 0; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 19 / 70 >.
(43) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with the architecture When it becomes tricky. . .. Static approach: cannot deal with such code Dynamic approach: can extract the architecture for individual instances of the system. int sc_main(int argc, char **argv) { int n = atoi(argv[1]); int m = atoi(argv[2]); Node array[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { array[i][j] = new Node(...); ... } } sc_start(100, SC_NS); return 0; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 19 / 70 >.
(44) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with the architecture When it becomes very tricky. . .. void compute(void) { for (int i = 0; i < n; i++) { ports[i].write(true); } ... }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 20 / 70 >.
(45) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with the architecture When it becomes very tricky. . .. One can unroll the loop to let i become constant, Undecidable in the general case.. Matthieu Moy (LIP). void compute(void) { for (int i = 0; i < n; i++) { ports[i].write(true); } ... }. Transaction-Level Models of SoCs. February 2018. < 20 / 70 >.
(46) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. The beginning: Pinapa AKA “my Ph.D’s front-end”. Pinapa’s principle: I I. Use GCC’s C++ front-end Compile, dynamically load and execute the elaboration (sc_main). Pinapa’s drawbacks: I I I I. Uses GCC’s internals (hard to port to newer versions) Hard to install and use, no separate compilation Ad-hoc match of SystemC constructs in AST AST Vs SSA form in modern compilers. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 21 / 70 >.
(47) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. LLVM: Low Level Virtual Machine JIT compilation. C++ Front ends. C. Bitcode. ... Optimizer. Back ends Code Generation. Clean API Clean SSA intermediate representation Many tools available Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 22 / 70 >.
(48) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. LLVM: Low Level Virtual Machine JIT compilation. C++ Front ends. C. Bitcode. ... Optimizer. Back ends Code Generation. Can we be here?. Clean API Clean SSA intermediate representation Many tools available Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 22 / 70 >.
(49) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. PinaVM: Enriching the bitcode SystemC. Compilation (llvm-g++, llvm-link). LLVM bitcode. Execute elaboration. Identify SC constructs. Architecture. bitcode++. Intermediate Representation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 23 / 70 >.
(50) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. PinaVM: Enriching the bitcode ... port.write(data); .... SystemC. Compilation (llvm-g++, llvm-link). SystemC construct is still a normal function. LLVM bitcode. Execute elaboration. %this is fixed. ... %port = expr1(%this) %data = expr2 call write %port, %data .... %this not known Cannot compute %port. Identify SC constructs. Architecture. Execute dependencies. Intermediate Representation. bitcode++. ... %port = expr1(%this) %data = expr2 SCWrite - data = ?? - port = ?? .... ... %port = expr1(%this) %data = expr2 SCWrite Process 0 → data d0 - data = Process 1 → data d1 - port =. Matthieu Moy (LIP). .... Transaction-Level Models of SoCs. Process 0 → port p0 Process 1 → port p1. . February 2018. < 23 / 70 >.
(51) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Summary. PinaVM relies on executability (JIT Compiler) for execution of: I I. elaboration phase (≈ like Pinapa) sliced pieces of code. Open Source: http://forge.imag.fr/projects/pinavm/ Still a prototype, but very few fundamental limitations ≈ 3000 lines of C++ code on top of LLVM Experimental back-ends for I I. Execution (Tweto) Model-checking (using SPIN). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 24 / 70 >.
(52) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. This section. 2. Compilation of SystemC/TLM Front-end Optimization and Fast Simulation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 24 / 70 >.
(53) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Typical Transaction Journey 0x6000 0x5000. CPU. 0x3000 0x2000 0x1000 0x0000. RAM. T2 T1. Bus. T1. T2 RAM. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 25 / 70 >.
(54) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Typical Transaction Journey 0x6000 0x5000. CPU. RAM. .... port.write(addr,data); .... 0x3000 0x2000 0x1000 0x0000. T2 T1. Bus. T1. T2 RAM status write(addr,data) { mem[addr] = data; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 25 / 70 >.
(55) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Typical Transaction Journey 0x6000 0x5000. CPU. RAM. .... port.write(addr,data); .... 0x3000 0x2000 0x1000 Forward method 0x0000 call to target socket. Call virtual method on socket. T2 Address Decoding T1. Bus. T1. Another virtual T2 method call. Forwarded to target socket. RAM status write(addr,data) { mem[addr] = data; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 25 / 70 >.
(56) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Typical Transaction Journey 0x6000 0x5000. CPU. RAM. .... port.write(addr,data); .... 0x3000 0x2000 0x1000 Forward method 0x0000 call to target socket. Call virtual method on socket. Bus. T1 Ends-up calling target module’s method. T2 Address Decoding T1. Another virtual T2 method call. Forwarded to target socket. RAM status write(addr,data) { mem[addr] = data; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 25 / 70 >.
(57) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Typical Transaction Journey 0x6000 0x5000. CPU. RAM. .... port.write(addr,data); .... 0x3000 0x2000 0x1000 Forward method 0x0000 call to target socket. Call virtual method on socket. Ends-up calling target module’s method. T2 Address Decoding T1. Bus Another virtual T1 T2 method call. Forwarded to target socket. RAM status write(addr,data) { mem[addr] = data; }. Many costly operations for a simple functionality Work-around: backdoor access (DMI = Direct Memory Interface) I I. CPU get a pointer to RAM’s internal data Manual, dangerous optimization. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 25 / 70 >.
(58) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Typical Transaction Journey 0x6000 0x5000. CPU. RAM. .... port.write(addr,data); .... 0x3000 0x2000 0x1000 Forward method 0x0000 call to target socket. Call virtual method on socket. Ends-up calling target module’s method. T2 Address Decoding T1. Bus Another virtual T1 T2 method call. Forwarded to target socket. RAM status write(addr,data) { mem[addr] = data; }. Many costly operations for a simple functionality Work-around: backdoor access (DMI = Direct Memory Interface) I I. CPU get a pointer to RAM’s internal data Manual, dangerous optimization. Can a compiler be as good as DMI, automatically and safely? Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 25 / 70 >.
(59) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Basic Ideas. Do statically what can be done statically ... ... considering “statically” = “after elaboration” Examples: I I I. Virtual function resolution Inlining through SystemC ports Static address resolution. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 26 / 70 >.
(60) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with addresses Statically 0x6000 0x5000. CPU. RAM. .... port.write(0x5500,data); .... 0x3000 0x2000 0x1000 0x0000. T2 T1. Bus. RAM status write(addr,data) { mem[addr] = data; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 27 / 70 >.
(61) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with addresses Statically 0x6000 0x5000. CPU. RAM. .... port.write(0x5500,data); .... Get actual port addr from PinaVM. 0x3000 0x2000 0x1000 0x0000. T2 T1. Bus. RAM status write(addr,data) { mem[addr] = data; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 27 / 70 >.
(62) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with addresses Statically 0x6000 0x5000. CPU. RAM. .... port.write(0x5500,data); ... Follow path to bus Get actual port addr from PinaVM. 0x3000 0x2000 0x1000 0x0000. T2 T1. Bus. RAM status write(addr,data) { mem[addr] = data; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 27 / 70 >.
(63) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with addresses Statically 0x6000 0x5000. CPU. RAM. .... port.write(0x5500,data); ... Follow path to bus Get actual port addr from PinaVM. 0x3000 T2 0x2000 0x1000 Address T1 0x0000 Decoding. Bus. RAM status write(addr,data) { mem[addr] = data; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 27 / 70 >.
(64) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with addresses Statically 0x6000 0x5000. CPU. RAM. .... port.write(0x5500,data); ... Follow path to bus Get actual port addr from PinaVM. 0x3000 T2 0x2000 0x1000 Address T1 0x0000 Decoding. Bus. Find target socket at this address. RAM status write(addr,data) { mem[addr] = data; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 27 / 70 >.
(65) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with addresses Statically 0x6000 0x5000. CPU. RAM. .... port.write(0x5500,data); ... Follow path to bus Get actual port addr from PinaVM. Find function in target module. 0x3000 T2 0x2000 0x1000 Address T1 0x0000 Decoding. Bus. Find target socket at this address. RAM status write(addr,data) { mem[addr] = data; }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 27 / 70 >.
(66) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Dealing with addresses Statically 0x6000 0x5000. CPU. RAM. .... port.write(0x5500,data); ... Follow path to bus Get actual port addr from PinaVM. 0x3000 T2 0x2000 0x1000 Address T1 0x0000 Decoding. Bus. Find function in target module. Find target socket at this address. RAM status write(addr,data) { mem[addr] = data; }. Possible optimizations: I I. Replace call to port.write() with RAM.write() Possibly inline it. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 27 / 70 >.
(67) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. Compilation of SystemC/TLM. 3. Verification of SystemC/TLM. 4. Extra-Functional Properties in TLM. 5. Conclusion. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 27 / 70 >.
(68) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Encoding Approaches SystemC. Encoding Formal language Existing verifier Yes/No/Maybe. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 28 / 70 >.
(69) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Encoding Approaches. T1 × T2 × T3 × Sch Synchronous automata + scheduler. T1 × T2 × T3 Asynchronous product shared variable. Matthieu Moy (LIP). T1 × T2 × T3 Asynchronous automata Dedicated product SystemC Concurrent program T1 × T2 × T3 × Sch Asynchronous automata. Transaction-Level Models of SoCs. February 2018. < 29 / 70 >.
(70) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Encoding Approaches. T1 × T2 × T3 × Sch Synchronous automata + scheduler. T1 × T2 × T3 Asynchronous product shared variable. Matthieu Moy (LIP). T1 × T2 × T3 Asynchronous automata Dedicated product SystemC Concurrent program T1 × T2 × T3 × Sch Asynchronous automata. Transaction-Level Models of SoCs. February 2018. < 29 / 70 >.
(71) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Translating a SystemC Program Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 30 / 70 >.
(72) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Translating a SystemC Program Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton. Scheduler. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 30 / 70 >.
(73) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Translating a SystemC Program Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton User code: Automatic translation. Scheduler. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 30 / 70 >.
(74) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Translating a SystemC Program Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton User code: Automatic translation. SystemC kernel: Direct semantics. Scheduler. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 30 / 70 >.
(75) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Translating a SystemC Program Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton User code: Automatic translation. SystemC kernel: Direct semantics. Scheduler. Communication: Direct semantics. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 30 / 70 >.
(76) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. The SystemC scheduler Non-preemptive scheduler Non-deterministic processes election Select process. Run. Init. Update Time elapse. (+ 1 automaton per process to reflect its state). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 31 / 70 >.
(77) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Encoding Approaches. T1 × T2 × T3 Asynchronous automata Dedicated product. T1 × T2 × T3 × Sch Synchronous automata + scheduler. T1 × T2 × T3 Asynchronous product shared variable. Matthieu Moy (LIP). SystemC Concurrent program T1 × T2 × T3 × Sch Asynchronous automata. Transaction-Level Models of SoCs. February 2018. < 32 / 70 >.
(78) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Encoding Approaches. T1 × T2 × T3 Asynchronous automata Dedicated product. T1 × T2 × T3 × Sch Synchronous automata + scheduler. T1 × T2 × T3 Asynchronous product shared variable. Matthieu Moy (LIP). SystemC Concurrent program T1 × T2 × T3 × Sch Asynchronous automata. Transaction-Level Models of SoCs. February 2018. < 32 / 70 >.
(79) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Encoding Approaches. T1 × T2 × T3 Asynchronous automata Dedicated product. T1 × T2 × T3 × Sch Synchronous automata + scheduler. T1 × T2 × T3 Asynchronous product shared variable. Matthieu Moy (LIP). SystemC Concurrent program T1 × T2 × T3 × Sch Asynchronous automata. Transaction-Level Models of SoCs. February 2018. < 32 / 70 >.
(80) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Encoding Approaches. T1 × T2 × T3 Asynchronous automata Dedicated product. T1 × T2 × T3 × Sch Synchronous automata + scheduler. T1 × T2 × T3 Asynchronous product shared variable. Matthieu Moy (LIP). SystemC Concurrent program T1 × T2 × T3 × Sch Asynchronous automata. Transaction-Level Models of SoCs. February 2018. < 32 / 70 >.
(81) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SystemC to Spin: encoding events. notify/wait for event E k :. p::wait(E k ): Wp := k blocked(Wp == 0). p::notify(E k ): ∀i ∈ P|Wi == K Wi := 0. Wp : integer associated to process p. Wp = k ⇔ “process p is waiting for event E k ”.. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 33 / 70 >.
(82) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SystemC to Spin: encoding time and events discrete time a deadline variable Tp is attached to each process p Tp = next execution time for process p p::wait(d): Tp := Tp + d blocked(Tp == min (Ti )) i∈P. Matthieu Moy (LIP). “Set my next execution time to now + d and wait until the current execution time reaches it”. Transaction-Level Models of SoCs. February 2018. < 34 / 70 >.
(83) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SystemC to Spin: encoding time and events discrete time a deadline variable Tp is attached to each process p Tp = next execution time for process p p::wait(d): Tp := Tp + d blocked(Tp == min (Ti )) i∈P Wi ==0. p::wait(E k ): Wp := K blocked(Wp == 0). Matthieu Moy (LIP). “Set my next execution time to now + d and wait until the current execution time reaches it”. p::notify(E k ): ∀i ∈ P|Wi == K Wi := 0 Ti := Tp. Transaction-Level Models of SoCs. February 2018. < 34 / 70 >.
(84) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SystemC to Spin: results 7e+06 PinaVM [SPIN 07] 6e+06. Nb of states. 5e+06. 4e+06. 3e+06. 2e+06. 1e+06. 0 2. PinaVM 4. Matthieu Moy (LIP). 6. 8. 10. 12. 14. Transaction-Level of SoCs Nb ofModels components. 16. 18 February 2018. 20. 22 < 35 / 70 >.
(85) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Encoding Approaches. T1 × T2 × T3 × Sch Synchronous automata + scheduler. T1 × T2 × T3 Asynchronous product shared variable. Matthieu Moy (LIP). T1 × T2 × T3 Asynchronous automata Dedicated product SystemC Concurrent program T1 × T2 × T3 × Sch Asynchronous automata. Transaction-Level Models of SoCs. February 2018. < 36 / 70 >.
(86) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. Compilation of SystemC/TLM. 3. Verification of SystemC/TLM. 4. Extra-Functional Properties in TLM. 5. Conclusion. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 36 / 70 >.
(87) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. This section. 4. Extra-Functional Properties in TLM Time and Parallelism Power and Temperature Estimation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 36 / 70 >.
(88) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Parallelization of Simulations. WIFI SPI. USB U A R T. PRCMU. Ethernet. C O R E. T I M E R. M M U. I T C. CAN. ADC ADC. DOCSIS. PWM. U A R T. DAC. C O R E. T I M E R. M M U. I2C. I T C. DAC UART. CORE. MMU. Audio. LIN Compo Capteur. TIMER. H.265. ITC. DISPLAY Capteur UART. GPU. CORE. TIMER. MMU. ITC. MEM CTLR. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 37 / 70 >.
(89) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Parallelization of Simulations System-level Simulation Vs HPC. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 38 / 70 >.
(90) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Problems and solutions for parallel execution of SystemC/TLM. (1) Execution order imposed by SystemC semantics (2) Concurrent access to shared resources (e.g., x++ on a global variable). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 39 / 70 >.
(91) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Problems and solutions for parallel execution of SystemC/TLM. (1) Execution order imposed by SystemC semantics (2) Concurrent access to shared resources (e.g., x++ on a global variable). ; No 100% automatic and efficient solution for TLM. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 39 / 70 >.
(92) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Problems and solutions for parallel execution of SystemC/TLM. (1) Execution order imposed by SystemC semantics (2) Concurrent access to shared resources (e.g., x++ on a global variable). ; No 100% automatic and efficient solution for TLM Our proposal = additional constructs: Desynchronization (1) / Synchronization (2). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 39 / 70 >.
(93) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Approaches to parallelization Efficient. Targets a wide subset of SystemC. Matthieu Moy (LIP). Few/no modifications required. Transaction-Level Models of SoCs. February 2018. < 40 / 70 >.
(94) SoCs and TLM. Compilation. Verification. SC - DURING :. Extra-functional. Conclusion. The Idea. SC_THREAD_1. OS thread_1. SC_THREAD_2. OS thread_2. .. . SC_THREAD_N. OS thread_N. SystemC. OS thread. Unmodified SystemC Some computation delegated to other threads Weak synchronization between SystemC and threads thanks to tasks with duration Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 41 / 70 >.
(95) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Wall-clock time. Simulated Time Vs Wall-Clock Time. Time elapse Computation. 0. 10. 20. 30. 40. Simulated time. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 42 / 70 >.
(96) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SystemC. A. sc-during. Simulated Time in SystemC and SC - DURING. P. B. Q. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 43 / 70 >.
(97) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Simulated Time in SystemC and SC - DURING. SystemC. A. sc-during. f() wait(20). P. B. Process A: // Computation f(); // Time taken by f wait(20);. Q. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 43 / 70 >.
(98) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. sc-during. SystemC. Simulated Time in SystemC and SC - DURING f() wait(20). Process A: // Computation f(); // Time taken by f wait(20);. g() wait(20). Process P: g(); wait(20);. A B. P Q. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 43 / 70 >.
(99) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. sc-during. SystemC. Simulated Time in SystemC and SC - DURING f() wait(20). Process A: // Computation f(); // Time taken by f wait(20);. g() wait(20). Process P: g(); wait(20); during(15, h);. A B. P Q. Matthieu Moy (LIP). h(). Transaction-Level Models of SoCs. February 2018. < 43 / 70 >.
(100) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. sc-during. SystemC. Simulated Time in SystemC and SC - DURING f() wait(20). Process A: // Computation f(); // Time taken by f wait(20);. g() wait(20). Process P: g(); wait(20); during(15, h);. A B. h(). P Q. i(). Matthieu Moy (LIP). j(). Transaction-Level Models of SoCs. February 2018. < 43 / 70 >.
(101) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Impact on Parallelism P1 P2 P3 P4. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 44 / 70 >.
(102) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Concurrency in an industrial platform Number of SystemC threads active within a cycle (ST set-top-box case study) :. mpeg2 → h264 h264 mpeg2 boot+init 0% 0 Proc.. Matthieu Moy (LIP). 50 % 1. 2. 3. Transaction-Level Models of SoCs. 100 % 4 and more. February 2018. < 45 / 70 >.
(103) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Impact on Parallelism P1 P2 P3 P4. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 46 / 70 >.
(104) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Impact on Parallelism P1 P2 P3 P4. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 46 / 70 >.
(105) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Impact on Parallelism P1 P2 P3 P4. Overlap between tasks ; parallel execution in sc-during. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 46 / 70 >.
(106) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Execution of during(T) Fast computation. Slow computation Task finishes. Task starts 0. 10. 20. 30. 40. Computation ends. Wall-clock time. Wall-clock time. Simulated time blocked. Task finishes. Rest of the platform drives time Task starts 0. Simulated time. 10. 20. 30. 40. Simulated time idle. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 47 / 70 >.
(107) SoCs and TLM. Compilation. SC - DURING :. Verification. Extra-functional. Conclusion. First (Naive) Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Thread creation 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } A B C. Thread Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 48 / 70 >.
(108) SoCs and TLM. Compilation. SC - DURING :. Verification. Extra-functional. Conclusion. First (Naive) Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Thread creation 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. Thread Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 48 / 70 >.
(109) SoCs and TLM. Compilation. SC - DURING :. Verification. Extra-functional. Conclusion. First (Naive) Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Thread creation 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. 1. création du thread Thread Matthieu Moy (LIP). f Transaction-Level Models of SoCs. February 2018. < 48 / 70 >.
(110) SoCs and TLM. Compilation. SC - DURING :. Verification. Extra-functional. Conclusion. First (Naive) Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Thread creation 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. 1. création du thread Thread Matthieu Moy (LIP). 2 wait(d). f Transaction-Level Models of SoCs. February 2018. < 48 / 70 >.
(111) SoCs and TLM. Compilation. SC - DURING :. Verification. Extra-functional. Conclusion. First (Naive) Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Thread creation 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. 1. création du thread Thread Matthieu Moy (LIP). 2 wait(d). f Transaction-Level Models of SoCs. February 2018. < 48 / 70 >.
(112) SoCs and TLM. Compilation. SC - DURING :. Verification. Extra-functional. Conclusion. First (Naive) Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Thread creation 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. création du thread Thread Matthieu Moy (LIP). 3. 1 2 wait(d). join() f Transaction-Level Models of SoCs. February 2018. < 48 / 70 >.
(113) SoCs and TLM. Compilation. SC - DURING :. Verification. Extra-functional. Conclusion. First (Naive) Implementation. void during(sc_core::sc_time d, std::function<void()> f) { std::thread t(f); // Thread creation 1 sc_core::wait(d); // SystemC executes 2 3 t.join(); // Wait for completion } during(d, f); A B C. création du thread Thread Matthieu Moy (LIP). 3. 1 2 wait(d). join() f Transaction-Level Models of SoCs. February 2018. < 48 / 70 >.
(114) SoCs and TLM. Compilation. SC - DURING :. Verification. Extra-functional. Conclusion. New Synchronization Primitives. extra_time(t): Increase duration of current task wait(5) initial extra time P duration. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 49 / 70 >.
(115) SoCs and TLM. Compilation. SC - DURING :. Verification. Extra-functional. Conclusion. New Synchronization Primitives. extra_time(t): Increase duration of current task wait(5) initial extra time P duration catch_up(): Wait for SystemC to reach the end of the task while (!c) { extra_time(10); catch_up(); // Ensures fairness }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 49 / 70 >.
(116) SoCs and TLM. Compilation. SC - DURING :. Verification. Extra-functional. Conclusion. New Synchronization Primitives. extra_time(t): Increase duration of current task wait(5) initial extra time P duration catch_up(): Wait for SystemC to reach the end of the task while (!c) { extra_time(10); catch_up(); // Ensures fairness } sc_call(f): Call function f in the context of SystemC x++; // Forbidden in // sc-during task sc_call([]{ x++; }); // OK Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 49 / 70 >.
(117) SoCs and TLM. Compilation. Verification. SC - DURING :. Extra-functional. Conclusion. Implementations. SC_THREAD_1. sync_task_1. OS thread_1. SC_THREAD_2. sync_task_2. OS thread_2. sync_task_N. OS thread_N. .. . SC_THREAD_N. OS Thread. SystemC Strategies: SEQ THREAD POOL ONDEMAND. Sequential (= reference) Thread creation + destruction for each task Pre-allocated set of threads Thread created on demand and reused. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 50 / 70 >.
(118) SoCs and TLM. Compilation. Verification. SC - DURING : 14. Extra-functional. Conclusion. Results. Loose timing (explicit synchronization). 12. 8 6. Speedup. 10. 4. Fine-grained synchronization. 2 0. Number of processors in the model 10. 20. 30. 40. 50. 60. Test machine : 4 × 12 = 48 cores Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 51 / 70 >.
(119) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Addressing the Faithfulness Issue: Exposing Bugs Example bug: mis-placed synchronization: imgReady = true; wait(5, SC_US); writeIMG(); wait(10, SC_US);. ||. while(!imgReady) wait(1, SC_US); wait(10, SC_US); readIMG();. ⇒ bug never seen in simulation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 52 / 70 >.
(120) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Addressing the Faithfulness Issue: Exposing Bugs Example bug: mis-placed synchronization: imgReady = true; wait(5, SC_US); writeIMG(); wait(10, SC_US);. ||. while(!imgReady) wait(1, SC_US); wait(10, SC_US); readIMG();. ⇒ bug never seen in simulation during(15, SC_US, []{ imgReady = true; writeIMG(); });. ||. while(!imgReady) wait(1, SC_US); wait(10, SC_US); readIMG();. ⇒ strictly more behaviors, including the buggy one. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 52 / 70 >.
(121) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Model Faithfulness model. actual. Unmodeled behaviors (B) Extra behaviors of the model (A). Matthieu Moy (LIP). Exactly modeled behaviors (C). Transaction-Level Models of SoCs. February 2018. < 53 / 70 >.
(122) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. SC - DURING. New way to express concurrency in the platform Allows parallel execution of loosely-timed systems Exposes more bugs ( faithfulness Vs correction) Next steps (skipped from this talk): I I I. Worker threads Vs platform partitioning: DistemC Exploit FIFO-based communication: FOFIFON Integration in the design-flow: HLS code wrapping. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 54 / 70 >.
(123) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. This section. 4. Extra-Functional Properties in TLM Time and Parallelism Power and Temperature Estimation. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 54 / 70 >.
(124) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Power and Temperature Estimation An example. “How to validate embedded software that regulates the chip’s temperature?” while (true) { // Temperature of one or more // locations of the chip read_sensors(); compute(); // Reduce frequency/voltage, // emergency stop, ... control_actuators(); } Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 55 / 70 >.
(125) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Power and Temperature Estimation What precision? What applications?. control_actuators(). read_sensors(). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 56 / 70 >.
(126) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Power and Temperature Estimation What precision? What applications?. control_actuators() CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. read_sensors(). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 56 / 70 >.
(127) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Power and Temperature Estimation What precision? What applications?. control_actuators() CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. read_sensors(). Arbitrary Temperature. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 56 / 70 >.
(128) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Power and Temperature Estimation What precision? What applications?. control_actuators() CPU ITC. process = C++ code. Timer. VGA. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. read_sensors(). Scenario. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 56 / 70 >.
(129) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Power and Temperature Estimation What precision? What applications?. control_actuators() CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. read_sensors(). Computation on a model. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 56 / 70 >.
(130) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Power and Temperature Estimation What precision? What applications?. control_actuators() CPU process = C++ code. ITC. Timer. VGA. TLM TLM Bus. Data RAM. Instruction RAM. GPIO. read_sensors(). Computation on a model. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 56 / 70 >.
(131) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Power Consumption, Temperature, Heat Dissipation Power (Joule effect). Dissipation. Component. (from another component). Dissipation (to another component). Dissipation (to environment). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 57 / 70 >.
(132) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Power Consumption, Temperature, Heat Dissipation Power (Joule effect). Dissipation. Component. (from another component). Dissipation (to another component). Dissipation (to environment) ; differential equations, solved by dedicated solvers Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 57 / 70 >.
(133) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Estimation with Power-State Models. // SystemC Process void compute() { while (true) { WIFI SPI. USB U A R T. PRCMU. Ethernet. C O R E. T I M E R. M M U. I T C. CAN. ADC ADC. DOCSIS. PWM. U A R T. DAC. C O R E. T I M E R. M M U. I2C. I T C. f(); wait(10);. DAC UART. CORE. MMU. Audio. LIN Compo Capteur. TIMER. H.265. ITC. DISPLAY Capteur UART. GPU. CORE. TIMER. MMU. ITC. MEM CTLR. wait(); } }. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 58 / 70 >.
(134) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Estimation with Power-State Models. 0.4 watt Run. WIFI SPI. USB U A R T. PRCMU. Ethernet. C O R E. T I M E R. M M U. I T C. CAN. ADC ADC. DOCSIS. PWM. U A R T. DAC. C O R E. T I M E R. M M U. I2C. I T C. DAC UART. CORE. MMU. Audio. LIN Compo Capteur. TIMER. H.265. ITC. DISPLAY Capteur UART. GPU. CORE. TIMER. MMU. ITC. MEM CTLR. Sleep. Idle. 0 watt. 0.1 watt. Matthieu Moy (LIP). // SystemC Process void compute() { while (true) { set_state("run"); f(); wait(10); set_state("idle"); wait(); } }. Transaction-Level Models of SoCs. February 2018. < 58 / 70 >.
(135) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. From States to Consumption State. sleep. run. idle. 0.4 watt. Consumption. 0 watt. run 0.4 watt. 0.1 watt. Total. 2.5 Joules. Energy (Consumption × Time) Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 59 / 70 >.
(136) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. From Power to Temperature State. sleep. run. idle. 0.4 watt. Consumption. 0 watt. run 0.4 watt. 0.1 watt 40o C. 20o C Temperature. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 60 / 70 >.
(137) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Traffic Models CPU ITC. process = C++ code. TLM Bus. Data RAM. Timer. VGA. Instruction RAM. Consumption = f (bits transmitted). GPIO. Consumption = f 0 (bits processed). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 61 / 70 >.
(138) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Traffic Model and Loosely Timed Models Real System. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 62 / 70 >.
(139) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Traffic Model and Loosely Timed Models Real System. f(); wait(40);. g(); wait(35);. Loosely-Timed Model. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 62 / 70 >.
(140) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Traffic Model and Loosely Timed Models Real System. f(); wait(40);. g(); wait(35);. Loosely-Timed Model +6. total=9. +3 Energy. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 62 / 70 >.
(141) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Traffic Model and Loosely Timed Models Real System. f(); wait(40);. g(); wait(35);. Loosely-Timed Model +6. total=9. +3 Energy. Temperature. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 62 / 70 >.
(142) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Traffic Model and Loosely Timed Models Real System. f(); wait(40);. g(); wait(35);. Loosely-Timed Model +6. total=9. +3 Energy Unrealistic peaks Temperature. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 62 / 70 >.
(143) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Traffic Model and Loosely Timed Models Real System. f(); wait(40);. g(); wait(35);. Loosely-Timed Model Frequency. Matthieu Moy (LIP). 3 40. trans/sec. Transaction-Level Models of SoCs. 6 35. trans/sec. February 2018. < 62 / 70 >.
(144) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Traffic Model and Loosely Timed Models Real System. f(); wait(40);. g(); wait(35);. Loosely-Timed Model Frequency. 3 40. trans/sec. 6 35. trans/sec. total=9. Energy. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 62 / 70 >.
(145) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Traffic Model and Loosely Timed Models Real System. f(); wait(40);. g(); wait(35);. Loosely-Timed Model Frequency. 3 40. trans/sec. 6 35. trans/sec. total=9. Energy. Temperature Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 62 / 70 >.
(146) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Cosimulation SystemC and Extra-Functional Solver. States Power/Temperature Solver. SystemC Temperature. Functionality can depend on extra-functional data (e.g.: temperature sensor). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 63 / 70 >.
(147) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Cosimulation of SystemC and Extra-Functional Solver. SystemC. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 64 / 70 >.
(148) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Cosimulation of SystemC and Extra-Functional Solver. SystemC. Simulation Instant (Zero-time). Simulation Interval. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 64 / 70 >.
(149) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Cosimulation of SystemC and Extra-Functional Solver. SystemC. Function. Fonction. Simulation Instant. Simulation Interval. Simulation Instant. t=0. t ∈]0, 3[. t=3. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 64 / 70 >.
(150) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Cosimulation of SystemC and Extra-Functional Solver. SystemC. P/To. Matthieu Moy (LIP). Function. Fonction. .... P/To. Transaction-Level Models of SoCs. February 2018. < 64 / 70 >.
(151) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Cosimulation of SystemC and Extra-Functional Solver. SystemC. P/To. 1 Function. Fonction. .... P/To. 1 SystemC runs simulation up to end of instant t. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 64 / 70 >.
(152) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Cosimulation of SystemC and Extra-Functional Solver. SystemC. 1 Function. Fonction 2. P/To. .... P/To. 1 SystemC runs simulation up to end of instant t 2 SystemC sends a request for extra-functional simulation on [t, t + d]. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 64 / 70 >.
(153) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Cosimulation of SystemC and Extra-Functional Solver. SystemC. 1 Function. Fonction 2 3. P/To. .... P/To. 1 SystemC runs simulation up to end of instant t 2 SystemC sends a request for extra-functional simulation on [t, t + d] 3 Extra-functional solver does the computation on the interval. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 64 / 70 >.
(154) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Cosimulation of SystemC and Extra-Functional Solver. SystemC. 1 Function. Fonction 2. 4 3. P/To. .... P/To. 1 SystemC runs simulation up to end of instant t 2 SystemC sends a request for extra-functional simulation on [t, t + d] 3 Extra-functional solver does the computation on the interval 4 SystemC resumes simulation at beginning of instant t + d Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 64 / 70 >.
(155) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Extra-Functional Events End of instant 1 SystemC. P/To 1 SystemC runs simulation until end of instant t. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 65 / 70 >.
(156) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Extra-Functional Events End of instant. Next instant. 1 SystemC. P/To 1 SystemC runs simulation until end of instant t 2 SystemC requests a extra-functional simulation in [t, t + d] or until “too hot”. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 65 / 70 >.
(157) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Extra-Functional Events End of instant 1 SystemC 2 3 P/To. Too hot!. 1 SystemC runs simulation until end of instant t 2 SystemC requests a extra-functional simulation in [t, t + d] or until “too hot” 3 Extra-functional runs simulation, encounters stop condition Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 65 / 70 >.
(158) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Extra-Functional Events End of instant. Fire IT. 1 SystemC 2. 4 3. P/To. Too hot!. 1 SystemC runs simulation until end of instant t 2 SystemC requests a extra-functional simulation in [t, t + d] or until “too hot” 3 Extra-functional runs simulation, encounters stop condition 4 SystemC resumes earlier than expected with interrupt. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 65 / 70 >.
(159) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Extra-Functional Events End of instant. Fire IT. 1 .... SystemC 2. 4 3. P/To. Too hot!. 1 SystemC runs simulation until end of instant t 2 SystemC requests a extra-functional simulation in [t, t + d] or until “too hot” 3 Extra-functional runs simulation, encounters stop condition 4 SystemC resumes earlier than expected with interrupt. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 65 / 70 >.
(160) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Results. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 66 / 70 >.
(161) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Outline. 1. Introduction: Systems-on-a-Chip, Transaction-Level Modeling. 2. Compilation of SystemC/TLM. 3. Verification of SystemC/TLM. 4. Extra-Functional Properties in TLM. 5. Conclusion. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 66 / 70 >.
(162) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Conclusion. Transaction-Level Models of Systems-on-a-Chip Can they be Fast, Correct and Faithful?. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 67 / 70 >.
(163) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Conclusion. Fast I I I. Optimized compiler Parallelization techniques High abstraction level (Loose Timing). Correct I. Formal verification. Faithful I I. More ways to express concurrency Preserve Faithfulness of Temperature Models for Loose Timing. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 68 / 70 >.
(164) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. The new CASH Team, LIP (ENS-Lyon) Compilation and Analysis for Software and Hardware. HPC Applications. Sequential Program. Polyhedral Model Parallelism Extraction. Parallel Program. Optimization. Analysis. Intermediate Parallel Representation. Dataflow Semantics. Abstract Interpretation. Hardware (FPGA). Code Generation. Software (CPU & accelerators). Simulation. Christophe Alias, Laure Gonnord, Matthieu Moy Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 69 / 70 >.
(165) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Questions?. Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 70 / 70 >.
(166) SoCs and TLM. Compilation. Verification. Extra-functional. Conclusion. Sources. http://en.wikipedia.org/wiki/File:Diopsis.jpg (Peter John Bishop, CC Attribution-Share Alike 3.0 Unported). http://www.fotopedia.com/items/flickr-367843750 (oskay@fotopedia, CC Attribution 2.0 Generic). Matthieu Moy (LIP). Transaction-Level Models of SoCs. February 2018. < 70 / 70 >.
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