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A 35.6TOPS/W/mm$^2$ 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric Applications

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Academic year: 2021

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Figure

Fig. 1.  Integration  scheme  of  the  proposed  C-SRAM  used  as  an  energy- energy-efficient vector processing unit
Fig. 3.  Proposed C-SRAM architecture based on two adjacent memory pages.
Fig. 5.  Horizontal  BL  metallization  scheme  enabling  adjustable  form  factor  for inter-page IMC operands (e.g
Fig. 9.  Benchmark platform using SystemC/TLM calibrated with silicon data.

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