the change letter and a serial subscript to appear here and on the page involved (there enclosed in a circle, triangle" or other attention-getting outline).

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NOTE: This page provides a running history of changes for a mUlti-page drawing which cannot conveniently be re-issued completely after each change. When making a change, list for each page all before- and-after numbers (within reason; use judgement, and use

"extensive" revision note if loss of past history is tolerable, or retype complete page) and associate with each a symbol made up

of

the change letter and a serial subscript to appear here and on the page involved (there enclosed in a circle, triangle" or other attention-getting outline).

Ltr REVISIONS

DATE

INITIALS

A As Issued

Model No.

I

Stock No.

Title l'vlonochrome Display Card 'l'heory of Operat·ion

Description Date

BV Steve Wolf Sheet No. 1 of 11

Supenedes Drawing No •. A-59 58-43 56-9

9320-3246 (6/15)

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TBEOOY OIl OPERAnOll

Revision

18

Jun

1985

Steve Wolf

DESCRIPTION Monochrome Display Card Theory of Operation

I

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1 Introduction • .

2

3

1.1 Coverage • . 1.2 Nomenclature

Communicating with the Card 2.1 Address Decoding Circuit . .

2.1.1 NLOREG • • . • . 2.1.1.1 NREAD1.

2.1.1.2 NwRITE1 2.1.i.3 NREAD3.

2.1.1.4 NWRITE3 2.1.2 NHIROM

2.1.3 / NlMAC 2.1.4 NTC 2.1.5 NFB

2.2 GeneratingNDTACZ(

2.3 Data Signals Reset Circuitry 3.1 Soft Resets

3.2

Hard Resets 4 Interrupts . • •

. 5 How the Clock Circuit Works

6

Video Output Circuitry • . • .

6.1

Low-resolution Video Circuit

6.2

High-resolution Video Circuit 1 RAM Management • • . . • . • ^{0 • . • •}

See Pg. 1 for Revs.

4 4 4 5 5 5 5 5

e 0 It • • 0 5

5 6 6 6 6 6 6 7 1 1

.

⁸

9 10 10 10·

11

,DESCRIPTION Monochrome Display Card Theory, of Op'eratio~ ^Dwg N"A-5958-4356-9 PAGE 3 of 11

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Introdudicm:

1.1 Coverage.

Chapter 1

'rhis document covers the internal workings of the two flavors of monochrome display boards for

98542A

made from the

98542-26510

printed circuit board. These two products are the medium-resolution

(1024

x

400

pixels) display board

(98542A)

and the high-resolution

(1024

x

168

pixels) display board

(98544A).

1.2 .0000000el.ature

In this document and on the

98542-66510

schematic, an 'N' before a signal name denotes that' the s'ignal is active-low, or 'negative true'.

Bus signals are differentiated from buffered signals by the presence ,or absence of the 010 'B' nomenclature. For example, NBAS is Bus Address Strobe (active-low) and NAS is Address Strobe after it has gone through the

14ALS244

input buff6r.

A dollar sign before a number indicates that the number is in hexidecimal representation.

See Pg. 1 for

Revs.

DESCRIPTION Monochrome Display Card Theory of Operation

I

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2.1 Jddreas Decodq Circuit

Chapter 2

The heart of the address decoding on'the Display Board is a

16L6

Programmed Logic Array (U28). In order to get all the needed address and control lines into the sixteen

"inputs of the PLAt two groups of five ,address lin'es (A2-A6 and A7-Al1) are fed through five-input NOR gates (U44) and then into the PLA. When the lower bits of the address are in the rang'e $000 - $003, the outputs of the NOR gates are high.

/ ^' The PLA's decoding

Output Signal Pin

16

^(NLOREG)

Pin

17

(NHIROM) Pin 18 (NIMAC) Pin 20 (NTC) Pin 21 (NFB) 2.1.1 BLmEG

signals are as follows:

, Address Ran~e (hex), 560000:5 0003 560004: 563FFF

020000:02FFFF; 560000:56FFFF 020000:02FFFF; 564000:565FFF

020000:02FFFF

Signals HAS low

NAS low, R/NW high NAS low

NAS low HAS low

This signal indicates that either the ID Register or the Interrupt Register is being addressed. It is further decoded by the 74ALS138 3-to-8 Demultiplexer

(U36)

into NREAD1 '(Read ID Register), NWRITE1 (Write ID Register), NREAD3 (Read Interrupt Register), and HWRITE3 (Write Interrupt Register).

2.1.1.1 IREAD1

The 10 of the Display Board is contained in the 2764 Display ID ROM (U11). This signal enables the ROM.

2.1.1.2 BWRI!E1

A write to the ID Register is d~fined 'a,s a soft reset. The effects of a soft reset ,are discussed in Section 3.1.

I

^-:.,!. 2.1.1.3 1RlW>]

_ The Interrupt Register (U37) contains the interrupt level bits

(3)

and interrupt enable bit. The interrupt request bit comes from the 'CRT Controller. These bits are sent through a 74ALS244 Buffer (U38) to the Data Bus. Tbe NREAD3 signal enables this buffer.

I

^2.1.1.4 This signal, combined with the NDTACK generation signal (U32-8), clocks the Interrupt ^~3 Register (U37). which contains the interrupt level and interrupt request bits. The inputs to the four latches are connected to the appropriate data lines.

-: ":, __ .':';:: •. 1 -1...,... ; I tor Revs.

DESCRIPTION Monochrome Display Card Theory of Operation

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2.1.2 JIB.iRaI

NHIROM enables the

2164

Display ID ROM (U11). The contents of this ROM are discussed in the Display ID ROM Definition.

2.1.3 nitAc

When the Display Board is addressed, it must return an "I Am Addressed" signal within 50nr:a if it i"s connected to a DIO Expander. For testing purposes, the NlMA signal is made available on the Display Board, but is not connected to anything.

NlMAC ("I Am Addre·ssed 'Control") enables the NlMA and NDTACK buffers (U21A and U270).

It is ANO'ad:with HAS because when NAS goes away, the Display board must stop driving NlMA and NDTACK sooner than the time it takes for NlMAC to go inactive.

NlMAC also determines when the Bidirectional Buffers (U31 and u4o), handling the data signals are enabled.

2.1.4 JI.L'C

The TOPCAT.Enable signal is doubly synchronized through a Hex Flip-Flop (U18) to become NSTC (Syncronized TOPCATEnable). It then drives the Chip Select pin of the TOPCAT Chip (U5).

2.1.5 IIFB

The Frame Buffer signal tells when the frame buffer is being addressed. This signal, after being. inverted to FB, drives the FB/NTC pin of the TOPCAT Chip. It also enables some grounded buffers (U27B, U27C, u45B, aildU29)' so that the seven "unused planes" on the board return zeros during frame buffer reads.

NDTACK comes from one of·two places.

If

the CRT Controller (U5) is being accessed, it generates NTCDTACK by itself, which is passed on as NDTACK. If anything in the $560000 ...

$56FFFF address space other than the CRT Controlier is addressed, NDTACK is "generated by a shift register (U4.2). A BEGINDTACKsignal is generated through U41D when either NLOREGo'r NHIROM is active. This signal pulls the RESET pin of the shlft register up so that the register can start shifting Ones.

On the low-resolution board (98542A), the third clock pulse to the shift register generates NDTACK, and on. the high-resolution board (98544A), the fifth clock pulse generates NDTACK. The ROM access time remains constant (200nS), but the clock is faster on the high-resolution board than on the low-resolution board. NDTACK is generated for any a.ccess to the display address space, whether or not valid data is returned. For exalliple, a byte read to location $560000 will receive a data acknowledge, even though the IIdata" is garbage.

2.3 Data Signals

The direction of the Bidirectional Buffers handling the data signals (U31 and U49) is determined by the R/NW signal. However, they are enabled only when the Display Board address space is addressed'(indicated by NlMAC being active}. In addition, only the Dyte(s) address'edare enabled (indicated by NUDS and NLDS).

~~

?g.

^{1 for} Rev~

DESCRIPTION Mono'chrome Display Card Theory of Operation

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Reset Circui

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3.1

Sort Re.~t~

Chapter

3

A soft reset can occur by writing to Register 1 ($S60001) or by pulling the NRESET signal active whiie NliALT remains inactive. The soft res'et is not allowed to alter the setup parameters of the CRT Controller (US). The only fUnction of this write is~o clear the 'Interrupt Register

(U37).

Note that a soft reset does not clear the bit that

indicates apel,lding interrupt from the CRT Controller.

After,a soft reset, the interrupt level is set to zero, and int~rrupts to the DIO bus are disabled by disabling the 74LS1S6 3-to':;'S Demultiplexer chip (u47) that drives those

interrupt line,s (NIR1 - NIR7). If interrupts are enabled before changing thei,nterrupt

~ level with a wr,ite to Register 3, there still will be no interrupts to 'the processor, since the non-maskable interrupt (NIRO) is not on the bus.

3.2

Bard Resets

A hard reset occurs when NRESET and NHALT are both active. It clears the Interrupt Register in the same way a soft reset does. In addition, it is doubly synchi"onized through two D-type Flip Flops (U3S) and drives the NRESET pin on the TOPCAT Chip. This causes all registers in the TOPCAT to do whatever the TOPCAT ERE says they ^dOt wiping out

" all initialization that may have be'en done.

Hard resets get the entire card, including the TopcAT Chip, into a known state, with r the exception of syncronizing the clock circuit. The clock runs and rUns and runs with

~ total disregard for hard resets. When a hard' reset goes away, the aforementioned synchronizer guarantees that the TOPCAT Chip is synchronized with the clock circuit, rather than having to synchronize the clock circuit to the TOPCATChip.

See

pg. \ tor

Revs.

L~SCRIPTiON

Monochrome Display Card Theory of Operation Owg No. A-=-S95B-4356.. PAGE 7 of 11

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Interrupts

", . \

Chapter

4

The Interrupt Register is defined in the DIO spec. Part of this register is the

inte~rupt level bits, which define a level froin one to seven. These three bits are sent to a 3-to-8 Demultiplexer with open-collector outputs

(U47)

which drives the appropriate

interrupt line. '

Another bit in the Interrupt Register enables or ,disables 'interrupts from the card.

This bit has j;o be high for an interrupt from the TOPCAT Chip to enable

u47

and drive an interrupt line •

DESCRIPTION Monochrome Display C,ard Theory of Operation, Dwg Nc. A::';>~435"e'-~ ^IPAGE ~ of 11

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^the Clock Circui't

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---~---~---~---

Chapter 5

,I

~ The clock signal originates, of course, in the oscillator (Yl). It is immediately : buttered by a screaming-fast inverter (U32C). This buffered signal runs the video output , shift register (016) and two pairs of J-K Flip-Flops (U33 and 011).

The first pair of J-K Flip-Flop~ (U33)is set up so the ii,rst toggles on ea.ch clock (divide-by-two) and the second toggles on every other clock (divide-by-four). Thus, the

Flip~Flop pair runs through four distinct states, which can be defined by the Q-outputs as : 00, 10, 01, and 11.

The TOPCAT chip takes the clock supplied to its NCLK pin, which is the oscillator frequency divided by two, and intf:!rnally divides it by two again. The outside world must keep track of the internal clock, so it knows when the video information on pins Vl - v4

is valid.

If the NRESET signal to TOPCAT is pulled high during a certain window of the NCLK, signal,- the internal clock phase is known. The double synchronizer in the NRES circuit guarantees that NRESET goes high between states 10 and 11 of the clock circuit, since the synchronizer Flip-Flops are clocked by the Q-output of the second (divide-by-fou:r) J-K Flip-Flop.

With the state of the .internal TOPCAT clock known, the Video Shift Register (u16)'is loaded at the transition from State 01 to State 11. This is what the second pair of J-K Flip-Flops (U11) accomplishes. The first half of the pair d'elays the divide-by-four signal. by one state. The second half has a 2510 duty cycle and loads the Video Shift Register at the appropriate state. The following table shows the outputs of various gates

l in the four states.

!

, ,

)

'~

State U33-6 U33-10 U33-6 U11-9 u16 mode

0 0

0 0 - 1 - 0 SHIFT

10 1 0 0 0 SHIFT

01 0 1 0 1 LOAD

11 1 1 1 0 SHiFT

The'synchronizer-circuit for the NSTC, NSLDS and NSUDS signals (U25B and U18) is triggered on the transition from State 00 to State 10. By a quirk of fate, the D-type Flip-Flop output (U25-8) has the same signal as J-K Flip-Flop output'U11-6. This was a 'design,oversight and could be eliminated if the board is turned. U25 and its pullup (R16)

can be removed and U11-6 can be connected to U18-9.

See Pg.

1 f('ir

Revs.

DESCR.IPTION Monochrome Display Card Theory of Operation

I

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Video OIltpit Cirmitry

6.1 Low-resolution Video Circuit

Chapter

6

The low-resolution circuit is designed to send a composite video signal out .to the monitor, with sync signals from 0 - .3V and video trom

.3 -

1.0V. This circuit was leveraged from the 98204B Composite Video Card.

TransistQr Q2 is held ata certain bias level by the diodes and resist.ors around it.

Syncs and video pull various amoWlts of current out of its base, changing the voltage level at its collector. Since the 98204B card had a halt-bright mode, the circuit use's two transistors for .the video signals, and one for horizontal and vertical sync. For more 'detail cn this circuit, see the Theory

ot

operation for the 98204B Card.

6.2

High-resolution Video Circuit

The high-resolution circuit sends a TTL-level video signal out ot a

BHe

connector, and horizontal and vertical sync out of a n-subminiature connector. This circuit was

leveraged from the

9831.

The sync signais

and

12V that go out on the D-subminiature connector go through a liT-filter" that helps to keep the video signal off of the board it it bleeds onto these lines in the monitor. The protection diodes are to keep bad things from happening if the user accidentally plugs an RS-232 cable onto the sync connector.

The 12V is used in the 98781A monitor to enable its power supply (with a relay) and power an Hp·HIL repeater (which in turn can power up to seven HP-HIL devices).

The video signal runs through a; drive transistor in the transistor pack. which is kept out of saturation (and thus sped up) with a Shottky diod~

(cR4)

from base to collector.

- . .:,;,. , 'or

Rev$,

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DESCRIPTION Monochrome Display Card Thf;0ryof Opera.tion

I

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]---~---~---

Chapter

7

The TOPCAT Chip nicely takes care of all RAM refreshing and HAS/CAS generation·~ sol

~ didn't have ,to .

t~ESCRIPTION MonochrC?me Display Card Theory of Operation Dwg NC·A-5958--:-4356-9 PAGE 11 of 11

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