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The mixed analog/digital shaper of the LHCb preshower
J. Lecoq, G. Bohner, R. Cornat, Pascal Perret, C. Trouilleau
To cite this version:
J. Lecoq, G.Bohner, RemiCornat,P.Perret, Cyrille Trouilleau(nowat Thales) L.P.C. Clermont-Ferrand,UniversiteBlaisePascal,63177AUBIERECedex
lecoq@clermont.in2p3.fr
Abstract
TheLHCb preshowersignalsshowso many uctuations atlowenergythataclassicalshapingisnotusableatall. Thankstothefactthatthefractionofthecollectedenergy duringawholeLHCbeamcrossingtimeis85%,we stud-ied thespecial solutionwepresentedat Snowmass 1999 workshop. This solutionconsistsof 2interleaved fast in-tegrators,onebeingin integratemode whentheother is digitallyreset. Twotrack-and-hold andananalog multi-plexerare used to give at the output 85% of the signal plus 15% of the previous one. These 15% are digitally computedfrom the previoussample, and subtracted. A completely new design of this solution had to be made, see gure2. Thisnewdesignis described,includingnew methodstodecrease thesupplyvoltageandthenoise,as wellastoincreasethequalityoftheresetandthe linear-ity. An output stage, consisting of aABclass push-pull usingonlyNPNtransistorsisalsodescribed. Laboratory andbeamtestresultsaregiven.
I. Introduction
The LHCb preshower is used for the level 0 trigger, for which a threshold corresponding to 5 minimum ioniza-tionparticle(MIP)is applied, witha5%accuracy. This detectorisalsousedtoimproveelectronandphoton mea-surement up to 100MIP. These two functions give us a dynamicrangeof 0.1to100MIP(i.e. 10bits).
Thestudyofthesignal[1]givenbyascintillatorcelland the64 channels HammamatsuPMT, witha good agree-mentwiththeirsimulation, showsus thatat lowenergy, the dominant e ect is the statistical uctuation of the photoelectron collection, while at high energy the domi-nante ectisthePMTsaturationwhichbeginat0.6mA, see gure1. Theseconditions,andthefactthatthesignal lengthisalwayslongerthan25ns,driveustothesolution described before. We don't change the main electronic choiceswemadeon1999[2]:
afullydi erentialdesigntominimizethenoises; bipolartransistorsat theinput stagesto reduce the
o sets;
CMOStransistorstosavepowerand design integra-torswitches;
AMS 0:8m BiCMOS technology and CADENCE
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Figure1: cosmicevents
However,wehadtoredesignthechipduetothefollowing considerations:
because of thePMT saturation, wehad to increase thegainbyafactor20,andthenwehadtotakemore careofthenoiseando sete ects. Forthenoise,the integratorinputstagewaschanged,andfortheo set and the operating point stability a special common modefeedbackloopwasadded;
weneedaveryhighqualityreset,tobeableto com-pute thesubtractionwith anegligibleerror,evenin thecasesofamaximumsignalimmediatelyfollowed by a "trigger level" one: the integrator itself was changed;
thesupplyvoltagehadtobedecreaseddownto 2:75V to matchthefoundryspeci cations,andto obtainthe"smallpowerconsumption"of100mW/channel; to carrythe 6000outputanalogsignals, weplan to
we have to drive eÆciently the cable without extra chips: an "all NPN A-B class push-pull " was de-signed.
II. Design considerations
Mostblocksofthechiparedesignedaroundasimple bipo-lardi erentialpair: thisschemeisstable,easytouseand economic in term of silicon area. Inaddition, in a fully di erentialdesign, each signal hasits opposite, which is veryuseful to compensate parasitice ects. In ourcase, we have to take care of the linearity : our calibration willbedoneessentiallybytheMIPvalueswhichareonly 10ADC counts. Forthis reasonweneedanon linearity smaller than 1%, and we have ve blocks (i.e. ve non linearitysources)in serial,see gure2.
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Ω
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Figure2: onechanneldesign
Itis well kownthat thenon linearityof di erentialpair, essentiallyduetothevariationofthebase-emittervoltage ofthetwotransitorsiseasilycorrectedbytheadditionof onediode(gainof1),ortwodiodes(gainof2)inthe col-lectorbranchestoobtainthesamevoltagedropinemitter andcollectorload,see gure3. However,theconsequence ofthis "serialcorrection" isthe lost of oneortwodiode voltagedropswhichisincompatiblewithalargedynamic rangeusingsmallvoltagepowersupply. Theideawe ex-ploreto overcome this problem is to replace this "serial correction"byaparallelone,see gure4.
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Figure4: parallelcompensation
Figure5: without Figure6: under
Figure7: over Figure8: right
Inthisnewcorrection,thelostofgainiscompensatedby decreasingtheemmitterloadin theoposite branch. The gainobtainedisdouble: weobtainaverygoodcorrection withoutlostofdynamicrangeandtheover-compensation ispossible. Thisisusefultocompensatestwostageswith onlyoneparallelcorrection.
As anexample,see gure3and4,onthis application, a gain of 2 is needed in the multiplexer stage: using this correctionanonlinearityerrorofonly100V was ob-tainedfora4volt(2V)dynamicrangeincludingoutput stage,using a2:75V powersupply. Figures5,6,7and 8 shown the error obtainedin this example in the cases of no compensation (5), under-compensation (6), over-compensation(7)andrightcompensation(8).
areall bipolar, low level, ECL,and theCMOS clocksof theintegratorsaregeneratedinsideeachintegratorblock.
III. Building blocks
1.-Common to differentialmode block (C2DM) The nalschemechosenisavoltageinputcurrentoutput block,insteadofthevoltageampli erofthe rstversion, see gure 9. The C2DM outputs can be considered as grounded(virtual groundof theintegrator): i1= i2= Vin=2R
0 .
Thevalueof the curent I determines only the speed, as the values of r and V only the operating output point, providedthatthevalueofrremainshighwithrespectthe integratorinput impedance. These valuesare optimized forthenoise,thepowersupplyisreducedby3diodesand darlingtontransistorsareusedtoreduceinputcurentand allowto settheoutputoperatingpointnear theground.
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Figure9: C2DMand integrator 2.-Switchedintegrator
Thisblock,see gure9,isbuiltaroundthewidebandhigh gainampli er. Ithastwogainstages,the rstisoptimized tominimize theo set,thesecond isarailto railCMOS output. Theconnectionbetweenthetwostagesisasimple followerforthePMOS'sanda xedvoltagedrop(diodes andresistorat constantcurrent)fortheNMOS's. Twooriginalitiesareimplemented:
Duringthe integrate phase, from the DC point of view, theintegratoris an open loop high gainampli er: as a consequencethe o set and the operating point stability arecritical: fortheo setgreatestcare was takenonthe inputstage(resistorloadandtransistorsdoubledand de-signedasacross),andanextrafeedbackloop,actingonly onthecommonmodesignalwasaddedsee gure10: rst thecommonmodevoltageisobtainbysummationofthe twocomplementaryoutputswith2resistors. Thisvoltage isthencomparedtogroundandtheerrorresultampli ed
Asaresult,theoutputcommonvoltageismaintainedto ground,andtheo setisreduced.
During thereset phase, inputs and outputs are shorted. As aconseqence thegain becomes very lowand the vir-tual ground is not achieved. To overcome this problem two extra switches are added at the inputs. The four switchesaredesignedwithcomplementaryMOSasusual tominimisetheinjectedchargee ect.
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Figure10: AOPwithC.M.feedback
Results: thesimulationresultsshowagainof5000anda veryhighqualityreset. Thesimulatedlinearityisperfect. An integrator was realized and tested alone. The test results arein verygood agreementwith the simulation: the o setsmeasured at the output vary from a few mV toamaximumof100mVand thelinearityisbetterthan ourmeasurementcapability.
3.-Track andHold
Theused structureis described byPieter Vorenkamp [3] andJean-MarieBussat[4],andalreadyusedanddescribed severaltimes. Thecompensationofthebaseemitter par-asitic capacity was unchanged,but the"serial" linearity compensation was replaced by our new parallel one to be more confortable on dynamic and also to obtain the output operatingpointas high aspossible. Under these condition, the 1V dynamic range waseasily obtained with a linarity of few perthousand. These results were con rmed by the tests of the prototypes, see the LHCb website [5].
4.-Differential analog multiplexer
Thecircuitwasinterestingtodesign: inthis nalversion itisthekeyblockwherewehadtogofrom1V to2V dynamicrange, ina25ns multipexingoperationwithout anycrosstalkfrom oneinputtotheother.
Westartfrom thesimpleswitchoftwoidentical di eren-tialpairsofthe gure11. Thisschemeshowsthefollowing imperfections:
out
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Figure11: multiplexerdesign
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Figure12: multiplexerdetail rectedwiththe"parallelcompensation";
asonmanyothermultiplexers, thereisalittlecross talk between thetwo inputs, specialy when the un-usedinput isfastand high. Here thisfact is due to thefact that theblockedtransistorsof thenonused inputactasparasiticcapacitorandinjectonthe out-put alittle partof their own signal. Thanksto the factthatthisdesignisfullydi erential,weusedtwo extra transistors, always blocked, to inject also the opposite parasites, see gure 12. Notice that the 4 transistorshaveexactlythe samebase andcollector operating points. As a result, the compensation is perfect, andthecrosstalkdisappearsfully.
5.-Output buffer
The output bu er is also a challenge: the consumption oftheveryfrontend board isverycriticalaswehaveto handle 64 channels and drive them on 20 meter cables, ona77cmPC board includind the64channel photo-tube! A true class B orAB push-pull using only NPN transistorswasdesigned. It canbeseenonthe gure13 that transistorsT1 acts asausual complementary push pull. ThetransistorT2,whichreplacestheclassicalPNP isdrivenbyacontolloopforwhichthetransistorsT3,T4 andT5are added. T1+T3andT4+T5formacurrent mirror: they havesame base and same emitter voltage. Afraction of theoutput current,determined bythe size
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Figure 13: bu erdesign
ratioofT1,T3andT4,T5,is"measured"byT4+T5and subtractedtoI
ref
. ThepartofIrefwhichisnottakenby T4,T5isapplytothebaseofT2bythePMOStransistor. Itiseasytoverifythatthisfeedbackisstable: ifapositive signaloccurs,thecurrentofT1increases,itsV
be
increases andthentheV
be
ofT4andT5increase. Asaconsequence, morecurrentistakentoI
ref
byT4andT5andthecurrent given toT2by thePMOSdecreases to allowtheoutput voltagetoincrease. Thesameanalyzeis easytodowith anegativegoingsignal. Thesimulationcon rmsthatthis circuitisatruepushpull. It isinterestingto noticethat thecurrentfeedbackparametersarenotcriticalatall,and veryeasy to adjust. It is also interestingto notice that themaximumdynamicrangewecanreachisonlylimited bythepowersupplyandthelostoftwoV
be
(T1andT3), exactlylikeinacomplementaryPushPull. Thefollowing tableshowstheresultswhichcouldbeeasilyreachedwith thisoutputstagefor3di erentquiescentcurrents:
powersupply quiescent linearityerror risetime currents on2volts
2:75V 25mA 2mVmax 2ns 2:75V 16mA 5mVmax 3.5ns 2:75V 12mA 8mVmax 5ns For our application, we chose to operateat 16mA. No-tice that, asexplainbefore, the5mV nonlinearity error wascorrectedintheparallelcompensationoftheprevious stage to reach, insimulation100V errorwiththetwo stagestogether.
IV. Measurements
oratoryandtest beamtestand measurementweredone, theirresultsaresummarizedbellow.
1.-Laboratoty tests
O set: asexpectedo setdispersionislowerthan100mV. Gains: the gain dispersion (few per cent) is negligible behindthechannelgaindispersionofthephototube. Switchingand risetime: theresultsofthe "multiplexer-bu eralone"test show theirtotalagreementwith simu-lation,withoutanyovershoot,andwiththepredictedrise time.
Globallaboratotytestsaresumarizedin gures14and15 whichshowthesimulatedoutputjust near themeasured one,and quanti ed bya global measure ofthe linearity, whichis themostimportanttest. Aswedidn'thaveany very precise pulse generator in term both of time jitter and amplitude, we test the chip on its worst operating mode; i.e. with averylarge input pulse given by athe AWG2022 Tektronix 12 bits arbitrary waveform gener-ator. The output of thechipis then transmittedto the sameADC driverasused onthefrontend boardand to the14bits65MS/sADC AD6644. Theresultwhich rep-resentsthe sum of errorsof the generator, the chip, the opampand theADC isshown gure 14. Thismeasured errorislessthanoneLSBforthelowsignalsandlessthan onepercentalong thewholedynamic range. As this er-rorisinthesameorderofmagnitudeoftheseofourtest bench, the fact that they are not exactly so good than thesimulatedonesisnotsigni cant. Inanycase,they t withtherequirementsoftheexperiment.
Figure14: linearity Figure15: chipin/out
Thenoisewasmeasured: weobtainthevalueof 650V which tsourrequirement,asitislesthanoneLSB. 2.-Testbeam results
During the last LHCb test beam (september 2001), we test for the rst time the nal version. The gure 17 shows the output of the chip after a 15 meter cable for one MIP. The noise value, see gure 16, was obtained byhistogrammingthechipoutputfewperiodsbeforethe trigger.Thevalueof700V weobtainshowsthat,inthe poorconditionsofthistest, theperformancesofthechip
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Figure17: theMIP V. Conclusion
Themixedanalog/digitalshaperoftheLHCbpreshower, basedonswitchedintegrator,trackandhold,multiplexer andcablepushpulldriverwassuccessfullydesigned, real-izedandtested. Theresults,inverygoodagreementwith simulationsgive:
a dynamic range higher than 2V with 2:75V powersupply;
a linearity better than 1% or 1mV over the whole dynamicrange;
anoisesmallerthan650V;
aconsumptionof100mW perChannel; asiliconareaof1:5mm
2
perchannel,8channelsper chip.
Thanksto thefull di erentialdesign, all the corrections wereeasilydone,andtheoutputnoisewasnota ectedat allbythe40MHzclock.
References
[1] Gerard Bohner and al., "LHCb Preshower Signal characteristics",LHCbnote2000-026.
[2] Gerard Bohner and al., "A mixed analog/digital shaper for the LHCbpreshower", Fifth worshop on electronics for LHC experiments, september 1999, Snowmass.
[3] PieterVorenkamp, JohanP.M. Verdaasdonk."Fully bipolar, 120-Msamples/s 10-b Track and Hold Cir-cuit." IEEE journal of solid-state circuits, July 7, 1992.
[4] Jean-Marie Bussat, these de doctorat "Conception d'un dispositif d'acquisition rapide de grande dy-namique..."5juin 1998.
