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InGaAs SINGLE- AND DUAL-GATE HIGH-SPEED FETs : PREPARATION AND PERFORMANCE
K. Steiner, K. Ntikbasanis, U. Seiler, K. Heime, E. Kuphal
To cite this version:
K. Steiner, K. Ntikbasanis, U. Seiler, K. Heime, E. Kuphal. InGaAs SINGLE- AND DUAL-GATE
HIGH-SPEED FETs : PREPARATION AND PERFORMANCE. Journal de Physique Colloques,
1988, 49 (C4), pp.C4-205-C4-208. �10.1051/jphyscol:1988442�. �jpa-00227940�
InGaAs SINGLE- AND DUAL-GATE HIGH-SPEED FETS : PREPARATION AND PERFORMANCE
K. STEINER, K. NTIKBASANIS, U. SEILER, K. HEIME and E. KUPHAL*
Universitilt Duisburg, Halbleitertechnik/ Halbleitertechnologie, Sonderforschungsbereich 254, 0-4100 Duisburg, F.R.G
'~orschungsinstitut der Deutschen Bundespost, 0-6100 Darmstadt, F.R.G.
Abstract:
The preparation and performance of self-aligned single- and dual-gate InGaAs JFETs is discussed.
Single-gate InGaAs JFETs exhibit maximum extrinsic transconductance of 350, 275 and 140 mS/mm a t a gate length of 0.5, 1.5 and 3.5 pm, respectively. High overall potential barriers at the channel substrate heterointerface are necessary for control of threshold voltage uniformity over a wide range of gate lengths. For the first time device behaviour of self-aligned dual-gate InGaAs JFET is demonstrated.
1. Introduction
The compatibility with optoelectronic devices in longwavelength optical communication systems, the high electron mobility and velocity makes InGaAs lattice matched to InP attractive for microwave devices and amplifiers in OEICs. In the case of InGaAs FETs the low Schottky barrier of n-InGaAs /1/ prevents the fabrication of MESFETs. To overcome this problem high band gap materials such as GaAs /2,3/, InP /4/ or InAlAs /5/ were grown on top of the channel or InGaAs MISFETs were realized / 6 / . The best way to realize InGaAs FETs seems to be the JFET. This is due to the high potential barrier of the pn-junction which is solely determined by bulk properties.
The pn-junction can be implanted /7,8/, diffused /9,11/ or grown by epitaxy /12-14/. State of the art are submicron high speed InGaAs-JFETs with self-aligned structures, which reduce parasitic resistance, noise and the mask-alignment effort. They achieve cut-off frequencies above 30 GHz at a gate length of 1.2 pm /15/ and above 70 GHz a t a gate length of 0.5 pm /14/, extrinsic transconductances of 330 mS/mm for normally on /11/ and 550 mS/mm for normally-off devices /lo/. In this work the fabrication and device performance of mesa type self-aligned single- and dual-gate InGaAs JFET with diffused gates is discussed.
2. Samvle Prevaration
All layers were grown by LPE. The growth started with a Zn doped p-InP buffer layer (p<1017 cm-', =0,4 m) on s.i. 1nP:Fe substrate (Sumitomo). It is followed by the n-InGaAs channel layer (1.10~' cm-
8 ,
0.40 pm). This layer is lattice matched a t growth temperature to the InP buffer layer.The p + - ~ n ~ a ~ s layer is diffused from Zn doped spin-on film sources into the n-InGaAs. The pn- junction is diffused because thermal degradation effects during the fabrication process are lower as compared to ion-implanted and annealed or epitaxially grown layers /9/. The doped emulsions are spun on and dryed in air a t about 100 OC for 30 min. During the open tube diffusion the samples are covered with a quartz plate to prevent thermal degradation effects at the surface of the sample.
There is no mechanical damage due to the covering of the sample during the diffusion process.
The sample is diffused at 535 OC within IOmin. Hole concentrations well above 10'' cm-' can be reached /9/. The junction depth is controlled by the diffusion time and obeyes a Jt law.
For the T-shaped gate Al is evaporated onto the whole sample (200nm). It is followed by a photolithography step and a second metallization (5nm Cr, lOOnm Au). After lift-off the gate is defined by the CrAu patterns. The Al is selectively etched with a phosphoric acid (H3P0 : CH3COOH) using the CrAu cap layer as an etch mask. The T-shaped gate is completed by etchi4ng the p+-mesa. The source and drain metal is directly evaporated onto the undercut structure and thus ensures the self-alignment. It is followed by an additional bond pad metallization. The fabrication process is finished by etching the n-mesa.
Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988442
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PHYSIQUE3. Exoerimental Results
After gate forrnation a Hall-mobility of 7300 cm2/vs was measured on an ungated Hall-bar. From ma neto-transconductance measurements /16/ maximum drift mobilities between 5500 and 6500 cm /Vs were deduced. These values agree well with numerical Hall-factor calculations for InGaAs
H
bulk material with a background carrier concentration of about 1.10'~ ~ m/17,18/. Therefore it is - ~ concluded that the FET formation process does not degrade transport characteristics of the active InGaAs channel layer.
Fig. 1 displays DC-characteristics of InGaAs single-gate JFETs. Due to the T-shaped gate the gate lengths are 3.5, 1.5 and 0.5 ym. As it is expected /9/ the transconductance increases with decreasing the gate lengths. The maximum extrinsic transconductance comes up to 140, 275 and 350 mS/mm a t a gate length of 3.5, 1.5 and 0.5 ym, respectively. These are the highest values ever reported for normally-on InGaAs-JFETs in the submicron and micron gate regime.
With decreasing gate length short-channel effects appear; i.e. the saturation and pinch-off behaviour become worse. The threshold voltage shifts from -IV to -1,6V with decreasing gate length. This is about the order which was predicted in /19/ by numerical simulations of InGaAs- FETs. In contrast to these results InGaAs-FETs with highly doped (pINP > 1.10'~ cm-') and thick (0.8 pm) p-InE' buffer layers exhibit no threshold voltage shifts in the submicron gate regime / I I/.
InGaAs-FETs without buffer layer typically display tremendous short channel effects with decreasing gate length /6,9,13,18,20/. If a p-InP buffer layer is used it is assumed that the lack of short-channel effects is due to a better carrier confinement in the channel. The reason is a higher overall potential barrier at the channel-substrate heterointerface which is solely determined by the carrier concentration in the active region of the FET and the p-InP buffer layer. The high potential barrier suppresses carrier transfer from the channel into the substrate which may lead to the aforement~oned short-channel effects /21,22/. FETs without a buffer layer
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the channel is directly grown on the s.i. InP substrate - exhibit a channel-s'ubstrate potential barrier which is determined by the conduction band offset only (AEc w 0.22eV /23/). This is indicated by an accumulation layer in the InGaAs at the heterointerface /6,24/. In contrast to this accumulation layer a depletion region arises with increasing the distance between the Fermi-level and the conduction band edge in the InP; i.e. with doping the InP by acceptors. In the case of a small potential barrier a t the channel-substrate heterointerface an electron transfer from the channel into the substrate is probable especially at higher electron velocities. Therefore short channel effects occure with decreasing the gate length. As a result potential barrier tuning a t the channel-substrate heterointerface is necessary for the control of output characteristic at a certain gate length.Fig. 2 displays; device characteristics of self-aligned InGaAs dual-gate FFTs. The device consists of two gate electrodes (L,=1.5 pm) which allow a separate gain control by the second gate. The spacing between the two gates consists of a 4 pm wide floating metal layer. Fig. 2 clearly demonstrates the device behaviour. Biasing the second gate towards negative voltages strongly reduces the transconductance of the device. Such a dual-gate FET will find application in InP based high frequency mixers and oscillators.
In conclusion self-aligned single- and dual-gate InGaAs-JFET were fabricated on LPE layers.
Single-gate InGaAs-JFET exhibit maximum extrinsic transconductances of 350, 275 and 140 mS/mm a t a gate length of 0.5, 1.5 and 3.5 pm, respectively. For a better control of threshold voltage homogenity with decreasing gate length a high overall potential barrier a t the channel- substrate heterointerface is necessary. For the first time device behaviour of self-aligned dual-gate InGaAs-JFET is demonstrated.
The authors are indepted to Dr. G.Schlamp and G.Ptaschek (Demetron, Hanau, FRG) for preparation of the spin-on films and M.Bi)hm for assistance in device preparation. The work was supported by Deutsche Forschungsgemeinschaft.
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PHYSIQUEFig. 1: Output characteristics of self-aligned Fig. 2: Output characteristics of self-aligned single-gate 1nGaAs-JFETs in the same chip; dual-gate InGaAs-JFET, WG = 40 pm ND = 1 . 1 0 ~ ~ cm-', channel thickness a = 0.18 ND = 1.10'~ ~ m - ~ , a = 0.18 pm pm, gate width W, = 40 pm
