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PEDESTAL BIPOLAR TRANSISTOR WITH POLYSILICON ACTIVE BASE AND EMITTER WHICH ACHIEVES MINIMIZED CAPACITANCES
F. Hébert, D. Roulston
To cite this version:
F. Hébert, D. Roulston. PEDESTAL BIPOLAR TRANSISTOR WITH POLYSILICON ACTIVE
BASE AND EMITTER WHICH ACHIEVES MINIMIZED CAPACITANCES. Journal de Physique
Colloques, 1988, 49 (C4), pp.C4-375-C4-378. �10.1051/jphyscol:1988478�. �jpa-00227976�
JOURNAL DE PHYSIQUE
Colloque C4, supplbment au n09, Tome 49, septembre 1988
PEDESTAL BIPOLAR TRANSISTOR WITH POLYSILICON ACTIVE BASE AND EMITTER WHICH ACHIEVES MINIMIZED CAPACITANCES
F.
HEBERT*
and D.J. ROULSTONElectrical Engineering Department, University of Waterloo, Waterloo, Ont. N2L-3G1, Canada.
*~vantek Inc., Advanced Bipolar Products, 39201 Cherry Street , Newark, CA 94560, U.S.A.
~6sumii
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Des transistors bipolaires qui utilisent une couche de polysilicium doper de bore pour la base intrinszque (sur silicium monocristallin) et extrinseque (sur oxyde), et un gmetteurpolycristallin doper de phosphore, ont Qt6 realisgs avec des gains en courant inverses jusqu'd 10. Le processus de fabrication est bas6 sur la dgposition normale de couches polycristallines, suivie dtune recristallisation qui ddpent du doping.
Abstract
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Bipolar transistors using a boron doped polysilicon layer for the intrinsic (on monocrystalline silicon) and extrinsic base regions (on field oxide), and a phosphorous doped polysilicon emitter, have been realized with upward current gains up to 10. The process is based on standard polysilicon film deposition followed by doping dependent recrystallization.1
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INTRODUCTIONMinimized parasitic junction capacitances of bipolar transistors may be achieved by self-alignment and by locating the extrinsic base region on top of a thick oxide layer [I-41. The latter method, considered here, typically requires high temperature epitaxial film growth for the base formation [1,2,3] or photo-epitaxial equipment 1 4 1 . The results of such methods are similar: epitaxial silicon is formed over the monocrystalline Si (intrinsic region) and polysilicon forms where there is oxide
(extrinsic region).
In this paper, a polysilicon rather than epitaxial base is used in order to simplify the processing requirements. Polysilicon base devices (non self-aligned PNP transistors) have been realized by workers at IBM [5]
using an in-situ doped arsenic base, but low current gains and large capacitances have been obtained (rapid thermal anneal (RTA) was not utilized, and the extrinsic base region was not deposited on the field oxide). NPN transistors with minimized capacitances and recrystallized polysilicon base have been fabricated using RTA techniques. The
structure, referred to as the PEDESTAL transistor from its appearance (see Figure I), has been realized based on the doping dependence of the recrystallization of polysilicon films [ 6 ] . The recrystallization is performed prior to base doping in order to minimize the sensitivity of the base width to processing.
/- CONTACTS1
r
EMITTER ,-CONTACTFisure 1
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Cross-section of an NPN PEDESTAL transistor. The base and emitter are formed of polysilicon. The downward mode emitter is labelled.Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988478
C4-376 JOURNAL DE PHYSIQUE
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PROCESS DESCRICPTIONThe devices have been fabricated using a 3 Prn thick, 0.5 ohm-cm N type epitaxial layer grown on an N+ <Ill> substrate. After growth of a 0.5 pm field oxide, the intrinsic base area is patterned by etching of the
oxide. The base an undoped polysilicon layer of 0.5 to 0.6 pm is deposited at 5 9 0 ~ ~ using silane in an LPCVD reactor. An HF interface treatment (to remove any native or chemical oxide grown during any RCA clean) is carried out prior to poly deposition.
Since undoped polysilicon does not easily realign epitaxially (even after a 120 seconds 1 1 5 0 ~ ~ heat treatment) [6], but phosphorus (Ph) doped poly films do (even after a 30 seconds 1 1 0 0 ~ ~ heat treatment), a low concentration of phosphorus is introduced in the undoped poly layer in order to enhanc:e the recrystallization and epitaxial realignment with the substrate. The Ph furnace deposition conditions are 10 minutes at 6 5 0 ~ ~ followed by an 80 minute drive-in at 9 0 0 ~ ~ to redistribute the doping. It should be noted that an in-situ P dop d layer (with
concentration of the order of 1x10'~ to 1 ~ 1 0 ' ~ ~ m - ~ ) could also have been used (this was not investigated since the gas flow meters used in our LPCVD in-situ doped reactor cannot yield such concentrations). Rapid thermal anneal (RTA), is used to recrystallize the poly film [6] and the conditions are 1150 C for 40 seconds in oxygen.
The base layer is then boron (B) doped ( 9 0 0 ~ ~ process) yielding a base sheet resistance of approximately 150 ohms/square. An indication of the crystalline nature of the base layer is the time required for patterning similarly doped poly layers in KOH. Typical poly films etch in 4 minutes while the base layer of the PEDESTAL transistor required 42 minutes to clear, indicating that the layer morphology has significantly been altered.
The combination of Ph doping and RTA is responsible for the changed layer morphology since an identical poly layer to the PEDESTAL base deposited on a patterned test wafer, undoped when annealed at 1 1 5 0 ~ ~ for 120 minutes in 02, cleared in only 13 minutes using the same KOH solution.
The emitter window is defined through patterning of the base oxide followed by deposition of a 0.42m thick in-situ phosphorus doped N+ polysilicon film (deposited at 585 C, with 20-30 ohms/square). After RTA for activation of the emitter doping (40 seconds at 1 0 5 0 ~ ~ in nitrogen) the contact windows and metallization steps are performed.
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EXPERIMENTAL RESULTS1,-Vce characteristics of a PEDESTAL transistor are shown in Figure 2 (upward mode). The device characteristics are adequate for I ~ L operation:
BVCEO of 2.5 volts, Early voltage of greater than 13 volts and current gain greater than 5. The measured base width of the transistor is approximately 0.14 pm, partly within the polysilicon and epitaxial regions, as obtained from groove and stain measurements. Current gains of 10 have been obtained with the trade-off sf reduced Early voltage
(4 volts). The Gummel plots of a lOOxlOOpm upward transistor are shown in Figure 3. The collector surrent shows ideal behaviour and the leakage current is less than 5 pA/cm
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The base current has an ideality factor of 1.62. In the downward mode of operation, Ic is ideal, with low leakage.The collector saturation current (Is) of the transistor is near identical for either mode of operation, indicating a near symmetrical transistor
(upward Is of 0.99 fA and downward I of 1.22 fA) in terms of effective emitter area. The base current in tge downward mode is greater, with ideality factor of the order of 2 to 2.6 which is typical of polysilicon diodes [5,7,8]. The maximum downward current gain achieved is unity.
It has been observed through measurements of devices with equal emitter area but different perimeter, that the recombination is not only a function of the poly characteristics, but also of the oxide films covering the base layer (surface recombination). The base oxide has been grown using 8 5 0 ~ ~ steam oxidation rather than a higher temperature dry oxygen process, and
the poor quality oxide which results (cracking observed using a surface profiler) increase:; the surface recombination. This has been confirmed
through measurement of the base ideality factor of poly emitter
transistors with diffused bases in mono silicon, fabricated using the same base oxide: ideality factor of 1.4 rather than 1.0 is obtained, indicating that the surface recombination is non-negligible (also, devices with large emitter periphery to area ratios have lower current gains).
COLLECTOR -EMITTER VOLTAGE ( V BASE-EM ITTER VOLTAG E ( V
Fisure 2
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1,-Vce characteristics in Fi ure 3-
Gummel pl ts in the upward the upward mode of operation. The mo:e of a 100x100 pmS device. The base current values $re 1, 2, 3, 4 ideality factors for Ic and Ib are 1.0 and 5 mA. 100x100 pm emitter device. and 1.62 respectively.Test wafers have also been processed without RTA and Ph doping of the base polysilicon layer prior to boron doping. The resulting devices had current gains below unity and non-ideal Gummel plots (ideality factors for the base and collector current greater than unity). The poor performance is
attributed to non-ideal characteristics of the interface between the base layer and the emitter and collector regions since boron doped poly does not easily recrystallize and epitaxially realign 163, even after the final RTA used to activate the emitter dopant. Similar results have been obtained for test devices which received an RTA of the boron doped poly prior to the emitter deposition.
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TYPICAL APPLICATIONA typicah application considered for such a process is Integrated Injection Logic (I L). The lateral PNP device, required as injector, may be
fabricated by diffusing the base dopant into the N type substrate rather than into the undoped polysilicon layer, as shown in Fig. 4. This would require patterning the base polysilicon prior to doping, such as to expose the collector and emitter regions of the PNP transistor (one extra non- critical mask, no extra diffusions). Improved speed is possible due to reduced dimensions of the active area and reduced injection in the
extrinsic base when compared to diffused technologies [ 7 ] . Since the delay (due to the device) is proportional to the stored charge, the increase in switching speed is proportional to the reduction in active area of the transistor. For a typical 5 pm process, the reduction in active emitter area. (upward mode) when using the PEDESTAL process is approximately 5 times.
JOURNAL DE PHYSIQUE
CONTACT TO
N+ POLY COLLECTOR LATERAL PNP
CONTACT TO P POLY BASE
Fisure 4
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Cross-section of a I ~ L cell compatible with the PEDESTAL process.5
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CONCLUSIONSBipolar transistors referred to as PEDESTAL transistors have been fabricated using a boron doped polysilicon layer for the intrinsic and extrinsic base regions. The extrinsic base is formed on top of a thick field oxide in order to minimize the parasitic capacitances and minimize the effective upward emitter area. The downward emitter is formed using an in-situ phosphorus doped polysilicon layer. Current gains up to 10 and ideal collector current behaviour have been realized through
recrystallization of the polysilicon base layer. This has been achieved by depositing an undoped poly base layer and doping the layer very lightly with phosphorus prior to a rapid thermal anneal ( 1 1 5 0 ~ ~ for approximately 40 seconds) and prior to boron doping. T e PEDESTAL device is an ideal candidate for high speed low complexity I L logic.
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ACKNOWLEDGMENTS
The authors would like to thank Roger Grant of the SiDIC laboratory for the successful fabrication of the test wafers and for useful discussions
regarding technological issues.
REFERENCES
[I] D.D. Tang et.al., IEEE J. Solid-State Cir., SC-17, (1982), 925.
[2] T. Nakamura et.al., ISSCC Dig. Tech. Papers, (1981), 214.
[ 3 ] N. Oh-uchi et.al., Proc. IEDM, (1983), 55.
[4] T. Sugii et.al. IEEE Elec. Dev. Let., EDL-8, (1987), 528.
[5] P.M. Solomon et.al., Proc. IEDM, (1979), 510.
[6] M. Tamura et-al., Jap. Jour. Applied Physics, 24, (1985), L151.
[7] H. Mikoshiba, IEEE J. Solid-State Cir., SC-13, (1978), 483.
[8] J. Manoliu and T.I. Kamins, Solid-State Elec., 15, (1972), 1103
