1573.3

File Number 1573.3

5.6A, 100V, 0.540 Ohm, N-Channel Power MOSFET

This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power.

These types can be operated directly from integrated circuits.

Formerly developmental type TA17441.

Features

• 5.6A, 100V

• r_DS(ON)= 0.540Ω

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”

Symbol

Packaging

JEDEC TO-220AB

Ordering Information

PART NUMBER PACKAGE BRAND

IRF510 TO-220AB IRF510

NOTE: When ordering, include the entire part number.

D

G

S

SOURCE

DRAIN (FLANGE)

DRAIN GATE

Data Sheet June 1999

Absolute Maximum Ratings

IRF510 UNITS

Drain to Source Voltage (Note 1) . . . .V_DS 100 V Drain to Gate Voltage (R_GS = 20kΩ)(Note 1) . . . V_DGR 100 V Continuous Drain Current . . . I_D 5.6 A T_C = 100^oC . . . I_D 4 A Pulsed Drain Current (Note 3) . . . I_DM 20 A Gate to Source Voltage . . . .V_GS ±20 V Maximum Power Dissipation . . . .P_D 43 W Linear Derating Factor . . . 0.29 W/^oC Single Pulse Avalanche Energy Rating (Note 4) . . . .E_AS 19 mJ Operating and Storage Temperature Range . . . T_J, T_STG -55 to 175 ^oC Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s . . . T_L Package Body for 10s, See Techbrief 334 . . . T_pkg

300 260

oC oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. T_J = 25^oC to 150^oC.

Electrical Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV_DSS V_GS = 0V, I_D = 250µA, (Figure 10) 100 - - V

Gate to Threshold Voltage V_GS(TH) V_GS = V_DS, I_D = 250µA 2.0 - 4.0 V

Zero-Gate Voltage Drain Current I_DSS V_DS = Rated BV_DSS, V_GS = 0V - - 25 µA

V_DS = 0.8 x Rated BV_DSS, V_GS = 0V, T_J = 150^oC - - 250 µA On-State Drain Current (Note 2) I_D(ON) V_DS> I_{D(ON) x}r_DS(ON)MAX, V_GS = 10V (Figure 7) 5.6 - - A

Gate to Source Leakage Current I_GSS V_GS =±20V - - ±100 nA

Drain to Source On Resistance (Note 2) r_DS(ON) V_GS = 10V, I_D = 3.4A (Figures 8, 9) - 0.4 0.54 Ω

Forward Transconductance (Note 2) g_fs V_GS = 50V, I_D = 3.4A (Figure 12) 1.3 2.0 - S

Turn-On Delay Time t_d(ON) I_D≈ 5.6A, RGS = 24Ω, VDD = 50V, R_L = 9Ω, V_DD = 50V, V_GS = 10V

MOSFET switching times are essentially independent of operating temperature

- 8 11 ns

Rise Time t_r - 25 36 ns

Turn-Off Delay Time t_d(OFF) - 15 21 ns

Fall Time t_f - 12 21 ns

Total Gate Charge

(Gate to Source + Gate to Drain)

Q_g(TOT) V_GS = 10V, I_D = 5.6A, V_DS = 0.8 x Rated BV_DSS, I_G(REF) = 1.5mA (Figure 14)

Gate charge is essentially independent of operating temperature.

- 5.0 7.7 nC

Gate to Source Charge Q_gs - 2.0 - nC

Gate to Drain “Miller” Charge Q_gd - 3.0 - nC

Input Capacitance C_ISS V_GS = 0V, V_DS = 25V, f = 1.0MHz (Figure 11) - 135 - pF

Output Capacitance C_OSS - 80 - pF

Reverse-Transfer Capacitance C_RSS - 20 - pF

Internal Drain Inductance L_D Measured From the

Contact Screw On Tab To Center of Die

Modified MOSFET Symbol Showing the Internal Devices Inductances

- 3.5 - nH

Measured From the Drain Lead, 6mm (0.25in) From Package to Center of Die

- 4.5 - nH

Internal Source Inductance L_S Measured From The

Source Lead, 6mm (0.25in) From Header to Source Bonding Pad

- 7.5 - nH

Junction to Case R_θJC - - 3.5 ^oC/W

Junction to Ambient R_θJA Free air operation - - 80 ^oC/W

L_D

L_S D

S G

Source to Drain Diode Specifications

PARAMETER SYMBOL Test Conditions MIN TYP MAX UNITS

Continuous Source to Drain Current I_SD Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode

- - 5.6 A

Pulse Source to Drain Current (Note 3)

I_SDM - - 20 A

Source to Drain Diode Voltage (Note 2) V_SD T_J = 25^oC, I_SD= 5.6A, V_GS = 0V (Figure 13) - - 2.5 V

Reverse Recovery Time t_rr T_J = 25^oC, I_SD = 5.6A, dI_SD/d_t = 100A/µs 4.6 96 200 ns

Reverse Recovered Charge Q_RR T_J = 25^oC, I_SD = 5.6A, dI_SD/d_t = 100A/µs 0.17 0.4 0.83 µC

NOTES:

2. Pulse test: pulse width≤ 300µs, duty cycle≤ 2%.

3. Repetitive rating: pulse width limited by max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. V_DD = 25V, start T_J = 25^oC, L = 910µH, R_G = 25Ω, peak I_AS = 5.6A.

Typical Performance Curves

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE D

S G

T_C, CASE TEMPERATURE (^oC)

25 50 75 100 125 150 175

0

POWER DISSIPATION MULTIPLIER

0 0 0.2 0.4 0.6 0.8 1.0 1.2

T_C, CASE TEMPERATURE (^oC)

50 75 100 150

25 175

10

8

6

0 4 ID,DRAIN CURRENT (A)

2

125

ZθJC, TRANSIENT 10

1

0.1

0.01

10^-2

10^-5 10^-4 10^-3 0.1 1 10

SINGLE PULSE

t₁, RECTANGULAR PULSE DURATION (S)

DUTY FACTOR: D = t₁/t₂ PEAK T_J= P_DM x Z_θJC + T_C

t₂ P_DM

t₁ NOTES:

THERMAL IMPEDANCE (oC/W)

0.01 0.02 0.5 0.2 0.1 0.05

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves

10

1

10³

1 10 10²

0.1 ID, DRAIN CURRENT (A)

V_DS, DRAIN TO SOURCE VOLTAGE (V) OPERATION IN THIS

REGION IS LIMITED BY r_DS(ON)

T_C = 25^oC

10µs 100µs

1ms

DC T_J = 175^oC

SINGLE PULSE

V_DS, DRAIN TO SOURCE VOLTAGE (V)

10 20 30 40

0 50

10

8

6

0 4 ID, DRAIN CURRENT (A)

V_GS = 10V

V_GS = 8V

V_GS = 7V

V_GS = 6V V_GS = 5V V_GS = 4V PULSE DURATION = 80µs

2

DUTY CYCLE = 0.5% MAX

V_DS,DRAIN TO SOURCE VOLTAGE (V)

2 4 6 8

0 10

10

8

6

0 4

ID, DRAIN CURRENT (A)

V_GS = 10V

V_GS = 8V

V_GS = 7V

V_GS = 6V V_GS = 5V V_GS = 4V PULSE DURATION = 80µs

2

DUTY CYCLE = 0.5% MAX

V_DS ≥50V

PULSE DURATION = 80µs

T_J = 175^oC T_J = 25^oC

ID(ON), ON-STATE DRAIN CURRENT (A)

V_GS, GATE TO SOURCE VOLTAGE (V) 10

1

0.1

10^-2

0 2 4 6 8 10

DUTY CYCLE = 0.5% MAX

I_D,DRAIN CURRENT (A)

4 8 12 16

0 20

5

4

3

0 2

rDS(ON), DRAIN TO SOURCE

V_GS = 20V PULSE DURATION = 80µs

1

V_GS = 10V

ON RESISTANCE (Ω)

DUTY CYCLE = 0.5% MAX

3.0

1.8

0.6

0 60 160 180

-60

T_J, JUNCTION TEMPERATURE (^oC)

NORMALIZED ON RESISTANCE

I_D = 3.4A, V_GS = 10V 2.4

1.2

0 -40 -20 20 40 80 100 120 140 PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves

1.05

0.85

0 60 160 180

-60

T_J, JUNCTION TEMPERATURE (^oC)

NORMALIZED DRAIN TO SOURCE

I_D = 250µA 1.15

0.95

0.75 -40 -20 20 40 80 100120140

BREAKDOWN VOLTAGE

V_DS, DRAIN TO SOURCE VOLTAGE (V)

C, CAPACITANCE (pF)

500

400

300

200

100

0

V_GS = 0V, f = 1MHz C_ISS = C_GS + C_GD C_RSS = C_GD C_OSS≈ CDS + C_GD

C_ISS C_OSS

C_RSS

1 2 5 10 2 5 10²

I_D,DRAIN CURRENT (A)

2 4 6 8

0 10

2.5

2.0

1.5

0 1.0

gfs, TRANSCONDUCTANCE (S)

PULSE DURATION = 80µs

0.5

V_DS≥50V

T_J = 175^oC T_J = 25^oC DUTY CYCLE = 0.5% MAX

T_J = 175^oC

T_J = 25^oC ISD, SOURCE TO DRAIN CURRENT (A)

V_SD, SOURCE TO DRAIN VOLTAGE (V) 100

10

1

0.1

0 0.4 0.8 1.2 1.6 2.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

Q_g, GATE CHARGE (nC)

2 4 6 8

0 10

20

16

12

0 8

VGS, GATE TO SOURCE VOLTAGE (V)

V_DS = 80V

4

V_DS = 50V V_DS = 20V I_D = 3.4A

Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORM t_P

V_GS

0.01Ω L

I_AS

+ - V_DS

V_DD R_G

DUT VARY t_P TO OBTAIN

REQUIRED PEAK I_AS

0V

V_DD V_DS BV_DSS

t_P I_AS

t_AV 0

V_GS

R_L

R_G

DUT +

-

V_DD

t_ON t_d(ON)

t_r 90%

10%

V_DS

90%

10%

t_f t_d(OFF)

t_OFF

90%

50%

50%

10% PULSE WIDTH

V_GS 0

0

0.3µF 12V

BATTERY 50kΩ

V_DS S

DUT D

G

I_G(REF) 0

(ISOLATED V_DS

0.2µF

CURRENT REGULATOR

I_D CURRENT SAMPLING I_G CURRENT

SAMPLING

SUPPLY)

RESISTOR RESISTOR SAME TYPE AS DUT

Q_g(TOT) Q_gd Q_gs

V_DS

0

V_GS V_DD

I_G(REF)

0

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