25A and 28A, 80V and 100V, 0.077 and 0.100 Ohm,N-Channel Power MOSFETs

Features

• 25A and 28A, 80V and 100V

• r_DS(ON) = 0.077Ω and 0.100Ω

• Single Pulse Avalanche Energy Rated

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”

Description

These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching conver- tors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits.

Formerly developmental type TA17421.

Symbol

Packaging

JEDEC TO-220AB JEDEC TO-262AA

JEDEC TO-263AB

Ordering Information

PART NUMBER PACKAGE BRAND

IRF540 TO-220AB IRF540

IRF541 TO-220AB IRF541

IRF542 TO-220AB IRF542

IRF543 TO-220AB IRF543

RF1S540 TO-262AA RF1S540

RF1S540SM TO-263AB RF1S540SM

NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in the tape and reel, i.e., RF1S540SM9A.

G

D

S

GATE DRAIN (FLANGE)

SOURCE DRAIN

SOURCE DRAIN DRAIN GATE

(FLANGE)

DRAIN (FLANGE) GATE

SOURCE

November 1997

IRF543, RF1S540, RF1S540SM

25A and 28A, 80V and 100V, 0.077 and 0.100 Ohm,

N-Channel Power MOSFETs

Absolute Maximum Ratings

RF1S540SM IRF541 IRF542 IRF543 UNITS

Drain to Source Breakdown Voltage (Note 1). . . .V_DS 100 80 100 80 V

Drain to Gate Voltage (R_GS = 20kΩ)(Note 1) . . . V_DGR 100 80 100 80 V

Continuous Drain Current. . . I_D T_C= 100^oC . . . I_D

28 20

28 20

25 17

25 17

A A Pulsed Drain Current (Note 3) . . . I_DM 110 110 100 100 A Gate to Source Voltage . . . .V_GS ±20 ±20 ±20 ±20 V Maximum Power Dissipation . . . P_D 150 150 150 150 W Dissipation Derating Factor . . . 1 1 1 1 W/^oC Single Pulse Avalanche Energy Rating (Note 4) . . . E_AS 230 230 230 230 mJ Operating and Storage Temperature . . . T_J,T_STG -55 to 175 -55 to 175 -55 to 175 -55 to 175 ^oC Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s . . . T_L Package Body for 10s, See Techbrief 334 . . . T_pkg

300 260

300 260

300 260

300 260

oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. T_J = 25^oC to T_J = 150^oC.

Electrical Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV_DSS I_D = 250µA, V_GS = 0V (Figure 10) IRF540, IRF542,

RF1S540, RF1S540SM

100 - - V

IRF541, IRF543 80 - - V

Gate to Threshold Voltage V_GS(TH) V_GS = V_DS, I_D = 250µA 2 - 4 V

Zero Gate Voltage Drain Current I_DSS V_DS = Rated BV_DSS, V_GS = 0V - - 25 µA

V_DS = 0.8 x Rated BV_DSS, V_GS = 0V T_J = 150^oC

- - 250 µA

On-State Drain Current (Note 2) I_D(ON) V_DS > I_D(ON) x r_{DS(ON) MAX}, V_GS = 10V (Figure 7)

IRF540, IRF541, RF1S540, RF1S540SM

28 - - A

IRF542, IRF543 25 - - A

Gate to Source Leakage Current I_GSS V_GS =±20V - - ±100 nA

Drain to Source On Resistance (Note 2) r_DS(ON) I_D = 17A, V_GS = 10V (Figures 8, 9) IRF540, IRF541,

RF1S540, RF1S540SM

- 0.060 0.077 Ω

IRF542, IRF543 - 0.080 0.100 Ω

Input Capacitance C_ISS V_DS = 25V, V_GS = 0V, f = 1MHz (Figure 11)

- 1450 - pF

Output Capacitance C_OSS - 550 - pF

Reverse Transfer Capacitance C_RSS - 100 - pF

Internal Drain Inductance L_D Measured From the Contact Screw on Tab To Center of Die

Modified MOSFET Symbol Showing the Internal Devices Inductances

- 3.5 - nH

Measured From the Drain Lead, 6mm (0.25in) from Package to Center of Die

- 4.5 - nH

Internal Source Inductance L_S Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad

- 7.5 - nH

Thermal Resistance Junction to Case R_θJC - - 1 ^oC/W

Thermal Resistance Junction to Ambient

R_θJA Free Air Operation - - 80 ^oC/W

R_θJA RF1S540SM Mounted on FR-4 Board with Minimum Mounting Pad

- - 62 ^oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I_SD Modified MOSFET Sym- bol Showing the Integral Reverse

P-N Junction Diode

- - 28 A

Pulse Source to Drain Current (Note 3)

I_SDM - - 110 A

Source to Drain Diode Voltage (Note 2) V_SD T_J = 25^oC, I_SD = 27A, V_GS = 0V (Figure 13) - - 2.5 V Reverse Recovery Time t_rr T_J = 25^oC, I_SD = 28A, dI_SD/dt = 100A/µs 70 150 300 ns Reverse Recovery Charge Q_RR T_J = 25^oC, I_SD = 28A, dI_SD/dt = 100A/µs 0.44 1.0 1.9 µC NOTES:

2. Pulse test: pulse width≤300µs, duty cycle≤2%.

3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. V_DD= 25V, starting T_J= 25^oC, L = 440µH, R_G= 25Ω, peak I_AS = 28A. (Figures 15, 16).

Electrical Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

L_S L_D

G

D

S

G

D

S

Typical Performance Curves

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE T_C, CASE TEMPERATURE (^oC)

25 50 75 100 125 150 175

0

POWER DISSIPATION MULTIPLIER

0 0.2 0.4 0.6 0.8 1.0 1.2

12

6

0

25 50 75 100 125 150

24

ID, DRAIN CURRENT (A)

T_C, CASE TEMPERATURE (^oC) 30

175 18

IRF542, IRF543

IRF540, IRF541 RF1S540, RF1S540SM

t₁, RECTANGULAR PULSE DURATION (s)

10 ZθJC,TRANSIENT

10^-3 10^-2 10^-1 1

1

10^-5 10^-4

10

0.01 0.1

NOTES:

DUTY FACTOR: D = t₁/t₂ PEAK T_J = P_DM x Z_θJC + T_C

P_DM

t₁ t₂ 0.1

0.02 0.2 0.5

0.01 0.05

SINGLE PULSE THERMAL IMPEDANCE (oC/W)

100

IRF540, 1, RF1S540, SM

IRF542, 3 10µs

T_C = 25^oC

50

80µs PULSE TEST

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Typical Performance Curves

0 10

0 1.0 2.0 3.0 5.0

20 30

ID, DRAIN CURRENT (A)

V_DS, DRAIN TO SOURCE VOLTAGE (V) V_GS = 6V V_GS = 10V

40

4.0 V_GS = 4V

V_GS = 7V

V_GS = 5V 50

V_GS = 8V 80µs PULSE TEST

0 2 4 6 8 10

0.1 1 10

ID(ON), ON-STATE DRAIN CURRENT (A)

V_GS, GATE TO SOURCE VOLTAGE (V) 100

25^oC 175^oC

V_DS≥ 50V 80µs PULSE TEST

DUTY CYCLE = 0.5% MAX

0 0.4 0.6 0.8

25 50 75 100

rDS(ON), DRAIN TO SOURCE

I_D, DRAIN CURRENT (A)

125 1.0

0

0.2 V_GS = 10V

V_GS= 20V 80µs PULSE DURATION

ON RESISTANCE (Ω) NORMALIZED DRAIN TO SOURCE

3.0

1.8

1.2

0.6

0.0

-60 -40 -20 0 20 40 60

T_J, JUNCTION TEMPERATURE (^oC)

100 120 140 160 180 2.4

80 V_GS = 10V, I_D = 28A

ON RESISTANCE

1.25

1.05

0.95

0.85

0.75

-60 -40 -20 0 20 40 60

T_J, JUNCTION TEMPERATURE (^oC) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE

100 120 140 160 180 1.15

80

I_D = 250µA 3000

600

0

1 10 100

C, CAPACITANCE (pF)

1800

V_DS, DRAIN TO SOURCE VOLTAGE (V) 2400

1200

C_ISS

C_OSS

C_RSS

C_ISS = C_GS + C_GD C_RSS = C_GD C_OSS≈ CDS+ C_GD V_GS= 0V, f = 1MHz

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves

25^oC

I_D, DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S)

0

0 10 20 30 40

4 8 12 16 20

50 175^oC

V_DS≥50V, 80µs PULSE TEST

0 0.6 1.2 1.8 2.4 3.0

1 10 100

ISD, SOURCE TO DRAIN CURRENT (A)

V_SD, SOURCE TO DRAIN VOLTAGE (V) 1000

25^oC 175^oC

Q_g, TOTAL GATE CHARGE (nC) VGS, GATE TO SOURCE VOLTAGE (V)

0

0 12 24 36 48

4 8 12 16 20

60 I_D = 28A

V_DS = 50V

V_DS = 80V V_DS = 20V

Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS t_P

V_GS

0.01Ω L

I_AS

+ - V_DS

V_DD R_G

DUT VARY t_P TO OBTAIN

REQUIRED PEAK I_AS

0V

V_DD V_DS BV_DSS

t_P I_AS

t_AV 0

V_GS

R_L

R_G

DUT +

-

V_DD

t_ON t_d(ON)

t_r 90%

10%

V_DS

90%

10%

t_f t_d(OFF)

t_OFF

90%

50%

50%

10% PULSE WIDTH

V_GS 0

0

0.3µF 12V

BATTERY 50kΩ

V_DS S

DUT D

G

I_g(REF) 0

(ISOLATED V_DS

0.2µF

CURRENT REGULATOR

I_D CURRENT SAMPLING I_G CURRENT

SAMPLING

SUPPLY)

RESISTOR RESISTOR SAME TYPE AS DUT

Q_g(TOT) Q_gd Q_gs

V_DS 0

V_GS V_DD

I_G(REF)

0