Personal Computer Products Processors, Coprocessors, Video, and

Personal Computer Products

P rocessors, Coprocessors, Video, and Mass Storage

Advanced

Micro

Devices

Advanced Micro Devices

Personal Computer Products Data Book

© 1989 Advanced Micro Devices

Advanced Micro Devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics. The performance characteristics listed in this document are guaranteed by specific tests, correlated testing, guard banding,

design and other practices common to the industry.

For specific testing details, contact your local AMD sales representative.

The company assumes no responsibility for the use of any circuits described herein.

901 Thompson Place, P.O. Box 3453, Sunnyvale, California 94088-3000 (408)732-2400 TWX: 910-339-9280 TELEX: 34-6306

PAL is a registered trademark of Advanced Micro Devices, Inc.

Ada is a registered trademark of the Department of Defense.

ASM186 is a trademark of Microtech Research, Inc.

dBASE is a trademark of AShto'n-Tate.

DEC F, DEC 0, DEC G, and VAX are trademarks of the Digital Equipment Corporation.

Ethernet is a registered trademark of Xerox Corporation.

1-2-3 is a trademark of Lotus Corporation.

IBM PC/AT is a registered trademark of IBM Corporation.

MUL TIBUS is a trademark of Intel Corporation.

Norton 81 is a trademark of Peter Norton Computing, Inc.

NT**Multibus is a trademark of Intel Corporation.

OS/2 is a trademark of Microsoft and International Business Machines Corporation.

Paradox is a registered trademark of AT&T Technologies, Inc.

PC-XT is a trademark of International Business Machines Corporation.

TopView is a trademark of International Business Machines Corporation.

Z8000 is a trademark of Zilog, Inc.

Z8530H is a trademark of Zilog, Inc.

Personal Computer Products

INTRODUCTION

Advanced Micro Devices is dedicated to providing silicon systems solutions to the personal computer industry. These solutions include specific AMD integrated circuits as well as support tools from third party vendors designed to aid in the debug and evaluation of your PC deSigns.

The Personal Computer Products Data Book includes 80X86 processors and coprocessors. In addition, support peripherals such as color palettes, mass storage devices, and document processing products are included.

At AMD we are dedicated to keeping your deSigns competitive with leading edge solutions. Nearly 60 percent of AMD's personal computer products are CMOS high-performance ICs. CMOS is where AMD has the opportunity to apply our process technology expertise and our systems expertise most readily.

~

Vice President

Personal Computer Products Division

ill

Personal Computer Products

PREFACE

Advanced Micro Devices provides a broad product portfolio for personal computer applications. Included in this data book are microprocessors, video products, mass storage devices, and related peripherals available to optimize the cost performance of your PC design. AMD also manufactures other PC-related products such as EPROM and PAL devices listed in data books available from your local AMD sales office.

This data book is divided by product type into six chapters, with blue pages highlighting AMD CMOS products. Chapter 1 lists the 80XX and 80286 processors. In addition to the high-performance NMOS 16-MHz 80286, AMD now offers a CMOS version, the 80C286, which runs at clock speeds from 12.5 to 25 MHz. The 80C286 microprocessor is a cost-effective, high-performance solution for desktop and laptop PC markets. Also in this chapter is AMD's CMOS 80C287, which is a plug-in compatible with Intel's NMOS 80287 and is offered at speeds up to 16 MHz. It also is capable of automatic sleep mode for laptop PC applications.

Chapter 2 contains support peripherals for computational systems-the high-performance CMOS Am29C325 Double-Precision Floating Point Processor, the popular Z8530H Serial Communications Controller used in AppleTalk network connections, and the CMOS Z85C30, which is capable of a fast Mb/s data rate.

Chapter 3 focuses on graphics products for personal computers and high-performance workstations.

AMD offers a full line of industry standard NMOS and CMOS VGA color palettes for IBM- and Apple- compatible PCs, including products with low-power sleep mode, permitting longer battery life performance for laptop PC applications. For workstations, AMD offers a total systems solution Am95C60 QPDM for the display of bit-mapped and alphanumeric graphics.

Chapter 4 presents both CMOS and NMOS products for mass storage applications. The Am95C94 Advanced Burst Error Processor, Am95C95 Magnetic Disk Controller, and Am95C96 Optical Disk Con- troller combine to create high density and high-performance disk-embedded control designs with error detection and correction on the fly. In addition, Am53C80N and Am33C93A SCSI chips provide system interface for your mass storage needs.

Chapter 5 lists AMD's document proceSSing products. The Am95C71 VCEP can compress an 8¹/2 x 11- inch page format to 4 percent of its original size for FAXing and then expand it back to its original size at 60 Mb/s. The high speeds of the VCEP make this device ideal for those systems requiring real time processing of stored data while reducing the amount of data stored.

The final chapter of general information includes packaging, thermal characteristics, and support literature available on all AMD PC products.

Iv

Personal Computer Products

PERSONAL COMPUTER PRODUCTS DATA BOOK

System Integration Guide ... vii Numeric Listing ... viii

Chapter 1 Microprocessors

8086 Data Sheet ... ~ ... 1-3 8088 Data Sheet ... 1-34 80286 Data Sheet ... 1-66 80C286 Data Sheet ... 1-128 80L286 Data Sheet ... 1-191 AMD 80C287 Data Sheet ... 1-204 AMD 80EC287 Data Sheet ... 1-216 Am9517N8237A Data Sheet ... 1-227 80286 Memory Interface Applications Note ... 1-248 80C287 Performance Benchmarks Applications Note ... 1-258

Chapter 2 System Support Peripherals

Am29C325 Data Sheet ... , ... 2-3 Am29C327 Data Sheet ... ;2-59 Am9513A Data Sheef. ... 2-116 Am9516A Data Sheet ... 2-155 Am9519A Data Sheet ... 2-212 Am95C85 Data Sheet ... 2-226 Z8530H Data Sheet ." ... 2-250 Z85C30 Data Sheet ... 2-285 Z85C30 Serial Communications Controller Applications Note ... 2-339

Chapter 3 Graphics Products

AmB052 Data Sheet ... 3-3 AmB152NAm8152B Data Sheet ... 3-40 AmB172 Data Sheet ... 3-55 AmB177 Data Sheet ... 3-68 AmB151A Data Sheet ... 3-78 AmB1C176 Data Sheet_ ... 3-95 Am81 C451 1458 Data Sheet ... 3-112 Am81C453 Data Sheet ... : ... 3-134 Am81C471/478 Data Sheet ... 3-137 Am81 EC176 Data Sheet ... 3-151 Am81EC471/478 ... 3-155 Arn95C60 Data Sheet ... 3-159

v

Personal Computer Products

TABLE OF CONTENTS (continued)

Chapter 4 Mass Storage

Arn5380/Am53C80N Data Sheet ... 4-3 Am33C93A Data Sheet ... 4-31 Am95C94 Data Sheet ... 4-78 Am95C95 Data Sheet ... 4-83 Am95C96 Data Sheet ... 4-88 Am9580NAm9590 Data Sheet ... 4-93

Chapter 5 Document Processing

Am7971 A Data Sheet ... 5-3 Am95C71 Data Sheet ... 5-57 Am95C75 Data Sheet ... 5-83 Am95C76 Data Sheet ... 5-115

Chapter 6 General Information

Thermal Characteristics ... 6-3 Physical Dimensions ... 6-5 Support Literature ... ; ... 6-28

vi

Personal Computer Products

SYSTEM INTEGRATION GUIDE

Processor Video Mass Storage Other Related

Personal Computer Segment Products Products Products Products·

Cost Sensitive PCs 8088/8086 Am9580A Am9517A

80286-8, Am9590

-10,-12

Price/Performance PCs ' 80286-16 Am81C471/478 Am95C94 AMD 80C287

80C286-16, Am81C176 Am95C95 Am53C80N

-20,-25 Am81C453 Am95C96 Am33C93

See note 1

Laptop PCs 80C286-12, Am81EC176 Am95C94 AMD 80EC287

-16,-20 Am81 EC478

Am81EC471

Workstations Am29000, Am81C453 Am95C94 Am9513

other RISC Am81C458 Am95C95 Am9516

680XX, etc. Am95C60 Am95C96

Peripheral Cards or Devices

FAX cards Am7971A

Graphics Am95C60 Am81C176

Am29000

Networking 80186/88 See note 2

Disk Control 80186/88 Am95C94 Am33C93

80C521 Am95C95 Am53C80N

Am95C96

Memory management Am95C85

Laser printers Am95C75

Am95C76 Am29000

* AMD makes a complete line of PAL® and EPROM devices necessary for PC design. Further information can be found in other data books available from your AMD sales office.

Notes: 1. AMD's PC products are completely compatible with Integrated Peripherals such as those available from Chips & Technologies, Headland (G-2), VLSI Technologies, Faraday, VIA, etc. An 80286 cache controller for 20- and 25-MHz-based cache designs is available from Austek Microsystems.

2. AMD manufactures a complete line of Networking and Telecommunications Products. Further information can be found in other data books available from your AMD sales office.

vii

Personal Computer Products

Device Am29C325 Am29C327 Am33C93A Am5380/Am53C80N Am7971A 80286 Am8052 8086 8088 80C286 AMD80C287 AMD80EC287 80L286 Am8151A Am8152A1 Am8152B Am8172 Am8177 Am81C176 Am81C451/458 Am81C453 Am81C471/478 Am81EC176 Am81 EC471 1478 9513A 9516A 9517A18237A 9519A Am9580Al Am9590 Am95C60 Am95C71 Am95C75 Am95C76 Am95C85 Am95C94 Am95C95 Am95C96

vIII

Z8530H Z85C30

NUMERIC LISTING

Description Page Number

Single-Precision Floating Point Processor Double-Precision Floating Point Processor Second Generation SCSI Controller SCSI Bus Controller

Compression Expansion Processor 16-Bit High-Performance Microprocessor CRT Controller

16-Bit Microprocessor 8-Bit Microprocessor

CMOS Version of 80286 16-Bit Microprocessor Math Coprocessor

Enhanced Math Coprocessor

Reduced Power Version of 8028616-Bit Microprocessor Graphics Color Palette, Single 8-Bit DAC, 256 x 8 RAM Video System Controller

Video Data Assembly FIFO Video Data Serializer

CMOS Color Palette, Triple 6-Bit DAC, 256 x 18 RAM

CMOS Color Palette, Triple 4-Bit (8-Bit) DAC, 256 x 12 (24) RAM CMOS Color Palette, Triple 8-Bit DAC, 256 x 24 RAM

CMOS Color Palette, Triple 6-Bit (8-Bit) DAC, 256 x 18 (24) RAM CMOS Color Palette, Triple 6-Bit DAC, 256 x 18 RAM

Enhanced Am81 C471 1478 CMOS Color Palette System Timing Controller

Universal DMA Controller Multimode DMA Controller Universal Interrupt Controller Hard Disk Controller Quad Pixel Dataflow Manager

Video Compression Expansion Processor Raster Printer Controller

Orthogonal Rotation Processor Content Addressable Data Manager Advanced Burst Error Processor Magnetic Disk Controller Optical Disk Controller

Serial Communications Controller CMOS Version of Z8530H

2-3 2-59 4-31 4-3 5-3 1-66 3-3 1-3 1-34 1-128 1-204 1-216 1-191 3-78 3-40 3-55 3-68 3-95 3-112 3-134 3-137 3-151 3-155 2-116 2-155 1-227 2-212 4-93 3-159 5-57 5-83 5-115 2-226 4-78 4-83 4-88 2-250 2-285

Advanced Micro Devices

CHAPTER 1

Personal Computer Products

80.86 Data Sheet ... 1-3 80.88 Data Sheet '" ... 1-34 80.286 Data Sheet ... 1-66 8o.C286 Data Sheet ... 1-128 8o.L286 Data Sheet ... · ... 1-191 AMD 8o.C287 Data Sheet ... 1-20.4 AMD 8o.EC287 Data Sheet ... 1-216 Am9517N8237A Data Sheet ... 1-227 80.286 Memory Interface Applications Note ... 1-248 8o.C287 Performance Benchmarks Applications Note ... ;.1-258

8086

16-Bit. Microprocessor iAPX86 Family

FINAL

DISTINCTIVE CHARACTERISTICS

• Directly addresses up to 1 Mbyte of memory

• 24 operand addressing modes

• Efficient implementation of high level languages

• Instruction set compatible with 8080 software

• Bit, byte, word, and block operations

• 8 and 16·bit signed and unsigned arithmetic in binary or decimal

• MUL TIBUS® system interface

• Three speed options - 5MHz for 8086 - 8MHz for 8086·2 - 10MHz for 8086·1

GENERAL DESCRIPTION The 8086 is a general purpose 16·bit microprocessor CPU.

Its architecture is built around thirteen 16·bit registers and nine 1·bit flags. The CPU operates on 16·bit address spaces and can directly address up to 1 megabyte using offset addresses within four distinct memory segments, designated as code, data, stack and extra code. The 8086 implements a powerful instruction set with 24 operand addressing modes. This instruction set is compatible with that of the 8080 and 8085. In addition, the 8086 is particularly effective in executing high level languages.

The 8086 can operate in minimum and maximum modes.

Maximum mode offloads certain bus control functions to a peripheral device and allows the CPU to operate efficiently in a multi· processor system. The CPU and its high perfor·

mance peripherals are MUL TIBUS compatible. The 8086 is implemented in N·channel, depletion load, silicon gate technology and is contained in a 40·pin CERDIP package, Molded DIP package, or Plastic Leaded Chip Carrier.

BLOCK DIAGRAM

EXECUTION lINT

REGISTER~

DATA.

POINTER. AND INDEX REGS

(I WORDS)

BUS INTEAfACl! lINT RELOCAlIOH REGISTER~

DT/A. D£N.AU!

Trn' _ - l r - - - -... ~----""'L.

__

!NT NMI

HOlD

H~A----L_~-_r--~----r---~~

Publication IF Rev. Amendment 01966 0 - - ' - 0 - -

Issue Date: Au ust 1989 8086

80003740

1-3

~

I

1-4

DIP

Vee

AD15 A1a!S3

A17/54 A1a/SS A1e/Se BHE/57 IIN/Mi(

AD

RQ/GTo Ra/GT1

LoCK

52

S;

SO

QSo QS1

ffiT

READY RESET

CONNECTION DIAGRAMS Top View

ADi0 ADg ADa AD7 AD6

(HOLD) AD5

(HLDA)

AD4 (Wii)

AD3 (li/iO)

AD2 (DT/J!i)

ADi

(DEN) ADo

(ALE) (INTA)

CDOO5511 Note: Pin 1 is marked for orientation.

8086

PLCC

NC Aig_/S6 SHE/S 7 MN/MX R'O

Im/GT 0 (HOLD)

Im/aT 1 (HLDA) (QCK (WR)

S2

51

SO (DEN)

CD010701

ORDERING INFORMATION Commercial Products

AMO commercial products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range

.1

b. Package Type c. DevIce Number d. Speed OptIon e. OptIonal ProcessIng

8086 .=2.. J!.

L='

Blank - Standard Processing B -Bum·in

d. SPEED OPTION Blank-S MHz

-2- 8 MHz -1 -10 MHz

~---c. DEVICE NUMBER/DESCRIPTION 8086

16-Bit Microprocessor

' - - - b. PACKAGE TYPE

P - 40-Pin Plastic DIP (PO 040)

o -40·Pin Ceramic DIP (CD 040)

N - 44·Pin Plastic Leaded Chip Carrier (PL 044)

~---a. TEMPERATURE RANGE-

Valid CombInatIons 8086 P, 0, N 8086·2

8086-1

0,10 8086-2B

0 8086-1

10 8086B

8086

Blank - Commercial (0 to + 70·C) I - Industrial (-40 to + 8S°C)

Valid CombInatIons

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMO sales office to confirm availability of specific valid combinations, to check on newly released valid combinations, and to obtain additional data on AMO's standard military grade products.

1-5

..

1-6

ORDERING INFORMATION Military Products

AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number

8086 8086-2

b. Speed Option (if applicable) c. Device Class

d. Package Type e. Lead Finish

Q .A.

l:=

A - Hot Solder DIP

d. PACKAGE TYPE

a -40·Pin Ceramic DIP (CD 040)

~---c. DEVICE CLASS /B - Class B

' - - - b . SPEED OPTION Blank- 5 MHz

-2=8 MHz

- a. DEVICE NUMBER/DESCRIPTION 8086

l6·Bit Microprocessor IAPX Family

Valid Combinations /BOA

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check for newly released valid

combinations. '

8086

Group A Tests Group A tests consist of Subgroups

1, 2, 3, 7, 8, 9, 10, 11.

PIN DESCRIPTION

The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The "Local Bus" in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional bus buffers).

Pin No.· Name I/O Description

39,2-16 AD1S-ADO 110 Address Data Bus. These lines constitute the time multiplexed memory/IO address (Tl) and data (T2, T3, Tw, T4) bus. Ao is analogous to BHi: for the lower byte of the data bus. pins 0]-00. It is lOW during T 1 when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. Eight-bit oriented devices tied to the lower half would normally use Ao to condition chip select functions. (See BHi:.) These lines are active HIGH and float to three-state OFF during interrupt acknowledge and local bus "hold acknowledge."

35-3B A19/S6, 0 Address/Status. During T 1 these are the four most significant address lines for memory operations. During I/O Ale/5 5, operations these lines are lOW. During memory and I/O operations, status information is available on these lines A17/S4. during T 2. T 3. Tw. and T 4. The status of the interrupt enable FLAG bit (55) is updated at the beginning of each ClK A16/S3 cycle. A17/S4 and A16/S3 are encoded as shown.

This information indicates which relocation register is presently being used for data accessing.

These lines float to three-state OFF during local bus "hold acknowledge."

A17/S4 A16-Sa Characteristics

o (lOW) 0 Alternate Data

0 1 Stack

1 (HIGH) 0 Code or None

1 1 Data

56 is 0 (lOW)

34 tffiE/S7 0 Bus High Enable/Status. During Tl the bus high enable signal (BHE) should be used to enable data onto the most significant half of the data bus, pins. D15-De. Eight-bit oriented devices tied to the upper half of the bus would normally use SHE to condition chip select functions. BH!: is lOW during T 1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The 57 status information is available during T 2. T 3. and T 4. The signal is active lOW and floats to

three-state OFF in "hold." It is lOW during Tl for the .first interrupt acknowledge cycle.

BHE Ao Characteristics

0 0 Whole word

0 1 Upper byte from/

to odd address

1 0 lower byte from/

to even address

1 1 None

32 AD 0 Read. Read strobe indicates that the processor is performing a memory of I/O read cycle, depen~ on the state of the 52 pin. This signal is used to read devices which reside on the BOB6 local bus. 0 is active lOW during T2, T3. and TW of any read cycle and is guaranteed to remain HIGH in T2 until the BOB6 local bus has floated.

This signal floats to three-state OFF in "hold acknowledge."

22 READY I READY. Is the acknowledgment from the addressed memory or 110 device that it will complete the data transfer. The READY signal from memory/IO is synchronized by the B2B4A Clock Generator to fonm READY. This signal is active HIGH. The BOB6 READY input is not synchronized. Correct operation is not guaranteed if the set-up and hold times are not met.

1B INTR I Interrupt Request. Is a level triggered input which is sampled during the last clock cycle of each instruc- tion to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

23 'fESf I fEST. Input is examined by the "Wait" instruction. If the TEST input is lOW, execution continues; other- wise. the processor waits in an "Idle" state. This input is synchronized internally during each clock cycle on the leading edge of ClK.

17 NMI I Non-Maskable Interrupt. An edge-triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from a lOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.

21 RESET I Reset. Causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. It restarts execution, as described in the Instruction Set description, when RESET returns lOW. RESET is internally synchronized.

19 elK I Clock. Provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing.

40 Vee Vee. The + 5 V power supply pin.

1,20 GND Ground. The ground pin.

33 MN/MX I Minimum/Maximum. Indicates what mode the processor is to operate in. The two modes are discussed in the following sections.

·Pin numbers correspond to DIPs only.

8086 1-7

PIN DESCRIPTION (continued) .

Pin No.* Name I/O Description

28-26 S2, Sl, So 0 Status. Active during T 4, T 1, and T 2 and is returned to the passive state (1, 1, 1) during T 3 or during T W when READY is HIGH. This status is used by the 8288 Bus Controller to generate all memory and I/O access control signals. Any change by 52, 51, or So during T 4 is used to indicate the beginning of a bus cycle, and the return to the passive state in T3 or Tw is used to indicate the end of a bus cycle.

These signals float to three-state OFF in "hold acknowledge." These status lines are encoded as shown.

82 S1 So Characteristics

o (lOW) 0 0 Interrupt Acknowledge

0 0 1 Read I/O Port

0 1 0 Write I/O Port

0 1 1 Halt

1 (HIGH) 0 0 Code Access

1 0 1 Read Memory

1 1 0 Write Memory

1 1 1 Passive

31,30 Jm/rrTo, I/O Request/Grant. Pins are used by other local bus masters to force the processor to release the local bus Jm/crT1 at the end of thmrocessor's current bus cycle. Each pin is bidirectional with 'R"1:i/G'i'0 having higher

priority than ROI 1. m:i/CTI has an internal pull-up resistor so it may be left unconnected. The request/

grant sequence is as follows:

1. A pulse of 1 ClK wide from another local bus master indicates a local bus request ("hold") to the 8086 (pulse 1).

2. During a T 4 or T 1 clock cycle, a pulse 1 ClK wide from the 8086 to the requesting master (pulse 2), indicates that the 8086 has allowed the local bus to float and that it will enter the "hold acknowledge"

state at the next ClK. The CPU's bus interface unit is disconnected logically from the local bus during

"hold acknowledge."

3. A pulse 1 ClK wide from the requesting master indicates to the 8086 (pulse 3) that the "hold"

request is about to end and that the 8086 can reclaim the local bus at the next ClK.

Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one dead ClK cycle after each bus exchange. Pulses are active lOW.

If the request is made while the CPU is performing a memory cycle, it will release the local bus during T 4 of the cycle when all the following conditions are met:

1. Request occurs on or before T 2.

2. Current cycle is not the low byte of a word (on an odd address).

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing.

If the local bus is idle when the request is made, two possible events will follow:

1. local bus will be released during the next clock.

2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.

29 rncK 0 t:O"CK. Output indicates that other system bus masters are not to gain control of the system bus while [QCK is active lOW. The [QCK signal is activated by the "lOCK" prefix instruction and remains active until the completion of the next instruction. This signal is active lOW, and floats to three-state OFF in

"hold acknowledge."

24,25 QS1, QSo 0 Queue Status. The queue status is valid during the ClK cycle after which the queue operation is per- formed.

QSl and QSo provide status to allow external tracking of the internal 8086 instruction queue.

28 M/TO 0 Status line. logically equivalent to 52 in the maximum mode. It is used to distinguish a memory access from an I/O access. MilO becomes valid in the T 4 preceding a bus cycle and remains valid until the final T 4 of the cycle (M - HIGH, 10 -lOW). M/TO floats to three-state OFF in local bus "hold acknowledge."

29 ·WR 0 Write. Indicates that the processor is performing a write memory or write I/O cycle, depending on the state of MilO signal. WR is active for T 2, T 3, and T W of any write cycle. It is active lOW and floats to three-state OFF in local bus "hold acknowledge."

24 TFJTA 0 TNfA. Is used as a read strobe for interrupt acknowledge cycles. It is active lOW during T2, T3, and Tw of each interrupt acknowlegde cycle.

25 ALE 0 Address Latch Enable. Provided by the processor to latch the address into 8282/8283 address latch. It is a HIGH pulse active during T 1 of any bus cycle. Note that ALE is never floated.

27 DT/R 0 Data Transmit/Receive. Needed in minimum system that desires to use an 8286/8287 data bus transceiv- er. It is used to control the direction of data flow through the transceiver. logically DT IA is equivalent to Sl in the maximum mode, and its timing is the same as for M/R). (T - HIGH, R - lOW.) This signal floats to three-state OFF in local bus "hold acknowledge."

26 rn:FJ 0 Data Enable. Provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. l)Efij is active lOW during each memory and I/O access and for INTA cycles. For a read or TFJTA cycle, it is active from the middle of T 2 until the middle of T 4, while for a write cycle, it is active from the beginning of T2 until the middle of T4. om floats to three-state OFF in local bus "hold acknowledg

·Pin numbers correspond to DIPs only.

PIN DESCRIPTION (continued)

Pin No.· Name I/O Description

31,30 HOLD,

HLDA

1/0 HOLD. Indicates that another master is requesting a local bus "hold." To be acknowledged, HOLD must be active HIGH. The processor receiving the "hold" request will issue HLDA (HIGH) as an acknowledge- ment in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA, the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor will LOWer HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines.

The same rules as for RC:)/(IT apply, regarding when the local bus will be released.

HOLD is not asynchroneous input. External synchronization should be provided if the system cannot other- wise guarantee the set-up time.

·Pin numbers correspond to DIPs only.

DETAILED DESCRIPTION

The 8086 CPU is internally organized into two processing units. These two units are the Bus Interface Unit (BIU) and the Execution Unit (EU). A block diagram of this organization is shown on page 1.

The BIU performs instruction fetch and queuing, operand fetch and store, address relocation, and basic bus control. The EU receives operands and instructions from the BIU and process- es them on a 16-bit ALU. The EU accesses memory and peripheral devices through requests to the BIU. The BIU generates physical addresses in memory using the 4 segment registers and offset values.

The BIU and EU usually operate asynchronously. This permits the 8086 to overlap execution fetch and execution. Up to 6 instruction bytes can be queued. The instruction queue acts as a FIFO buffer for instructions, from which the EU extracts instruction bytes as required.

Memory Organization

The 8086 addresses up to 1 megabyte of memory. The address space is organized as a linear array, from 00000 to FFFFF in hexadecimal. Memory is subdivided into segments of 64K bytes each. There are 4 segments: code, stack, data, and extra (usually employed as an extra data segment). Each

~FFFFFH

t-\--

XXXXOH

L;; ¹

+jSET

SEGMENT

-I

I ""7~ I ~)---,---t----i

: ^{} - -}

segment thus contains information of a similar type. Selection of a destination segment is automatically performed using the rules in the table below. This segmentation makes memory more easily relocatable and supports a more structured programming style.

Physical addresses in memory are generated by selecting the appropriate segment, obtaining the segment "base" address from the segment register, shifting the base address 4 digits to the left, and then adding this base to the "offset" address. For programming code, the offset address is obtained from the instruction pointer. For operands, the offset address is calcu- lated in several ways, depending upon information contained in the addressing mode. Memory organization and address generation are shown in Figure 1 a.

Certain memory locations are reserved for specific CPU operations. These are shown in Figure 1 b. Addresses FFFFOH through FFFFFH are reserved for operations which include a jump to the initial program loading routine. After RESET, the CPU will always begin execution at location FFFFOH, where the jump must be located.

Addresses OOOOOH through 003FFH are reserved for interrupt operations. The service routine of each of the 256 possible interrupt types is signaled by a 4-byte pOinter. The pointer elements must be stored in reserved memory addresses before the interrupts are invoked.

1

r~

I'ROGIWI~

FfFFOH

3fFH INTERRUPT POINTER

FOR TYPE 255 3fCH

· ·

·

INTERRUPT POINTER FOR TYPE 1 _4H INTERRUPT POINTER 3H

FOR TYPE 0 OH DF003320

DF003310

Figure 1a. Memory Organization Figure 1 b. Reserved Memory Locations

8086 1-9

..

Memory Reference Need Instructions

Stack Local Data External (Global) Data

Segment Register Used CODE (CS) STACK (55) DATA (OS) EXTRA (ES)

Segment Selection Rule Automatic for all prefetching of instructions.

All stack pushes and pops, and all memory references relative to BP base register except data references.

Data references which are relative to the stack, the destination of a string operation, or explicitly overriden.

Destination of string operations, when they are explicitly selected using a segment override.

Minimum and Maximum Modes freeing up the CPU. The CPU communicates status informa·

tion to the 8288 through pins So, S1, and S2. In maximum mode, the 8086 can operate in a multiprocessor system, using the LOCK signal within a Multibus format.

The 8086 has two system configurations, minimum and maximum mode. The CPU has a strap pin, MN/MX, which defines the system configuration. The status of this strap pin defines the function of pin numbers 24 through 31.

When MN/MX is strapped to VCC, the 8086 operates in minimum mode. The CPU sends bus control signals itself through pins 24 through 31. This is shown in the Connection Diagrams (in parentheses). Examples of minimum and maxi·

mum mode systems are shown in Figure 2.

When MN/MX is strapped to GND, the 8086 operates in maximum mode. The operations of pins 24 through 31 are redefined. In maximum mode, several bus timing and control functions are "off·loaded" to the 8288 bus controller, thus

1284A CLOCK MN/MX I - -vee

GENERATOR t-- ^{elK M/iO}

1---

~

RES

t-- RUET RDI---1_---~----1_-

I

GND

r--l--,

I I

I WAIT I

I STATE I

I GENERAtOR I

I I

L. _____ .1

WR

DT/A DEN ION CPU

---,

----I

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I I I I

I I I

A~r_---~I~T-I~sn I

I I I I I I I I I

GND -+--l+---l Of 8282

I _I

ADo-AD1s /Al...-_ _ _ I....-..!.I_.I'," lATCH

ADDR/DATA 2 DR 3

L

A!t·AII 1'\.... I ...---..-....-.... I"'----r-~_-_._..,...I.J

BHE~

!

I I I ^t-

I I I

I I

r---.,

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r---'

I 1_ II I

"---~ DE 828& I I I

I TRANSCEIVER I I I

L -_ _ _ _ ... ;! (2) I i -I~..I-..L.---'--I.--LD~AI::-TA:---=--...JL----L...l...,~

~---~ I~~~~~~~r-_T~~~~-~~~T_ ... ~O

l~~~~JJBHE JiB .Y1lri ^~

FOR INCREASED

DATA BUS DRIVE ^CS~ WEOO 2142 RAM (4)

(2) (2)

lK.8 I lK. 1

Figure 2a. Minimum Mode 8086 Typical Configuration

CE DE CS RD WR

2715-2 PROM (2) 2K.I -.l 2K.I

MCS-eo PERIPHERAL

AF002850

'" ~~ Li.~ax----~--~~~ ^___

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~ REi I-- READY Ii ij AUWC r---NC

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r---++---+---... -

r

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r - -DT/A AiOWC r---He

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L . . . - - -

...c==:;-

<---T

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~----~~'I~~~ ~~A-L~----L~~~~~~~ ^... --~~~---~~rl

AF002860

Figure 2b. Maximum Mode 8086 Typical Configuration

Bus Operation

The 8086 has a combined address and data bus, commonly referred to as "a time multiplexed bus." This technique provides the most efficient use of pins on the processor while permitting the use of a standard 40-lead package. This bus can be used throughout the system with address latching provided on memory and 110 modules. The bus can also be demultiplexed at the processor with a single set of address latches if a standard non-multiplexed bus is desired for the system.

Each bus cycle consists of at least four elK cycles. These are referred to as T 1, T 2, T 3 and T 4 (see Figure 5). The address is sent from the processor during T 1. Data transfer occurs on the bus during T 3 and T 4. T 2 is used for changing the direction of the bus during read operations. In the event that a "NOT READY" indication is given by the addressed device, "Wait"

states (Tw) are inserted between T3 and T4. Each inserted

"Wait" state is of the same duration as a elK cycle. "Idle"

states (T 1) or inactive elK cycles can occur between 8086 bus cycles. The processor uses these cycles for internal housekeeping.

During T 1 of any bus cycle, the ALE (Address latch Enable) Signal is emitted (by either the processor or the 8288 bus controller, depending on the MN/MX strap). At the trailing edge of this pulse, a valid address and certain status informa- tion for the cycle may be latched.

Status bits

So,

8086

52 51 50 Characteristics

O(lOW} 0 0 Interrupt Acknowledge

0 0 1 Read I/O

0 1 0 Write I/O

0 1 1 Halt

1(HIGH) 0 0 Instruction Fetch 1 0 1 Read Data from Memory 1 1 0 Write Data to Memory 1 1 1 Passive (no bus cycle)

Status bits S3 through S7 are multiplexed with high-order address bits and the SHE Signal, and are therefore valid during T 2 through T 4. S3 and S4 indicate which segment register (see Instruction Set description) was used for this bus cycle in forming the address, according to the following table:

54 53 Characteristics

O(lOW} 0 Alternate Data (extra segment)

0 1 Stack

1(HIGH) 0 Code or None

1 1 Data

S5 is a reflection of the PSW interrupt enable bit. S6 = 0 and S7 is a spare status bit.

1/0 Addressing

8086 110 operations can address up to a maximum of 64K I/O byte registers or 32K 110 word registers. The 110 address appears in the same format as the memory address on bus lines A15-AQ. The address lines A19-A16 are zero in 110 operations. 110 instructions which use register OX as a pointer have full address capability. Direct I/O instructions directly address one or two of the 256 110 byte locations in page 0 of the I/O address space. 110 ports are addressed in the same manner as memory locations.

1·11

..

. -_ _ _ _ _ (4 + "wAIT)" T C V , - - - + - _ -_ _ _ (4 + "wAIT)· T C Y ' - - - - ' - - - I

TZ T3

I

I

CUt

GOES INACT'IV£ IN ntE STATE

~ ~'---_~//#h~@#U ~T' _\'----

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.-A,. , - - - " " " \ iiHe,

10,.-10,.

ADOR/

STATUS

ADDR/DATA

AD.INTA

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WAIT

---8 __ ^{D _}

_OUT_(_D_'S_-00_)_....,,)--{)C

READY

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WF006650

Figure 3. Basic System Timing

EXTERNAL INTERFACE

Processor Reset and Initialization

Processor initialization or start up is accomplished with activa- tion (HIGH) of the RESET pin. The 8086 RESET is required to be HIGH for greater than 4 ClK cycles. The 8086 will terminate operations on the high-going edge of RESET and will remain dormant as long as RESET is HIGH. The low-going transition of RESET triggers an internal reset sequence for approximately 10 ClK cycles. After this interval the 8086 operates normally beginning with the instruction in absolute location FFFFOH (see Figure 1 b). The details of this operation are explained in the Instruction Set description of the MCS-86 Family User's Manual. The RESET input is internally synchro- nized to the processor clock. At initialization the HIGH-to-lOW transition of RESET must occur no sooner than 50llS after power-up, to allow complete initialization of the 8086.

NMI may not be asserted prior to the 2nd ClK cycle following the end of RESET.

Interrupt Operations

Interrupt operations fall into two classes: software or hardware initiated. The software initiated interrupts and software as- pects of hardware interrupts are described in the Instruction Set description. Hardware interrupts are either non-maskable or maskable.

Interrupts transfer control to a new program location. A 256- element table containing address pointers to the interrupt service program locations resides in absolute locations 0 through 3FFH (see Figure 1b), which are reserved for this purpose. Each element in the table is 4 bytes in size and corresponds to an inte.rrupt "type." An interrupting device - supplies an 8-bit type n\lmber during the interrupt acknowl- edge sequence, which is used to "vector" through the appropriate element to the new interrupt service program location.

Non-Maskable Interrupt (NMI)

The processor provides a single non-maskable interrupt pin (NMI) which has higher priority than the maskable interrupt request pin (INTR). A typical use would be to activate a power 8086

failure routine. The NMI is edge-triggered on a lOW-to-HIGH transition. The activation of this pin causes a type 2 interrupt.

(See Instruction Set description.)

NMI is required to have a duration in the HIGH state of greater than two ClK cycles, but is not required to be synchronized to the clock. Any high-going transition of NMI is latched on-chip and will be serviced at the end of the current instruction or between whole moves of a block-type instruction. Worst case response to NMI would be to multiply, divide, and variable shift instructions. There is no specification on the occurrence of the low-going edge; it may occur before, during, or after the servicing of NMI. Another high-going edge triggers another response if it occurs after the start of the NMI procedure. The signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid triggering extraneous responses.

Maskable Interrupt (INTR)

The 86/10 provides a single interrupt request input (INTR) which can be masked internally by software with the resetting of the interrupt enable FLAG status bit. The interrupt request signal is level-triggered. It is internally synchronized during each clock cycle on the high-going edge of ClK. To be responded to, INTR must be present (HIGH) during the clock period preceding the end of the current instruction or the end of a whole move for a block-type instruction. During the interrupt response sequence, further interrupts are disabled.

The enable bit is reset as part of the response to any interrupt (INTR, NMI, software interrupt, or single-step), although the FLAGS register, which is automatically pushed onto the stack, reflects the state of the processor prior to the Interrupt. Until the old FLAGS register is restored, the enable bit will be zero unless specifically set by an instruction.

During the response sequence (Figure 4), the processor executes two successive (back-to-back) interrupt acknowl- edge cycles. The 8086 emits the lOCK signal from T 2 of the first bus cycle until T2 of the second. A local bus "hold"

request will not be honored until the end of the second bus cycle. In the second bus cycle, a byte is fetched from the external interupt system (e.g., 8259A PIC) which identifies the source (type) of the interrupt. This byte is multiplied by four and used as a pointer into the interrupt vector lookup table. An INTR signal left HIGH will be continually responded to within the limitations of the enable bit and sample period. The INTERRUPT RETURN instruction includes a FLAGS pop, which returns the ,status of the original interrupt. enable bit when it restores the FLAGS.

HALT

When a software "HALT" instruction is executed, the proces- sor indicates that it is entering the " HALT" state in one of two ways depending upon which mode is strapped. In minimum mode, the processor issues one ALE with no qualfying bus control signals. In Maximum Mode, the processor issues appropiate HALT status on S2S1 SO, and the 8288 bus controller issues one ALE. The 8086 will not leave the

"HALT" state when a local bus "hold" is entered while in

"HALT." In this case, the processor reissues the HALT indicator. An interrupt request or RESET will force the 8086 out of the "HALT" state.

Read/Modify/Write (Semaphore) Operation Via Lock

The lOCK status information is provided by the processor when directly consecutive bus cycles are required during the execution of an instruction. This provides the processor with the capability of performing read/modify/write operations on memory (via the Exchange Register With Memory Instruction, for example) without the possibility of another system bus

8086

master receiving intervening memory cycles. This is useful in multiprocessor system configurations to accomplish "test and set lock" operations. The lOCK signal is activated (forced lOW) in the clock cycle following the one in which the software" lOCK" prefix instruction is decoded by the EU. It is deactivated at the end of the last bus cycle of the instruction following the "lOCK" prefix instruction. While LOCK is active, a request on a RQ/GT pin will be recorded and then honored at the end of the lOCK.

External Synchronization Via Test

As an alternative to the interrupts and general I/O capabilities, the 8086 provides a single software-testable input known as the TEST signal. At any time, the program may execute a WAIT instruction. If at that time the 'fEST signal is inactive (HIGH), program execution becomes suspended while the processor waits for TEST to become active. It must remain active for at least 5 ClK cycles. The WAIT instruction is re- executed repeatedly until that time. This activity does not consume bus cycles. The processor remains in an idle state while waiting. All 8086 drivers go to three-state OFF if bus

"HOLD" is entered. If interrupts are enabled, they may occur while the processor is waiting. When this occurs, the proces- sor fetches the WAIT instruction one extra time, processes the interrupt, and then re-fetches and re-executes the WAIT instruction upon returning from the interrupt.

Basic System Timing

Typical system configurations for the processor operating in minimum mode and in maximum mode are shown in Figures 2a and 2b, respectively. In minimum mode, the processor emits bus control signals in a manner similar to the 8085. In maximum mode, the processor emits coded status information which the 8288 bus controller uses to generate MUl TIBUS compatible bus control signals. Figure 3 illustrates the signal timing relationships.

System Timing - Minimum System

The read cycle begins in T 1 with the assertion of the Address latch Enable (ALE) Signal. The trailing (low-going) edge of this signal is used to latch the address information, which is valid on the local bus at this time, into the 8282/8283 latch. The BHE and Ao signals address the low, high, or both bytes. From T 1 to T 4, the M/iO signal indicates a' memory or I/O operation.

At T 2 the address is removed from the local bus and the bus goes to a high impedance state. The read control signal is also asserted at T 2. The read (RD) Signal causes the addressed device to enable its data bus drivers to the local bus. Some time later valid data will be available on the bus and the addressed device will drive the READY line HIGH. When the processor returns the read signal to a HIGH level, the addressed device will again 3-state its bus drivers. If a transceiver (8286/8287) is required to buffer the 8086 local bus, signals DT /A and DEN are provided by the 8086.

A write cycle also begins with the assertion of ALE and the emission of the address. The M/iO signal is again asserted to indicate a memory or I/O write operation. In the T 2 immediate- ly following the address emission, the processor emits the data to be written into the addressed location. This data remains valid until the middle of T 4. During T 2, T 3, and Tw, the processor asserts the write control signal. The write (WR) Signal becomes active at the beginning of T 2 as opposed to the read which is delayed somewhat into T 2 to provide time for the bus to float.

The BHE and Ao signals are used to select the proper byte(s) of the memory/lO word to be read or written according to the following table.

1-13

..