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Founded in 1968 to pursue the integration of large numbers of transistors onto tiny silicon chips, Intel's history has been marked by a remarkable number of scientific breakthroughs and innovations. In 1971, Intel introduced the 4004, the first microprocessor. Containing 2300 transistors, this first commercially-available computer on a chip is considered primitive compared with today's million-plus transistor products.

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inta L

MCS® .. 48 Single Component System

MCS® .. 48 Expanded System

MCS® .. 48 Instruction Set

MCS® .. 48 Data Sheets MCS® .. 51 Architectural Overview

MCS® .. 51 Programmer's Guide and Instruction Set

MCS® .. 51 Hardware

Descriptions and Data Sheets 8XC51FX Hardware

Description and Data Sheets

8XC51 GB Hardware

Description and Data Sheets

int:e ^t

83ClS2 Hardware

Description and Data Sheet MCS® .. Sl Development Support Tools

RUPI .. 44 Family

MCS® .. 80/8S Data Sheets

MCS® .. 96 Architectural • Overview and Quick References ~

8X9X Data Sheets •

8XC196KBDataSheets . .

8XC 1 96KC Data Sheet

8XC196KD Data Sheets II

int:e ^t

8XC196KRDataSheet •

8XCI96NT/8XCI96NQand • 8XC 196KT Data Sheets

8XC 196MC Data Sheet MCS® .. 96 Development Support Tools . MCS® .. 51 and MCS .. 96 Packaging Information 80186/188/CI86/CI88 Data Sheets

80186/80188 Development Support Tools

i3 7 6 ™ Processor and Peripherals Data Sheets i3 7 6™ Processor Development Tools

II

II

III

II

II •

infel·

CAN 82527 Data Sheet

CAN 82527 Development

Tool

Table of Contents

Alphanumeric Index ... .-... ... ... xxi MCS®-48 FAMILY

Chapter 1

MCS®-48 Single Component System ... ... ... 1-1 Chapter 2

MCS®-48 Expanded System. . . 2-1 Chapter 3

MCS®-48 Instruction Set. . . .. . . 3-1 Chapter 4

MCS®-48 DATA SHEETS

8243 MCS-48 Input/Output Expander.. . . .. . . .. . . 4-1 P87 48H/P87 49H/8048AH/8035AHL/8049AH/8039AHLl8050AH/8040AH L

HMOS Single Component 8-Bit Microcontroller ... 4-8 D8748H/D8749H HMOS-E Single-Component 8-Bit Microcontroller .. . . .. . . 4-21 P8049KB HMOS Single-Component 8-Bit Microcontroller ... 4-33 MCS-48 Express . . . 4-45 MCS®-51 FAMILY

Chapter 5

MCS-51 Family of Microcontrollers Architectural Overview. . . .. . . 5-1 Chapter 6

MCS-51 Programmer's Guide and Instruction Set. . . 6-1 Chapter 7

8051,8052 and 80C51 Hardware Description ... ;. . . 7-1 8XC52/54/58 Hardware Description. . . .. . . 7-37 8X5X DATA SHEETS

MCS-51 8-Bit Control-Oriented Microcontrollers 8031 AH/8051 AH/8032AH /

8052AH/8751 H/8751 H-8 . .. . .. . .. .. .. .. .. . .. . .. . .. . .. .. .. . .. . ... . .. . . 7-48 8051 AHP MCS-51 Family 8-Bit Control-Oriented Microcontroller with Protected

ROM... 7-63 8751 BH Single-Chip 8-Bit Microcontroller with 4 Kbytes of EPROM Program

Memory. . . 7 -73 8751BH Express... 7-85 8752BH Single-Chip 8-Bit Microcontroller with 8 Kbytes of EPROM Program

Memory. . . .. . . 7 -87 8752BH Express. . . .. . . 7-99 8XC5X DATA SHEETS

80C31BH/80C51BH Express ... 7-101 80C51 BHP CHMOS Single-Chip 8-Bit Microcontroller with Protected ROM. . . .. 7 -103 87C51 /80C51 BH/80C31 BH CHMOS Single-Chip 8-Bit Microcontroller with

4 Kbytes Internal Program Memory . . .. . .. . .. .. . .. . .. .. .. .. . .. . .. . . .. . .. ... 7-117 87C51 Express ... 7-136 87C51-20/-3 Commercial/Express 20 MHz CHMOS Microcontroller ... 7-139 8XC51 SLlLow Voltage 8XC51SL Keyboard Controller. . . .. . . .. 7-153 87C52/80C52/80C32 CHMOS Single-Chip 8-Bit Microcontroller with 8 Kbytes

Internal Program Memory ... . . . .. 7-154 87C52/80C52/80C32 Express. .. . .. .. .. . .. . . . .. . . . .. . . .. .. . .. .. .. .. . .. .. 7 -170 87C52-20/80C52-20/80C32-20 Commercial/Express 20 MHz Microcontroller .... 7-172 87C54/80C54 CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes Internal

Program Memory. . . .. 7 -188 87C54/80C54 Express ... 7-204 87C54-201-3 80C54-20/-3 Commercial/Express 20 MHz Microcontroller . . . .. 7-206

Table of Contents

87C58/80C58 CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes Internal

Program Memory. . . .. 7-222 87C58/80C58 Express ... 7-239 87C58-201-3 80C58-201-3 Commercial/Express 20 MHz Microcontroller . . . .. 7 -241

Chapter 8

8XC51 FX Hardware Description. . . 8-1 8XC51FX DATA SHEETS

83C51 FA/80C51 FA Express ... 8-44 87C51 FA/83C51 FAl80C51 FA CHMOS Single-Chip 8-Bit Microcontroller with 8

Kbytes Internal Program Memory ... : . . . .. . . 8-46 87C51 FA Express. . . .. . . 8-65 87C51 FA-201-3 Commercial/Express 20 MHz CHMOS Microcontroller ... 8-68 87C51 FB/83C51 FB CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes

Internal Program Memory. . . .. . . 8-83 87C51 FB-201-3 83C51 FB-201-3 Commercial/Express 20 MHz Microcontroller . . .. 8-100 87C51 FC/83C5tFC CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes

Internal Program Memory ... i • • • • • • • • • • • • . • • • • • • • •• 8-115 87C51 FC/83C51 FC Express ... , 8-132 87C51 FC-201-3 83C51 FC-201-3 Commercial/Express 20 MHz Microcontroller.... 8-134 Chapter 9

87C51GB Hardware Description... 9-1 8XC51GB DATA SHEETS

87C51 GB/83C51 GB/80C51 GB CHMOS Single-Chip 8-Bit Microcontroller. . .. . . 9-56 87C51 GB/80C51 GB CHMOS Single-Chip 8-Bit Microcontroller Express. . . 9-78 Chapter 10

83C152 Hardware Description .. . . 10-1

8XC152JXDATASHEET .

8XC152JAI JBI JCI JD Universal Communication Controller 8-Bit Microcontroller .. 10-71 Chapter 11

MCS®-51 DEVELOPMENT SUPPORT TOOLS

Development Tools for the MCS-51 Family of Microcontrollers ... .11-1 ACE51 FX Software. . . .. . . 11-7 EV80C51 FX Evaluation Board ... . . . 11-8 EV80C51 GX Evaluation Board.. . .. . . .. . . ... . . .. . .. . .. .. .. .. .. .. .. .. . .. . .. 11-11 THE RUPI FAMILY

Chapter 12

The RUPI-44 Family: Microcontroller with On-Chip Communication Controller. . . 12-1 8044 Architecture . . . .. . . 12-9 The RUPI-44 Serial Interface Unit ... 12-19 8044 Application Examples. . . .. 12-57 8044 DATA SHEET

8044AH/8344AH/8744AH High Performance 8-Bit Microcontrollerwith On-Chip

Serial Communication Controller ... 12-131 MCS®-80/85 FAMILY

Chapter 13

MCS®-80/85 DATA SHEETS

8080Al8080A-1/8080A-2 8-Bit N-Channel Microprocessor. . . 13-1 8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors . . . .. 13-11 8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and

Timer. . . .. 13-31 8185/8185-21024 x 8-Bit Static RAM for MCS®-85... ... 13-45 8224 Clock Generator and Driver for 8080A CPU. . . .. 13-50

xviii

Table of Contents

8228 System Controller and Bus Driver for 8080A CPU. . . .. 13-55 8755A 16,384-Bit EPROM with 1/0 . . . .. 13-59 MCS®·96 FAMILY

Chapter 14

MCS-96 Architectural Overview . . . 14-1 8X9X Quick Reference. . . .. 14-15 8XC196KB Quick Reference. . . • . . . .. 14-40 8XC196KC Quick Reference. . . .. 14-73 8XC196KD Quick Reference ... 14-104 8XC196KR Quick Reference ... 14-134 8XC196KT Quick Reference ... 14-161 8XC196MCQuick Reference ... 14-190 8XC196NT /NQ Quick Reference ... 14-224 MCS-96 AID Converter Quick Reference ... 14-253 Chapter 15

8X9X DATA SHEETS

809XBH/839XBH/879XBH Commercial/Express HMOS Microcontroller... 15-1 8097JF/8397JF/8797JF Commercial/Express HMOS Microcontroller ... 15-23 8098/8398/8798 Commercial/Express HMOS Microcontroller . . . .. 15-42 Chapter 16

8XC196KB DATA SHEETS

80C196KB1 0/83C196KB1 0/80C196KB12/83C196KB12 Commercial/Express

CHMOS Microcontroller. . . .. .. . . .. . . . •. . . . 16-1 80C198/83C198/80C194/83C194 Commercial/Express CHMOS Microcontroller. 16-22 8XC196KB/8XC196KB16 Commercial/Express CHMOS Microcontroller . . . .. 16-38 8XC198 Commercial CHMOS Microcontroller . . . .. 16-60 Chapter 17

8XC196KC DATA SHEET

8XC196KC Commercial/Express CHMOS Microcontroller . . . 17-1 Chapter 18

8XC196KD DATA SHEETS

8XC196KD/8XC196KD20 Commercial CHMOS Microcontroller . . . 18-1 8XL 196KD Commercial CHMOS Microcontroller ...•... 18-26·

Chapter 19

8XC196KR DATA SHEET

8XC196KR/KQ/JR/JQ Commercial/Express CHMOS Microcontroller ... 19-1 Chapter 20

8XC196NT 18XC196NQ AND 8XC196KT DATA SHEETS

8XC196NT /8XC196NQ CHMOS Microcontroller .. . . 20-1 8XC196KT Commercial CHMOS Microcontroller ... 20-33 Chapter 21

, 8XC196MC DATA SHEET

87C196MC Industrial Motor Control Microcontroller. . . 21-1 Chapter 22

MCS®-96 DEVELOPMENT SUPPORT TOOLS

ICE-196KD/HX In-Circuit Emulator. .. . .. . . .. . . .. . . 22-1 ICE-196 KD/PC In-Circuit Emulator. . . 22-6 MCS-96 Software Development Packages.. . . .. . . .. . . .. . . 22-9 ApBuilder Programming Package. . .. . . ... . . .. 22-12 EV80C196KX/EV8097BH/EV80C196KB/EV80C196KC/EV80C196KD Evaluation

Boards ... 22-15 EV80C196KR Evaluation Board. . . .. 22-22

Table of Contents

EV80C196MC Evaluation Board. . . .. 22-24

Chapter 23

MCS®-51 and MCS-96 PACKAGING INFORMATION

MCS-51 and MCS-96 Packaging Information ... , ... ,... 23-1 80186/80188 FAMILY

Chapter 24

80186/188/C186/C188 DATA SHEETS

80186 High Integration 16-Bit Microprocessor. . . 24-1 80C186 CHMOS High Integration 16-Bit Microprocessor... 24-59 80C186XL20, 16, 12, 1016-Bit High Integration Embedded Processor ... 24-128 80C186EA20, 16, 1216-Bit High Integration Embedded Processor ... 24-174 80C186EB-20 ,-16, -13, -8, 16-Bit High-Integration Embedded ProceSsor ... 24-227 80C186EC-16, -13 16-Bit High-Integration Embedded Processor ... 24-283 80l186EA816-Bit High Integration Embedded Processor ...•.. 24-338 80L 186EB" 13, -8, 16-Bit High-Integration Embedded Processor .•... 24-366 80C187 80-Bit Math Coprocessor ... 24-390 80188 High Integration 8-Bit Microprocessor ...•...•.... 24-420 80C188 CHMOS High Integration 16-Bit Microprocessor ... ; 24-479 80C188XL20, 16, 12, 10 16-Bit High Integration Embedded Processor ... 24-551 80C188EA20, 16, 12 16-Bit High Integration Embedded Processor ... 24-597 80C188EB-20, -16, -13, -8 16-Bit High-Integration Embedded Processor ... 24-649 80C188EC-16, -13 16-Bit High-Integration Embedded Processor ...•.. 24-704 80l188EA816-Bit High Integration Embedded Processor ...•.. 24-761 80l188EB-13, -8, 16-Bit High-Integration Embedded Processor ...•... 24-788 82188 Integrated Bus Controller for 8086, 8088, 80186, 80188 Processors ... 24-812 Chapter 25

80186/80188 DEVELOPMENT SUPPORT TOOLS

ICE-186/188 Family In-Circuit Emulator ... , . .. . . .. . . .. . . .. . . ... .. 25-1 8086/80C186 Software Development Tools. . . .. . . • . . . • 25-8 EV80C186EAlXL Evaluation Board .... .'. . . .. 25-13 . EV80C186EB Evaluation Board. . . .. 25-16 EV80C186EC Evaluation Board. . . .. . . .. 25-19 DB86A Artic Software Debugger ... 25-21 i376™ EMBEDDED PROCESSOR

Chapter 26

i376TM PROCESSOR AND PERIPHERALS DATA SHEETS

376. High Performance 32-Bit Embedded Processor ...•...•. 26-1 Intel387 SXMath CoProcessor ...•... ~ . . . • . . .. 26-96 82355 Bus Master Interface Controller.(BMIC) '.. . . .. . . .. . . .. 26-97 82370 Integrated System Peripheral . . . .. . . • . . . .. 26-98 82596DX and 82596SX High-Performance 32-Bit Local Area Network'

Coprocessor ... 26-99 Chapter 27

i376TM PROCESSOR DEVELOPMENT TOOLS

Intel386 and Intel486 Family Development Support.. . . .. .. .. . . ... . . 27-1 TRANS 186-376 Assembly Code Translator... 27-9 CAN 82527 CONTROLLER

Chapter 28

82527 DATA SHEET

Serial Communications Controller (Controller Area Network Protocol) . . . 28-1 Chapter 29

82527 DEVELOPMENT TOOL

EV82527 Evaluation Kit... 29-1 xx

Alphanumeric Index

376 High Performance 32-Bit Embedded Processor. . . .. . . 26-1 80186 High Integration 16-Bit Microprocessor... 24-1 80188 High Integration 8-Bit Microprocessor ... 24-420 8044 Application Examples . . . .. 12-57 8044 Architecture. . . 12-9 8044AH/8344AH/8744AH High Performance 8-Bit Microcontroller with On-Chip Serial

Communication Controller ... 12-131 8051, 8052 and 80C51 Hardware Description. . . 7-1 8051AHP MCS-51 Family 8-Bit Control-Oriented Microcontroller with Protected ROM. . . 7-63 8080A/8080A-1 /8080A-2 8-Bit N-Channel Microprocessor. . . 13-1 8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors. . . .. 13-11 8086/80C186 Software Development Tools. . . 25-8 8097 JF /8397 JF /8797 JF Commercial/Express HMOS Microcontroller . . . .. 15-23 8098/8398/8798 Commercial/Express HMOS Microcontroller ... 15-42 809XBH/839XBH/879XBH Commercial/Express HMOS Microcontroller... 15-1 80C186 CHMOS High Integration 16-Bit Microprocessor. . . .. 24-59 80C186EA20, 16, 12 16-Bit High Integration Embedded Processor ... 24-174 80C186EB-20 ,-16, -13, -8, 16-Bit High-Integration Embedded Processor ... 24-227 80C186EC-16, -13 16-Bit High-Integration Embedded Processor ... 24-283 80C186XL20, 16, 12, 10 16-Bit High Integration Embedded Processor ... 24-128 80C187 80-Bit Math Coprocessor ... 24-390 80C188 CHMOS High Integration 16-Bit Microprocessor ... 24-479 80C188EA20, 16, 12 16-Bit High Integration. Embedded Processor ... 24-597 80C188EB-20, -16, -13, -816-Bit High-Integration Embedded Processor ... 24-649 80C188EC-16, -13 16-Bit High-Integration Embedded Processor ... 24-704 80C188XL20, 16, 12, 10 16-Bit High Integration Embedded Processor ... 24-551 80C196KB1 0/83C196KB1 0/80C196KB12/83C196KB12 Commercial/Express CHMOS

Microcontroller . . . 16-1 80C198/83C198/80C194/83C194 Commercial/Express CHMOS Microcontroller. . . .. 16-22 80C31BH/80C51BH Express ... 7-101 80C51 BHP CH MOS Single-Chip 8-Bit Microcontroller with Protected ROM ... 7 -103 80L 186EA8 16-Bit High Integration Embedded Processor ... 24-338 80L 186EB-13, -8, 16-Bit High-Integration. Embedded Processor ... 24-366 80L 188EA8 16-Bit High Integration Embedded Processor ... 24-761 80L 188EB-13, -8, 16-Bit High-Integration Embedded Processor ... 24-788 8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer.. 13-31 8185/8185-21024 x 8-Bit Static RAM for MCS®-85 ... 13-45 82188 Integrated Bus Controller for 8086, 8088, 80186, 80188 Processors ... 24-812 8224 Clock Generator and Driver fOi 8080A CPU. . . .. . . .. 13-50 8228 System Controller and Bus Driver for 8080A CPU ... 13-55 82355 Bus Master Interface Controller (BMIC) . . . .. 26-97 82370 Integrated System Peripheral. . . .. 26-98 8243 MCS-48 Input/Output Expander. . . .. . . 4-1 82596DX and 82596SX High-Performance 32-Bit Local Area Network Coprocessor ... 26-99 83C152 Hardware Description. . . 10-1 83C51 FAl80C51 FA Express. . . 8-44 8751 BH Express. . . .. . . 7-85 8751 BH Single-Chip 8-Bit Microcontroller with 4 Kbytes of EPROM Program Memory. . . .. 7-73 8752BH Express... 7-99 8752BH Single-Chip 8-Bit Microcontroller with 8 Kbytes of EPROM Program Memory. . . 7-87 8755A 16,384-Bit EPROM with I/O ... 13-59 87C196MC Industrial Motor Control Microcontroller ... . . . 21-1 87C51 Express. . . .. . . .. . . .... 7-136 87C51-20/-3 Commercial/Express 20 MHz CHMOS Microcontroller ... , . . . .... 7-139

Alphanumeric Index

. 87C51 /80C51 BH/80C31 BH CHMOS Single-Chip 8-Bit Microcontroller with 4 Kbytes

Internal Program Memory . . . .. . . .. 7-117 87C51 FA Express. . . .. . . 8-65 87C51 FA-20/-3 Commercial/Express 20 MHz CHMOS Microcontroller ... 8-68 87C51 FAl83C51 FAl80C51 FA CHMOS Single-Chip 8-Bit Microcontroller with 8 Kbytes

Internal Program Memory ... ' . . . 8-46 87C51 FB-20/ -3 83C51 FB-20/ -3 Commercial/Express 20 MHz Microcontroller ... 8-100 87C51 FB/83C51 FB CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes Internal

Program Memory ... 8-83 87C51 FC-20/ -3 83C51 FC-20/ -3 Commercial/Express 20 MHz Microcontroller ... 8-134 87C51 FC/83C51 FC CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes Internal

Program Memory .. . . .. 8-115 87C51 FC/83C51 FC Express ... 8-132 87C51GB Hardware Description... ... 9-1 87C51GB/80C51GB CHMOS Single-Chip 8-BitMicrocontrolier Express... .. 9-78 87C51GB/83C51GB/80C51GB CHMOS Single-Chip 8-Bit Microcontroller ... 9-56 87C52-20/80C52-20/80C32-20 Commercial/Express 20 MHz Microcontroller . . . .. 7 -172 87C52/80C52/80C32 CHMOS Single-Chip 8-Bit Microcontroller with 8 Kbytes Internal

Program Memory... 7-154 87C52/80C52/80C32 Express ... 7-170 87C54-20/-3 80C54-20/-3 Commercial/Express 20 MHz Microcontroller. . . .. 7-206 87C54/80C54 CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes Internal Program

Memory... 7-188 87C54/80C54 Express... 7-204 87C58-20/ -3 80C58-20/ -3 Commercial/Express 20 MHz Microcontroller ... , 7-241 87C58/80C58 CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes Internal Program

Memory .... ;... 7-222 87C58/80C58 Express. . . .. . . .. 7-239 8X9X Quick Reference ... '.' 14-15 8XC152JAI JB/ JC/ JD Universal Communication Controller 8-Bit Microcontroller . . . .. 10-71 8XC196KB Quick Reference ... . . . .. . . .. 14-40 8XC196KB/8XC196KB16 Commercial/Express CHMOS Microcontroller. . . .. 16-38 8XC196KC Commercial/Express CHMOS Microcontroller. . . 17-1 8XC196KC Quick Reference ... 14-73 8XC196KD Quick Reference ... 14-104 8XC196KD/8XC196KD20 Commercial CHMOS Microcontroller . . . 18-1 8XC196KR Quick Reference ... ' ... 14-134 8XC196KR/KQ/JR/JQ Commercial/Express CHMOS Microcontroller... 19-1 8XC196KT Commercial CHMOS Microcontroller . . . .. 20-33 8XC196KT Quick Reference ... 14-161 8XC196'MC Quick Reference ... 14-190 . 8XC196NT /8XC196NQ CHMOS Microcontroller . . . 20-1 8XC196NT /NQ Quick Reference ... 14-224 8XC198 Commercial CHMOS Microcontroller ... ; . . . .. 16-60 8XC51 FX Hardware Description ... 8-1 8XC51 SL/Low Voltage 8XC51 SL Keyboard Controller. . . .. 7-153 8XC52/54/58 Hardware Description .. ~ . . . • . . . 7-37 8XL 196KD Commercial CHMOS Microcontroller . . . • . . . .. 18-26 ACE51 FX Software ... 11-7 ApBuilder Programming Package ... 22-12 D8748H/D8749H HMOS-E Single-Component 8-Bit Microcontroller . . . 4-21 DB86A Artic Software Debugger. . . .. 25-21 DevelopmentTools for the MCS-51 Family of Microcontrollers... 11-1 EV80C186EAlXL Evaluation Board... 25-13

xxii

Alphanumeric Index

EV80C186EB Evaluation Board. . . .. 25-16 EV80C186EC Evaluation Board. . . .. 25-19 EV80C196KR Evaluation Board .. . . .. 22-22 EV80C196KX/EV8097BH/EV80C196KB/EV80C196KC/EV80C196KD Evaluation

Boards . . . .. 22-15 EV80C196MC Evaluation Board . . . .. 22-24 EV80C51 FX Evaluation Board. . . 11-8 EV80C51 GX Evaluation Board. . . .. 11-11 EV82527 Evaluation Kit. .. . . 29-1 ICE-186/188 Family In-Circuit Emulator. . . 25-1 ICE-196 KD/PC In-Circuit Emulator ... 22-6 ICE-196KD/HX In-Circuit Emulator. . . 22-1 Intel386 and Intel486 Family Development Support.. ... ... ... 27-1 Intel387 SX Math CoProcessor . . . .. 26-96 MCS-48 Express. . . 4-45 MCS-51 8-Bit Control-Oriented Microcontrollers 8031 AH/8051 AH/8032AH/8052AHI

8751H/8751H-8 ... 7-48 MCS-51 and MCS-96 Packaging Information. . . 23-1 MCS-51 Family of Microcontrollers Architectural Overview... ... 5-1 MCS-51 Programmer's Guide and Instruction Set. . . .. . . 6-1 MCS-96 AID Converter Quick Reference ... 14-253 MCS-96 Architectural Overview. . . . .. . . 14-1 MCS-96 Software Development Packages . . . 22-9 MCS®-48 Expanded System ... 2-1 MCS®-48 Instruction Set. . . 3-1 MCS®-48 Single Component System. . . 1-1 P8049KB HMOS Single-Component 8-Bit Microcontroller . . . 4-33 P87 48H/P87 49H/8048AH/8035AHL/8049AH 18039AHLl8050AH/8040AHL HMOS

Single Component 8-Bit Microcontroller . . . 4-8 Serial Communications Controller (Controller Area Network Protocol) . . . 28-1 The RUPI-44 Family: Microcontroller with On-Chip Communication Controller. . . 12-1 The RUPI-44 Serial Interface Unit. . . .. 12-19 TRANS 186-376 Assembly Code Translator... 27-9

, MCS®--48 Single Component 1

System

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THE SINGLE COMPONENT MCS(B;·48 SYSTEM

1.0 INTRODUCTION

Section; 2 through S describe in detail the func- tional characteristics of the 8748H and 8749H EPROM, 8048AH/8049AH/80S0AH ROM, and 8035AHLI 8039AHU8040-AHL CPU only single component micro- computers. Unless otherwise noted, details within these sections apply to all versions. This chapter is limited to those functions useful in single-chip implementations of the MCS~.-48. The Chapter on the Expanded MCS~-48 System discusses functions which allow expansion of program memory. data memory. and input output capa- bility.

2.0 ARCHITECTURE

The following sections break the MCS-48 Family into functional blocks and describe each in detail. The follow- ing description will use the 8048AH as the representative product for the family. See Figure L

2.1 Arithmetic Section

The arithmetic section of the processor contains the basic data manipulation functions of the 8048AH and can be divided into the following blocks:

• Arithmetic Logic Unit (ALU)

• Accumulator

• Carry Flag

• Instruction Decoder

In a typical operation data stored in the accumulator is combined in the ALU with data from another source on the internal bus (such as a register or I/o port) and the result is stored in the accumulator or another register.

The following is more detailed description of the function of each block.

INSTRUCTION DECODER

The operation code (op code) portion of each program instruction is stored in the Instruction Decoder and con-, verted to outputs which control the function of each of the blocks of the Arithmetic Section. These lines control the source of data and the destination register as well as the function performed in the ALU.

ARITHMETIC LOGIC UNIT

The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under control of the Instruc- tion Decoder. The ALU can perform the following functions:

• Add With or Without Carry

• AND. OR. Exclusive OR

• IncrementlDecrement

• Bit Complement

• Rotate Left. Right

• Swap Nibbles

• BCD Decimal Adjust

If the operation performed by the ALU results in a value represented by more than 8 bits (overflow of most sig- nificant bit), a Carry Flag is set in the Program Status Word.

ACCUMULATOR

The accumulator is the single most important data register in the processor. being one of the sources of input to the ALU and often the destination of the result of operations performed in the ALU. Data to and from 110 ports and memory also normally passes through the accumulator.

2.2 Program Memory

Resident program memory consists of 1024. 2048. or 4096 words eight bits wide which are addressed by the program counter. In the 8748H and the 8749H this memory is user programmable and erasable EPROM; in the 8048AHI 8049AHl8050AH the memory is ROM which is mask programmable at the factory. The 8035AHUB039AHU B040AHL has no internal program memory and is used with external memory devices. Program code is com- pletely interchangeable among the various versions. To access the upper 2K of program memory in the 8050AH.

and other MCS-48 devices, a select memory bank and a JUMP or CALL instruction must be executed to cross the 2K boundary.

There are three locations in Program Memory of special importance as shown in Figure 2.

LOCATION 0

Activating the Reset line of the processor causes the first instruction to be fetched from location O.

LOCATION 3

Activating the Interrupt input line of the processor (if interrupt is enabled) causes a jump to subroutine at lo- cation 3.

LOCATION 7

A timer/counter interrupt resulting from timer counter overflow (if enabled) causes a jump to subroutine at loca- tion 7.

Therefore. the first instruction to be executed after ini- tialization is stored in location O. the first word of an external interrupt service subroutine is stored in location 3, and the first word of a timer/counter service routines

"II

iii c

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QI ~

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~ PROGRAM SUPPLY POWER { V

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EXPANDER MEMORY I STROBE SEPARATE INITIALIZE

OSCILLATOR XTAl

RESIDENT EPROM ROM

ADDRESS LATCH STROBE

CYCLE CLOCK

PROGRAM SINGLE MEMORY STEP

ENABLE

READ WRITE- STROBES

EXPANSION TO MORE 110 AND MEMORY

TEST 0 TE5T1

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0 FlAG 0 0 u w FLAG 1 0 TIMER

FlAG CARRY ACC Ace BIT

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REGISTER 1 is:

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REGISTER 2

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REGISTER 3

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REGISTER 4 ~

00

REGISTER 5

en

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REGISTER 6

en

REGISTER 7 -I

8 lEVEL STACK m

is:

(VARIABLE LENGTH) OPTIONAL SECOND REGISTER ,BANK

DATA STORE

RESIDENT RAM ARRAY

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is stored in location 7. Program memory can be used to store constants as well as program instructions. Instruc- tions such as MOVP and MOVP3 allow easy access to data "lookup" tables.

- 0

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7 6 5 4 3 2 1

o 716151413121110 ~ ADDRESS

LOCATION 7 - TIMER INTERRUPT VECTORS PROGRAM HERE LOCATION 3 - EXTERNAL INTERRUPT VECTORS PROGRAM HERE RESET VECTORS PROGRAM HERE

'Figure 2. Program Memory Map 2.3 Data Memory

Resident data memory is organized as 64, 128, or 256 by 8-bits wide in the 8048AH, 8049AH and 8050AH. All locations are indirectly addressable through either of two RAM Pointer Registers which reside at address 0 and I of the register array. In addition, as shown in Figure 3, the first 8 locations (0-7) of the array are designated as working registers and are directly addressable by several instructions, Since these registers are more easily ad- dressed, they are usually used to store frequently accessed intermediate results. The DJNZ instruction makes very efficient use of the working registers as program loop counters by allowing the programmer to decrement and test the register in a single instruction.

By executing a Register Bank Switch instruction (SEL RB) RAM locations 24-31 are designated as the working

registers in place of locations 0-7 and are then directly addressable. This second bank of working registers may be used as an extension of the first bank or reserved for use during interrupt service subroutines allowing the reg- isters of Bank 0 used in the main program to be instantly

"saved" by a Bank Switch. Note that if this second bank is not used, locations 24-31 are still addressable as general purpose RAM. Since the two RAM pointer Registers RO and RI are a part of the working register array, bank switching effectively creates two more pointer registers (ROland RII) which can be used with RO and RI to easily access up to four separate working areas in RAM at one time. RAM locations (8-23) also serve a dual role in that they contain the program counter stack as explained in Section 2.6. These locations are addressed by the Stack Pointer during subroutine calls as well as by RAM Pointer Registers RO and R I. If the level of subroutine nesting is less than 8, all stack registers are not required and can be used as general purpose RAM locations. Each level of subroutine nesting not used provides the user with two additional RAM locations.

(12~ , . . . - - - . ((255))

USER RAM 32 x 8 (96 x 8) ((224 x 8)) 32t-____________ ^~

31 BANK 1

WORKING REGISTERS

8x8 ---Fif- - - -

24 ----AD' - - - - 23

8 LEVEL STACK OR USER RAM

16 x 8

8 7t---~B~A~NK~0---i

WORKING REGISTERS

8^x8

t---

o ---RO----

DIRECTLY

I

ADDRESSABLE WHEN BANK 1 IS SELECTED

I

ADDRESSED INDIRECTLY THROUGH

R1 OR RO (RO' OR R1') DIRECTLY

I

ADDRESSABLE WHEN BANK 0 IS SELECTED

I

IN ADDITION RO OR R1 (RO' OR R1')

MAY BE USED TO ADDRESS 256 ( ) 8049AH. 8749H.

WORDS OF EXTERNAL RAM. (( )) 8050AH

Figure 3. Data Memory Map

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VCC VCC

INTERNAL a

BUS D

D FLIP FLOP

LOW IMPEDANCE PULLDOWN CLK a

WRITE

PULSE

-=-

IN

4V

VOH VOH(V)

OV 1/0 PIN PORTl

AND 2

2V VOL

4V

LOW IMPEDANCE PULLUP HIGH IMPEDANCE PULLUP LOW IMPEDANCE PULLDOWN

These graphs are for Informational purposes only and are not guaranteed minimums or maximums.

Figure 4. "Quasi-bidirectional" Port Structure

1·4

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2.4 Input/Output

The 8048AH has 27 lines which can be used for input or output functions. These lines are grouped as 3 pons of 8 lines each which serve as either inputs. outputs or bidi- rectional pons and 3 "test" inputs which can alter pro- gram sequences when tested by conditional jump instructions.

PORTS 1 AND 2

Pons I and 2 are each 8 bits wide and have identical characteristics. Data written to these pons is statically latched and remains unchanged until rewritten. As input pons these lines are non-latching. i.e., inputs must be present until read by an input instruction. Inputs are fully 1TL compatible and outputs will drive one standard 1TL load.

The lines of pons I and 2 are called quasi-bidirectional because of a special output circuit structure which allows each line to serve as an input, and output, or both even though outputs are statically latched. Figure 4 shows the circuit configuration in detail. Each line is continu- ously pulled up to VCC through a resistive device of relatively high impedance.

This pullup is sufficient to provide the source current for a 1TL high level yet can be pulled low by a standard 1TL gate thus allowing the same pin to be used for both input and output. To provide fast switching times in a "0" to

"I" transition a relatively low impedance device is switched in momentarily ( ... liS of a machine cycle) when- ever a "I" is written to the line. When a "0" is written to the line a low impedance device overcomes the light pullup and provides 1TL current sinking capability. Since the pulldown transistor is a low impedance device a "I"

must first be written to any line which is to be used as an input. Reset initializes all lines to the high impedance "I"

state.

It is important to note that the ORL and the ANL are read!

write operations. When executed, the p£ "reads" the pon, modifies the data according to the instruction, then

"writes" the data back to the pon. The "writing" (es- sentially an OUTL instruction) enables the low impedance pull-up momentarily again even if the data was unchanged from a "1." This specifically applies to configurations that have inputs and outputs mixed together on the same port. See also section 8 in the Expanded MCS-48 System chapter.

BUS

Bus is also an 8-bit port which is a true bidirectional port with associated input and output strobes. If the bidirec- tional feature is not needed, Bus can serve as either a

1-5

statically latched output port or non-latching input port.

Input and output lines on this pon cannot be mixed however.

As a static pon, data is written and latched using the OUTL instruction and inputted using the INS instruction. The INS and OUTL instructions generate pulses on the cor- responding RD and WR output strobe lines; however, in the static port mode they are generally not used. As a bidirectional port the MOVX instructions are used to read and write the port. A write to the port generates a pulse on the WR ou~ line and output data is valid at the trailing~e of WR. A read of the port generates a pulse on the RD output line and input data must be valid at the trailing edge of RD. When not being written or read, the BUS lines are in a high impedance state. See also sections 7 and 8 in the Expanded MCS-48 System chapter.

2.5 Test and INT Inputs

Three pins serve as inputs and are testable with the~­

ditional jump instruction. These are TO, TI, and INT.

These pins allow inputs to cause program branches without the necessity to load an input port into the accumulator.

The TO,

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2.6 Program Counter and Stack

The Program Counter is an independent counter while the Program Counter Stack is implemented suing pairs of reg- isters in the Data Memory Array. Only 10, 11, or 12 bits of the Program Counter are used to address the 1024, 2048, or 4096 words of on-board program memory of the 8048AH, 8049AH, or 8050AH, while the most significant bits can be used for external Program Memory fetches.

See Figure 5. The Program Counter is initialized to zero by activating the Reset line.

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Conventional Program Counter

• Count. OOOH to 7FFH

• Overflow. 7FFH to OOOH

, Figure 5. Program Counter

An interrupt or CALL to a subroutine causes the contents of the program counter to be stored in one ofthe 8 register pairs of the Program Counter Stack as shown in Figure 6. The pair to be used is determined by a 3-bit Stack Pointer which is part of the Program Status Word (PSW).

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TER _--"'-

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the word. The Program Status Word is actually a collection of flip-flops throughout the machine which can be read or written as a whole. The ability to write to PSW allows for easy restoration of machine status after a power down

--"- ²² sequence.

110

101

100

011

010

001

000

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psw

•

PC4-7

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MSB LSB

Figure 6. Program Counter Stack

21 20 19 lS 17 16 lS 14 13 12 11 10 9 RS

Data RAM locations 8-23 are available as stack registers and are used to store the Program Counter and 4 bits of PSW as shown in Figure 6. The Stack Pointer when initialized to 000 points to RAM locations 8 and 9. The first subroutine jump or interrupt results in the program counter contents being transferred to locations 8 and 9 of the RAM array. The stack pointer is then incremented by one to point to locations 10 and I I in anticipation of another CALL. Nesting of subroutines wihtin subroutines can continue up to 8 times without overflowing the stack.

If overflow does occur the deepest address stored (loca- tions 8 and 9) will be overwritten and lost since the stack . pointer overflows from I I I to 000. It also underflows from

000 to I I I. .

The end of a subroutine. which is signalled by a return instruction (RET or RETR), causes the Stack Pointer to bl decremented and the contents of the resulting register pair to be transferred to the Program Counter.

2.7 Program Status Word

An 8-bit starus word which can be loaded to and from the accumulator exists called the Program Status Word (PSW). Figure 7 shows the information available in

1-6

MSB

SAVED IN STACK I

STACK POINTER

CY CARRY

AC AUXILIARY CARRY FO FLAG 0

BS REGISTER BANK SELECT

,

So LSB

Figure 7. Program Status Word (PSW) The upper four bits of PSW are stored in the Program Counter Stack with every call to subroutine or interrupt vector and are optionally restored upon return with the RETR instruction. The RET return instruction does not update PSW.

The PSW bit definitions are as follows:

Bits 0-2: Stack Pointer bits (So' S,. S2) Bit 3: Not used (" I" level when read) Bit 4:

Bit 5:

Bit 6:

Bit 7:

Working Register Bank Switch Bit (BS)

a

a

I = Bank I

Flag a bit (Fa) user controlled flag which can be complemented or cleared, and tested with the conditional jump instruction JFO.

Auxiliary Carry (AC) carry bit generated by an ADD instruction. and used by the decimal adjust instruction DA A .

Carry (CY) carry flag which indicates that the previous operation has resulted in overflow of the accumulator.

2.8 Conditional Branch Logic

The conditional branch logic within the processsor enables several conditions internal and external to the processor to be tested by the users program. By using the conditional jump instruction the conditions that are listed in Table lean effect a change in the sequence of the program execution.

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Table 1

Jump Conditions

Device Testable (Jump On)

not all

Accumulator All zeros, zero~

Accumulator Bit - I

Carry Flag 0 I

User Flags (FO, FI)

-

Timer Overflow Flag

-

Test Inputs (TO,-'D) 0 I

Interrupt Input (INT) 0

-

2.9 Interrupt

An interrupt sequence is initiated by applying a low "0"

level input to the INT pin. Interrupt is level triggered and active low to allow "WIRE DRing" of several interrupt sources at the input pin. Figure 8 shows the interrupt logic of the 8048AH. The Interrupt line is sampled every instruction cycle and when detected causes a "call to subroutine" at location 3 in program memory as soon as all cycles of the current instruction are complete. On 2- cycle instructions the interrupt line is sampled on the 2nd cycle only. INT must be held low for at least 3 machine cycles to ensure proper interrupt operations. As in any CALL to subroutine,the Program Counter and Program Status word are saved in the stack. For a description of this operation see the previous section, Program Counter and Stack. Program Memory location 3 usually contains an unconditional jump to an interrupt service subroutine elsewhere in program memory. The end of an interrupt service subroutine is signalled by the execution of a Return and Restore Status instruction RETR. The interrupt system is single level in that once an interrupt is detected all further interrupt requests are ignored until execution of an RETR reenables the interrupt input logic. This occurs at the beginning of the second cycle of the RETR instruction.

This sequence holds true also for an internal interrupt generated by timer overflow. Jf an internal timer/counter generated interrupt and an external interrupt are detected at the same time, the external source will be recognized.

See the following Timer/Counter section for a description of timer interrupt. If needed, a second external interrupt can be created by enabling the timer/counter interrupt, loading FFH in the Counter (ones less t1Jan terminal count), and enabling the event counter mode. A "I" to

"0" transition on the TI input will then cause an interrupt vector to location 7.

INTERRUPT TIMING

The interrupt input may be enabled or disabled under Program Control using the EN I and DIS I instructions.

abled by the users program. An interrupt request must be removed before the RETR instruction is executed upon return from the service routine otherwise the processor will re-enter the service routine immediately. Many pe- ripheral devices prevent this situation by resetting their interrupt request line whenever the processor accesses (Reads or Writes) the peripherals data buffer register. If the interrupting device does not require access by the processor, one output line of the 8048AH may be des- ignated as an "interrupt acknowledge" which is activated by the service subroutine to reset the interrupt request.

The INT pin may also be tested using the conditional jump instruction IN!. This instruction may be used to detect the presence of a pending interrupt before interrupts are en- abled. If interrupt is left disabled, !NT may be used as another test input like TO and Tl.

2.10 Timer/Counter

The 8048AH contains a counter to aid the user in counting external events and generating accurate time delays with- out placing a burden on the processor for these functions.

In both modes the counter operation is the same, the only difference being the source of the input to the counter.

The timer/event counter is shown in Figure 9.

COUNTER

The 8-bit binary counter is presenable and readable with two MOV instructions which transfer the contents of the accumulator to the counter and vice versa. The counter content may be affected by Reset and should be initialized by software. The counter is stopped by a Reset or STOP TCNT instruction and remains stopped until started as a timer by a START T instruction or as an event counter by a START CNT instruction. Once started the counter will increment to this maximum count (FF) and overflow to zero continuing its count until stopped by a STOP TCNT instruction or Reset.

The increment from maximum count to zero (overflow) results in the setting of an overflow flag flip-flop and in the generation of an interrupt request. The state of the overflow flag is testable with the conditional jump instruc- tion JTF. The flag is reset by executing a JTF or by Reset.

The interrupt request is stored in a latch and then ORed with the external interrupt input INT. The timer interrupt may be enabled or disabled independently of external in- terrupt by the EN TCNTI and DIS TCNTI instructions.

If enabled, the counter overflow will cause a subroutine call to location 7 where the timer or counter service routine may be stored.

If timer and external interrupts occur simultaneously, the

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S

JTF

EXECUTED _ _ -r-" ... ~-+_~ R RESET---i---'

TIMER FLAG

bl~ER~LOW ---<>--1 S Q TIMER OVERFLOW TIMER INT FF

RECOGNIZED

EXECUTED } - - - l R

RESET

DIS TCNTI _ _ .._ ...

EXECUTED ~--~

RESET

INTcr---~

PIN

S

R

D TIMER

INT ENABLE

INT FF

CLK ALE-~-""

LAST CYCLE ~----~

OF INST.

EN I EXECUTED

DIS I EXECUTED

RESET - - - i - - - '

S INT ENABLE R

Q

a

a

Q

CONDITIONAL JUMP LOGIC

INTERRUPT CALL EXECUTED

CLR

D Q

CLK

a

S Q

INTERRUPT IN PROGRESS R

RESET RETR EXECUTED

FF

EXTERNAL INTERRUPT RECOGNIZED

TIMER INTERRUPT RECOGNIZED

1. WHEN INTERRUPT IN PROGRESS FLIP-FLOP IS SET ALL FURTHER INTERRUPTS ARE LOCKED OUT INDEPENDENT OF STATE OF EITHER INTERRUPT ENABLE FLIP-FLOP.

2. WHILE TIMER INTERRUPTS ARE DISABLED TIMER OVERFLOW flf WILL NOT STORE ANY OVERFLOW THAT OCCURS. TIMER FLAG WILL BE SET, HOWEVER.

Figure 8_ Interrupt Logic

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PRESCALER

XTAL 1 5 - 32

LOAD OR READ CLEARED ON START TIMER

START TIMER

JUMP ON TIMER FLAG

r---,

EDGE DETECTOR

COUNTER

o

STOPT

8 BITTIMERI EVENT COUNTER

OVERFLOW FLAG

ENABLE---.~ __ ~

INT

Figure 9. Timer/Event Counter location 3. Since the timer interrupt is latched it will re-

main pending until the external device is serviced and immediately be recognized upon return from the service routine. The pending timer interrupt is reset by the Call to location 7 or may be removed by executing a DIS TCNTI instruction.

AS AN EVENT COUNTER

Execution of a START CNT instruction connects the Tl input pin to the counter input and enables the counter.

The Tl input is sampled at the beginning of state 3 or in later MCS-48 devices in state time 4. Subsequent high to low transitions on TI will cause the counter to increment.

Tl must be-held low for at least I machine cycle to insure it won't be missed. The maximum rate at which the counter may be incremented is once per three instruction cycles (every 5.7 f.isec when using an 8 MHz crystal) -- there is no minimum frequency. Tl input must remain high for at least 1/5 machine cycle after each transition.

AS A TIMER

Eexcution of a START T instruction connects an internal clock to the counter input and enables the counter. The internal clock is derived bypassing the basic machine cycle clock through a -;- 32 prescaler. The prescaler is reset during the START T instruction. The resulting clock in- crements the counter every 32 machine cycles. Various delays from I to 256 counts can be obtained by presetting the counter and detecting overflow. Times longer than 256 counts may be achieved by accumulating multiple over- flows in a register under software control. For time res-

olution less than I count an external clock can be applied to the T 1 input and the counter operated in the event counter mode. ALE divided by 3 or more can serve as this external clock. Very small delays or "fine tuning"

of larger delays can be easily accomplished by software delay loops.

Often a serial link is desirable in an MCSA8 family mem- ber. Table 2 lists the timer counts and cycles needed for a specific baud rate given a crystal frequency.

2.11 Clock and Timing Circuits

Timing generation for the 8048AH is completely selfcon- tained with the exeception of a frequency reference which can be XT AL, ceramic resonator, or external clock source.

The Clock and Timing circuitry can be divided into the following functional blocks.

OSCILLATOR

The on-board oscillator is a high gain parallel resonant circuit with a frequency range of I to 11 MHz. The X I external pin is the input to the amplifier stage while X2 is the output. A crystal or ceramic resonator connected between Xl and X2 provides the feedback and phase shift required for oscillation. If an accurate frequency reference is not required, ceramic resonator may be used in place of the crystal.

For accurate clocking, a crystal should be used. An ex- ternally generated clock may also be applied to XI-X2 as the frequency source. See the data sheet for more information.

SINGLE COMPONENT MCSS!-48 SYSTEM

Table 2. Baud Rate Generation

Frequency Tcy TO Prr(1/5 Tcy} Timer Prescaler

(MHz) (32 TCY)

4 3.75/-LS 750ns 120/-LS

6 2.50/-LS 500ns 80/-LS

8 1.88/-LS 375ns 60.2/-LS

11 1.36/-LS 275ns 43.5/-LS

Baud 4 MHz 6 MHz 8 MHz 11 MHz

Rate Timer Counts + Timer Counts + Timer Counts + Timer Counts + Instr. Cycles Instr. Cycles Instr. Cycles Instr. Cycles 110 75 + 24 Cycles 113 + 20 Cycles 151 + 3 Cycles 208 + 28 Cycles

.01% Error .01% Error .01% Error .01% Error 300 27 + 24 Cycles 41 + 21 Cycles 55 + 13 Cycles 76 + 18 Cycles.

.1% Error .03% Error .01% Error .04% Error

1200 6 + 30 Cycles 10 + 13 Cycles 12 + 27 Cycles 19 + 4 Cycles .1% Error .1% Error .06% Error .12% Error 1800 . 4 + 20 Cycles 6 + 30 Cycles 9 + 7 Cycles 12 +24 Cycles

.1% Error .1% Error .17% Error .12% Error 2400 3 + 15 Cycles 5 + 6 Cycles 6 + 24 Cycles 9+ 18 Cycles

.1% Error .4% Error .29% Error .12% Error 4800 1 + 23 Cycles 2 + 19 Cycles 3 + 14 Cycles 4 + 25 Cycles

1.0% Error~ .4% Error

STATE COUNTER

The output of the oscillator is divided by 3 in the State Counter to create a clock which defines the state times of the machine (CLK). CLK can be made available on the external pin TO by executing an ENTO CLK instruction.

The output of CLK on TO is disabled by Reset of the processor.

CYCLE COUNTER

ClK is then divided by 5 in the Cycle Counter to pro- vide a clock which defines a machine cycle consisting of 5 machine states as shown in Figure 10. Figure 11 shows the different internal operations as divided into the machine states. This clock is called Address latch Enable (ALE) because of its function in MCS-48 sys- tems with external memory. It is provided continuous- lyon the ALE output pin.

2.12 Reset

The reset input provides a means for .initialization for the processor. This Schmitt-trigger input has an internal pull- up device which in combination with an external 1 JL fd capacitor provides an internal reset pulse of sufficient length to guarantee all circuitry is reset, as shown in Figure 12. If the reset pulse is generated externally the RESET pin must be held -low for at least 10 milliseconds after the

1·10

.74% Error .12% Error

power supply is within tolerance.Only 5 machine cycles (6.8 JLS @ II MHz) are required if power is already on and the oscillator has stabilized. ALE and PSEN (if EA

= 1) are active while in Reset.

Reset perfonns the following fundions:

1) Sets program counter to zero.

2) Sets stack pointer to zero.

3) Selects register bank O.

4) Selects memory bank O.

5) Sets BUS to high impedance state (except when EA

=

6) Sets Ports I and 2to input mode.

7) Disables interrupts (timer and external).

8) Stops timer.

9) Clears timer flag.

. 10) Clears FO and Fl.

11) Disables clock output from TO.