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High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

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Academic year: 2021

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Fig. 3 An example of architectural description specifying a Freescale QorIQ P4080 platform
Figure 6a depicts the CAL JPEG encoder where actors are at the encoding DCT, quantization and zigzag scan (Q-ZZ), variable-length encoding (Huffman) and the bitstream organizer and writer which generates a 4:2:0 JPEG file (Syntax Writer)
Figure 7 represents the MPEG-4 Simple Profile.
Table 4 Speedup of the MPEG-4 decoder running on an X86 quad- quad-core and on a PowerPC e500 8-quad-core processors

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