Principles of Computer ArchitectureAppendix B: Reduction of DigitalLogic

Principles of Computer Architecture

Miles Murdocca and Vincent Heuring

Appendix B: Reduction of Digital

Logic

B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction of Two-Level Expressions

B.3 State Reduction

Reduction (Simplification) of Boolean Expressions

• It is usually possible to simplify the canonical SOP (or POS) forms.

• A smaller Boolean equation generally translates to a lower gate count in the target circuit.

• We cover three methods: algebraic reduction, Karnaugh map re-

duction, and tabular (Quine-McCluskey) reduction.

• Compared with the AND-OR circuit for the unreduced majority

function, the inverter for C has been eliminated, one AND gate has been eliminated, and one AND gate has only two inputs instead of three inputs. Can the function by reduced further? How do we go about it?

F

A B C

F

A B C

A B C A B C

A B C

A B C

Unreduced

Reduced

The Algebraic Method

• Consider the majority function, F. We apply the algebraic method to reduce F to its minimal two-level form:

F ABC AB C ABC ABC F ABC AB C AB C C F ABC AB C AB

F ABC AB C AB

F ABC AB C AB ABC F ABC AC B B AB F ABC AC AB

F ABC AC AB ABC F BC

= + + +

= + + +

= + +

= + +

= + + +

= + + +

= + +

= + + +

=

( )

( )

( )

Distributive Property Complement Property Identity Property

Idempotence Identity Property Complement and Identity

Idempotence 1

(( A A ) AC AB F BC AC AB

+ + +

= + +

Distributive

Complement and Identity

• This majority circuit is functionally equivalent to the previous ma- jority circuit, but this one is in its minimal two-level form:

F

A B C

Karnaugh Maps: Venn Diagram Rep- resentation of Majority Function

• Each distinct region in the “Universe” represents a minterm.

• This diagram can be transformed into a Karnaugh Map.

ABC

ABC’ AB’C’ AB’C

A’BC

A’BC’ A’B’C

A’B’C’ B

A

C

K-Map for Majority Function

• Place a “1” in each cell that corresponds to that minterm.

• Cells on the outer edge of the map “wrap around”

A B C F

Minterm Index

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

0 1 2 3 4 5 6 7

1

0

0-side 1-side

0

A balance tips to the left or right depending on whether

there are more 0’s or 1’s.

00 01 11 10

0

1 AB C

1

1

1 1

Adjacency Groupings for Majority Function

• F = BC + AC + AB

00 01 11 10

0

1 AB C

1

1

1 1

Minimized AND-OR Majority Circuit

• F = BC + AC + AB

• The K-map approach yields the same minimal two-level form as the algebraic approach.

F

A B C

K-Map Groupings

• Minimal grouping is on the left, non-minimal (but logically equiva- lent) grouping is on the right.

• To obtain minimal grouping, create smallest groups first.

00 01 11

1 01

11

1 1

AB 10

1 CD

10 00

01 11

01

11 CD 10

10 00

AB 00 1

1

1

1

1

2

3

4

1 1 1

1 1

1

1

1

2

4 1 5

F = A B C + A C D + A B C + A C D

F = B D + A B C + A C D + A B C + A C D

3

K-Map Corners are Logically Adjacent

00 01 11

1

1

1 01

11

1

1 1

1 1 AB 10

1 CD

00

10

F = B C D + B D + A B

K-Maps and Don’t Cares

• There can be more than one minimal grouping, as a result of don’t cares.

00 01 11

1 01

11

1 1

AB 10 1 CD

10 d

00 d

F = B C D + B D

01 11

1 01

11

1 1

10 1

CD

10 d

00 d

AB 00

F = A B D + B D

1 1

Five-Variable K-Map

• Visualize two 4-variable K-maps stacked one on top of the other;

groupings are made in three dimensional cubes.

01 11

001 011 CDE 10

010 000

AB 00

01 11

101 111 CDE 10

110 100

AB 00

1 1

1 1

1 1

1 1

1 1

1 1

F = A C D E + A B D E + B E

Six-Variable K-Map

• Visualize four 4-variable K-maps stacked one on top of the other;

groupings are made in three dimensional cubes.

001 011

001 011 DEF 010

010 000

000 ABC

001 011

101 111 DEF 010

110 100

000 ABC

101 111

001 011 DEF 110

010 000

100 ABC

101 111

101 111 DEF 110

110 100

100 ABC 1

1 1

1

1

1 1

1

G = B C E F + A B D E

• K-Kap Reduction results in a reduced two-level circuit (that is, AND followed by OR. Inverters are not included in the two-level count). Algebraic reduction can result in multi-level circuits with even fewer logic gates and fewer inputs to the logic gates.

M

A B C

Map-Entered Variables

• An example of a K-map with a map-entered variable D.

00 01 11 10

0

1 AB C

1 1

D

F = B C + A B C D

Two Map-Entered Variables

• A K-map with two map-entered variables D and E.

• F = BC + ACD + BE + ABCE

00 01 11 10

0

1 AB C

1 1

D d E E

Truth Table with Don’t Cares

• A truth table repre- sentation of a single function with don’t cares.

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C D 0

0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B

d 1 0 1 0 1 1 1 0 0 1 d 0 1 0 d F 0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

A

• Tabular reduction be- gins by grouping

minterms for which F is nonzero according to the number of 1’s in each minterm. Don’t cares are considered to be nonzero.

• The next step forms a consensus (the logical form of a cross prod- uct) between each pair of adjacent groups for all terms that differ in only one variable.

0 0 1 0 1 1 1 1 0 1

0 1 1 1 0 0 1 1 1 1 C D 0

0 0 1 1 0 1 0 1 1 B 0 0 0 0 0 1 0 1 1 1 A

√

√

√

√

√

√

√

√

√

√

0 _ 0 1 1 _ 0 1 1 1 1 _

_ 1 1 1 1 1 1 _ _ 1 1 1 C D 0

0 _ _ 0 1 1 1 0 1 _ 1 B 0 0 0 0 _ 0 _ 0 1 _ 1 1 A

*

√

√

√

√

√

√

*

*

√

√

√

_ 1 _

1 1 1 C D _

_ 1 B 0 _ _ A

*

*

* Initial setup After first

reduction

After second reduction

(a)

(b)

(c)

Table of Choice

• The prime implicants form a set that completely covers the func- tion, although not necessarily minimally.

• A table of choice is used to obtain a minimal cover set.

0 0 1 0 _ _

0 1 0 _ _ 1

0 1 1 _ 1 _

_ _ _ 1 1 1

0001 0011 0101 0110 0111 1010 1101 Minterms

Prime Implicants

√

√

√

√

√ √ √ √

√ √

√ √ √

*

*

*

Reduced Table of Choice

• In a reduced table of choice, the essential prime implicants and the minterms they cover are removed, producing the eligible set.

• F = ABC + ABC + BD + AD

0 0 _

0 _ _

0 _ 1

_ 1 1

0001 0011 Minterms Eligible

Set

√

√

Set 1 0 0 0 _ _ _ 1 1

Set 2 0 _ _ 1

X Y

Z √

√

Multiple Output Truth Table

• The power of tabular reduction comes into play for multiple func- tions, in which minterms can be shared among the functions.

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 B C

0 0 0 0 1 1 1 1 A

1 0 0 1 0 0 0 1 F ₀

0 1 0 1 1 0 1 1 F ₁

0 0 1 1 0 0 1 1 F ₂

m ₀

m ₁

m ₂

m ₃

m ₄

m ₅

m ₆

m ₇

Minterm

F ₀ (A,B,C) = ABC + BC

F ₁ (A,B,C) = AC + AC + BC F ₂ (A,B,C) = B

0 0 1 _ 1 _

0 _ _ 1 1 1

0 1 0 _ _ 1 Prime

Implicants

√

m ₀ m ₃ m ₇ m ₁ m ₃ m ₄ m ₆ m ₇ m ₂ m ₃ m ₆ m ₇ F ₀ (A,B,C) F ₁ (A,B,C) F ₂ (A,B,C) Min-

terms

F ₀ F ₁ F ₁ F ₂ F _1,2 F

√ √

√ √

√ √ √ √

√ √

√

√ √ √ √ √

*

*

*

*

*

√ √

Speed and Performance

• The speed of a digital system is governed by:

• the propagation delay through the logic gates and

• the propagation delay across interconnections.

• We will look at characterizing the delay for a logic gate, and a

method of reducing circuit depth using function decomposition.

Propagation Delay for a NOT Gate

• (From Hamacher et. al. 1990)

+5V

0V

+5V

0V

10%

90%

Transition Time

90%

10%

50%

(2.5V)

50%

(2.5V) Propagation Delay

Transition Time

Time

A NOT gate input changes from 1 to 0

The NOT gate output changes from 0 to 1

(Fall Time)

(Latency)

(Rise Time)

MUX Decomposition

A C

F

0000 0001 0010 0011

B

0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

D 1 0

0 1 0 1 1 0 0 1 0 0 0 0

0 1 A D

F 00

01 10 11 B C

00 01 10 11

B C 00 01 10 11 1

0 0 1

0 1 1 0

0 B C + B C

B C + B C

F ABCD AB C D AB CD ABC D ABCD AB C D ABCD B C BC AD B C BC AD B C BC

( )

( ) ( ) ( )

= + + + + +

= + + + + +

OR-Gate Decomposition

• Fanin affects circuit depth.

A + B + C + D A BCD

Associative law of Boolean algebra:

Initial high fan-in gate

Balanced tree

A B CD

(A + B) + (C + D)

A B C D

A + B + C + D = (A + B ) + (C + D) (( A + B ) + C) + D

State Reduction

• Description of state machine M ₀ to be reduced.

X

0 1

A C/0 E/1

Present state

Input

B C D E

D/0 E/1

C/1 B/0

C/1 A/0

A/0 C/1

• A next state tree for M ₀ .

(ABCDE)

(CDA)(CC) (ABE)(CD)

(CC)(C)(CC) (AB)(E)(CD)*

(BA)(E)(BB) (AB)(E)(CD)

(DC)(A)(DD) (AB)(E)(CD)

(EE)(C)(EE) (AB)(E)(CD)*

(CC)(C)(CC) (AB)(E)(AA) (AB)(E)(CD)

(CD)(A)(CC) (EE)(C)(EE)

(EEC)(BA) (ABE)(CD)

(AA)(C)(DC) (AB)(E)(CD)

(CC)(B)(EE) (AB)(E)(CD)*

(CC)(C)(CC) (EE)(B)(AB)

0 1

0 1

0 1

0 1

0 1

0 1

0 1

Next states

Distinguished states

Reduced State Table

• A reduced state table for machine M ₁ .

X

0 1

AB: A' B'/0 C'/1

Current state Input

CD: B' E: C'

B'/1 A'/0

A'/0 B'/1

The State Assignment Problem

• Two state assignments for machine M ₂ .

P.S.

Input X

0 1

A B/1 A/1

B C/0 D/1

C C/0 D/0

D B/1 A/0

Machine M ₂

Input X

0 1

A: 00 01/1 00/1 B: 01 10/0 11/1 C: 10 10/0 11/0 D: 11 01/1 00/0

State assignment SA ₀

S ₀ S ₁

Input X

0 1

A: 00 01/1 00/1 B: 01 11/0 10/1 C: 11 11/0 10/0 D: 10 01/1 00/0

State assignment SA ₁

S ₀ S ₁

State Assignment SA ₀

• Boolean equations for machine M ₂ using state assignment SA ₀ .

01 11

1

10 X

0 00 S ₀ S ₁

1 1

1 1

01 11

1

10 0 00 1

1

1 1

X S ₀ S ₁

01 11

1

10 0

00 1 1

1 1

X S ₀ S ₁

S ₀ = S ₀ S ₁ + S ₀ S ₁ Z = S ₀ S ₁ + S ₀ X + S ₀ S ₁ X

S ₁ = S ₀ S ₁ X + S ₀ S ₁ X

+ S ₀ S ₁ X + S ₀ S ₁ X

State Assignment SA ₁

• Boolean equations for machine M ₂ using state assignment SA ₁ .

01 11

1

10 X

0 00 S ₀ S ₁

1 1

1 1

01 11

1

10 0 00 1 1

1 1 X S ₀ S ₁

01 11

1

10 00 X

1 1

1

1 S ₀ S ₁ 0

S ₁ = X

S ₀ = S ₁ Z = S ₁ X + S ₀ X

Sequence Detector State Transition Diagram

A

B

0/0

1/0

C

D

E

F

G

0/0

1/0

0/0

1/0

0/0

1/0 1/0

1/1 0/0

1/1

0/0

0/1 Input: 0 1 1 0 1 1 1 0 0

Output: 0 0 1 1 1 1 0 1 0

Time: 0 1 2 3 4 5 6 7 8

Sequence Detector State Table

X

0 1

A B/0 C/0

Present state Input

B C D E

D/0 E/0 F/0 G/0 D/0 E/0 F/0 G/1

F D/0 E/1

G F/1 G/0

Sequence Detector Reduced State Table

X

0 1

B'/0 C'/0 Present state

Input

B'/0 D'/0 E'/0 F'/0 E'/0 F'/1 B'/0 D'/1 E'/1 F'/0 A: A'

BD: B'

C: C'

E: D'

F: E'

G: F'

Sequence Detector State Assignment

X

0 1

A': 000 001/0 010/0 Present state

Input

B': 001 C': 010 D': 011 E': 100

001/0 011/0 100/0 101/0 100/0 101/1 001/0 011/1 F': 101 100/1 101/0

S

S

S

S

S

S

Z S

S

S

Z

Excitation Tables

• In addition to the D flip-flop, the S-R, J-K, and T flip-flops are used as delay elements in finite state machines.

• A Master-Slave J-K flip-flop is shown below.

Q J Q

CLK

J

Q Q

K

Circuit Symbol

K

• K-map re- duction of next state and output functions for sequence detector.

01 11 10 00 S

X

1 1 1 1

01 11 10 d

d d d 1

1 1 1 00

S

S

01 11 10 00 S

X

1 1

01 11 10 d

d d d

1 00

S

S

01 11 10 00 S

X

1

1 1

10 d

d d d 00

S

S

01 11 10 00 S

X

1 01 11 10

d d d d 1

1 00

S

S

01 11

S

= S

S

X + S

X + S

S

+ S

X

S

= S

S

X + S

S

X

1 1

1

Clocked T Flip-Flop

• Logic diagram and symbol for a T flip-flop.

J

Q Q

K

Circuit

Q Q

Symbol 1

T T

Sequence Detector

Circuit

CLK

D Q Q S₀

Z Q

D Q S₁

Q D

Q S₂

Excitation Tables

• Each table

shows the set- tings that must be applied at the inputs at time t in order to

change the out- puts at time t+1.

0 0 1 1

0 1 0 1

Q _t Q _t+1 S 0 1 0 0

R 0 0 1 0 S-R

flip-flop

0 0 1 1

0 1 0 1

Q _t Q _t+1 D 0 1 0 1 D

flip-flop

0 0 1 1

0 1 0 1

Q _t Q _t+1 J 0 1 d d

K d d 1 0 J-K

flip-flop

0 0 1 1

0 1 0 1

Q _t Q _t+1 T 0 1 1 0 T

flip-flop

Serial Adder

Serial Adder 0 1 1 0 0

0 1 1 1 0

1 1 0 1 0 X

Y

Z

C

C

4 3 2 1 0

4 3 2 1 0 Time (t)

Time (t)

A B

00/0 01/1

10/1

11/0

00/1

10/0 01/0

11/1 No carry

state Carry state

x

y

z

Present state (S

)

Input XY

00 01 10 11

A:0 0/0 0/1 0/1 1/0

Present state

Input XY

00 01 10 11

A A/0 A/1 A/1 B/0

B A/1 B/0 B/0 B/1

Next state Output

• State transi-

tion diagram,

state table,

and state as-

signment for

a serial adder.

Serial Adder Next-State Functions

• Truth table showing next-state functions for a serial adder for D, S-R, T, and J-K flip-flops. Shaded functions are used in the ex- ample.

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 Y S _t 0

0 0 0 1 1 1 1 X

0 0 0 1 0 1 1 1 D

0 0 0 0 0 0 1 0 S

0 1 0 0 0 0 0 0 R

0 d 0 d 0 d 1 d J

d 1 d 0 d 0 d 0 K 0

1 0 0 0 0 1 0 T

0 1 1 0 1 0 0 1 Z

Present

State (Set) (Reset)

CLK

Q J X

Y

Q

X Y

Y

X

Z S X K

Y

D Flip-Flop Serial Adder Circuit

CLK

Q D X

Y

Q

X Y

Y

X

Z S X

Y

Majority Finite State Machine

A

0/0

B

C

D

E

F

0/1 G

1/0

1/1 0/0

1/0

0/0 1/0

0/0 1/0 0/0 1/1

0/0 1/1

Input: 0 1 1 1 0 0 1 0 1 Output: 0 0 1 0 0 0 0 0 1 Time: 0 1 2 3 4 5 6 7 8 Input History _ _ _

0 _ _

1 _ _

0 0 _ 0 1 _

1 0 _

1 1 _

Majority FSM State Table

• (a) State table for majority FSM; (b) partitioning; (c) reduced state table.

X

0 1

A B/0 C/0 P.S.

Input

B C D E

D/0 E/0 F/0 G/0 A/0 A/0 A/0 A/1 F A/0 A/1 G A/1 A/1

(a)

X

0 1

B'/0 C'/0 D'/0 E'/0 E'/0 F'/0 A'/0 A'/0 A'/0 A'/1 A'/1 A'/

1 A: A'

B: B' C: C' D: D' EF: E'

G: F'

(c) P ₀ = (ABCDEFG)

P ₁ = (ABCD)(EF)(G) P ₂ = (AD)(B)(C)(EF)(G) P ₃ = (A)(B)(C)(D)(EF)(G) P ₄ = (A)(B)(C)(D)(EF)(G) √

P.S.

Input

(b)

Majority FSM State Assignment

• (a) State assignment for reduced majority FSM using D flip-flops;

and (b) using T flip-flops.

X

0 1

A': 000 001/0 010/0 P.S.

Input

B': 001 C': 010 D': 011 E': 100

011/0 100/0 100/0 101/0 000/0 000/0 000/0 000/1 F': 101 000/1 000/1

S

S

S

S

S

S

Z S

S

S

Z

X

0 1

A': 000 001/0 010/0 P.S.

Input

B': 001 C': 010 D': 011 E': 100

000/0 010/0 110/0 111/0 011/0 011/0 100/0 100/1 F': 101 101/1 101/1

S

S

S

T

T

T

Z T

T

T

Z

(a) (b)

Majority FSM Circuit

Q D

Q T

2

000 001 010 011 100 101 110 111 0

0 1 0 0 0 0 0

Q D

Q T

1

000 001 010 011 100 101 110 111 x

1 1 0 0 0 0

Q D

Q T

0

000 001 010 011 100 101 110 111 x

1 0 1 0 0

000 001 010 011 100 101 110 111 0

0 0 0 x 1 0 0

Z x0

xx

CLK

x