1-bit Adder

Arithmetic and Logic Unit (ALU)

Designing an Adder

Traditional circuit design: truth table approach

Cost/Speed tradeoff:

• n-bit adder: truth table with 2n inputs, 2²ⁿrows→fast circuit (theoretically), but very costly

• n 1-bit adders: cheap but slow

• Tradeoff: n 1-bit adders and additional circuitry to speed up computation

+

……….…

+

……….…

+

……… +

1 0 0 1 1

1 0 1 0 1

0 1 0 0 1

1 0 1 1 0

1 1 1 1 1 0 0 0 r

1 1 0 S

0 0 1

0 1 0

0 0 0

R y x

1 0 1 1

1 1 0 S

0 0 1

0 1 0

0 0 0

R y x

1-bit Adder

+ y x

r S R Half Adder

Full Adder R

S

r x y

R = x.y + r.(x+y)

S = r’(x’.y + x.y’) + r.(x.y + x’.y’)=r ⊕x⊕y

0 1 1

1 1 0

⊕

0 1

1 0

0 0

y x

Exclusive OR

= x.y + r.(x⊕y)

x⊕y x

y

n-bit Addition/Substraction

Substraction:

•X-Y = X + (-Y) = X + Y’ + 1

•c = 1 →no additional adder

Bottleneck: carry

propagation

+ S₁ r₁

+ S₀ r₀ +

S₂ r₂ +

x₁ x₀

x₂ x₃

S₃ r₃

r₀ r₁ r₂ r₃

s₀ s₁ s₂ s₃ r₃ Z

y₀ y₁ y₂ y₃ + Y

x₀ x₁ x₂ x₃ X

y₁ y₀

y₂ y₃

c c=0: addition

c=1: substraction

y₀c y₁c

y₂c y₃c

A Simple 1-bit ALU

Elementary operations:

• ADD, AND, NOT

ALU: Arithmetic and Logic Unit Multiplexor:

select among several inputs

MUX

m₀ m₁ m₂ m₃

m c₁c₀

m3

1 1

m2

m1

m0

m

0 1

1 0

0 0

c0

c1

MUX

ALU c₁

c₀

y x

r

+

R

1 d 1

NOT AND ADD ALU

0 1

1 0

0 0

c0

c1

n-bits ALU

n 1-bit ALUs

Embryo of instruction set:

n n X Y

n Z

1 d 1

NOT AND ADD ALU

0 1

1 0

0 0

c0

c1

Overflow

Detect overflow in twos-complement ?

0 0 1

1 1 0 1 -5

1 0 1 0 + 5

0 1 1 0 6

0 0 0 1

1 0 1 0 1 5

1 0 0 1 + -7

0 0 1 1 -4

Overflow

Overflow signal S_overflow (1=overflow)

Overflow in twos-complement:

• x ≤0, y ≥0 →no overflow possible

• x ≥0, y ≥0:

Overflow: Z=X+Y (twos-complement) Z > 2^n-1-1, et 0 ≤X ≤2^n-1-1, 0 ≤Y ≤2^n-1-

1

⇒2^n-1-1 < Z ≤2ⁿ-2

⇒In twos-complement, negative numbers coded in [2^n-1;2ⁿ-1]

⇒Z is negative

• x ≤0, y ≤0: same; in case of overflow, Z is positive

→overflow detection criterion

0 0 1 1

0 1 0 1

1 0 0 1

1 1 1 0

0 1 1 1 0 0 0 zn-1

0 0 0 Soverflow

0 1

1 0

0 0

yn-1

xn-1

1 '

1 '

1 '

1 1

1. −. − −. −. −

− +

= n n n n n n

overflow x y z x y z

S

Overflow

Action upon overflow ? Several solutions:

• Stop program (TRAP)

Example: MIPS R3000;

• Raise a signaling bit such as S_overflow

Example: Intel x86, Sun SPARC;

• Do nothing

Example: using C on a Sun SPARC 32-bits

-2147483648 (-2³¹) →2147483647 (2³¹-1)

01110111001101011001010000000000 + 01110111001101011001010000000000 --- 11101110011010110010100000000000

Génération de la retenue Propagation de la retenue

Speeding Up Carry Propagation

+ +

+ +

+ +

+ +

3 3 3

2 2 2

1 1

1 0 1 0 1

1 0 1 1

0 0

0 0 0 0 0

. . .

) . .(

) . (

. .

) .(

) . (

P c G r

P c G r

P c G

p p c p g g

p r g r

p c g

y x c y x r

+

= +

= +

=

+ +

= +

= +

=

⊕ +

=

S (t=t_r+2) r (t=t_r) x,y (t=0) x,y (t=0)

p,g (t=2) r_4k-1(t=t_r4k-1)

r4k,4k+1,4k+2,4k+3(t=max(t_r4k-1+2,4)) t_r3=4 t_r7=6

t_r7=16 t_r3=8

Carry Look Ahead r₀ r₁ r₂ p3g3

r₃

CLA

p2g2 p1g1 p0g0

p7g7 p6g6 p5g5 p4g4

c

p₀g₀ c

Speeding Up Carry Propagation

n

= number of bits

CLA: O(n).

Tree structure:

O(log₂n).

p_i= x_i

⊕

⊕

p₁g₁ p₂g₂ p₃g₃

x₃y₃ x₂y₂ x₁y₁ x₀y₀

a₂,b₂

b₂+b₁.a₂ a₁,b₁

a₁.a₂

a,b r

b + a.r

r1

r3

p2

s₂

p₀

s₀ p₁

s₁ p3

s₃

P_2..1=p₂p₁ G_2..1=g₂+p₂g₁

r2

r₀=g₀+p₀c

Speeding Up Carry Propagation

n=16.

Brent-Kung.

CLA: 5 steps (pgand 4 CLA) to propagate carry

Tree: 7 steps (pgand 6 PG operators) Starting with

32 bits, tree (8) faster than CLA (9)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

15 c

Speeding Up Carry Propagation

n=16

Han-Carlson.

Cost/Perform ance tradeoff

Itanium:

•64 bits,

•0,18µm,

•482 ps for one addition

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

15 c