New Digital Predistortion Design Based on Mixed-Signal Cartesian Feedback Training for 3G Homodyne Transmitter
W. Sanaa1,2, B. Le Gal2, D. Dallet2, C. Rebai1, N. Deltimple2, D. Belot3, E. Kerherve2
1CIRTA’COM Research Laboratory, SUP’COM, University of Carthage, Tunisia
2Université de Bordeaux, Laboratoire IMS, CNRS UMR 5218, IPB, 351 crs de la Libération, 33405 Talence, France
3STMicroelectronics, 850 rue Jean Monnet, F-38926 Crolles Cedex, France
Abstract— in this paper, a smart adaptive RF power amplifier linearization technique is presented. We invest a Mixed-Signal Cartesian Feedback Loop design to train an embedded Random Access Memory in order to overcome digital-stage latency and bandwidth limitation. The new design consists of a traditional analog stage including filters, I/Q modulator, feedback I/Q demodulator and an improved digital stage which adjusts the phase misalignment around the loop and updates the RAM. We used a not fully-pipelined CORDIC design for the digital part in order to improve the system operating frequency without increasing the silicon surface area. We implemented this design for the UMTS standard using ASIC 65nm low power technology. We reached 230 MHz with system power consumption less than 6 mw which is better than a fully analog system (8.8 mW).
Keywords— RAM, Mixed-Signal Loop, Predistortion, CORDIC, ASIC
I. INTRODUCTION
Wide band communication standards need efficient modulation techniques to achieve high data rate communications and to increase spectral efficiency [1]. These energy-efficient modulations require linear processing and, consequently, a high linear radio-frequency (RF) power amplifier (PA). Nevertheless, power efficiency is maximized when the PA operates at its non-linear region. In a transmitter the use of a linear power amplifier needs more power consumption than the use of a linearization structure.
According to that, the best solution consists in designing a moderately linear PA then employing an adequate linearization technique. Thus, the amplifier operates as close as possible to saturation, maximizing the power efficiency while the linearization system maximizes the spectral efficiency. A various linearization solutions (analog and digital) are proposed to reduce the effects of nonlinearities like Predistortion and Feedback techniques [2]. Static digital predistortion is a well-known technique that implements the mathematical model of the power amplifier as a static look-up table (LUT). The weakness of this approach is that it is not robust to temperature variations and aging effects. Cartesian feedback loop (CFB), which forms an alternative feedback
technique, seems to be an attractive solution for two reasons:
it automatically compensates all process variations and its linearization process is applied to all components in the loop [3]. Despite the excellent efficiency of this method, and the natural robustness to variations in the PA model, the bandwidth of Cartesian transmitters is severely limited by the group delay in the transmit path and latency in the feedback path.
In this paper, authors present an adaptive digital predistortion approach that combines the best of both solutions, employing a random access memory supporting the PA model and, which, is continuously updated by the mixed- signal Cartesian FeedBack loop. This smart technique was applied to an UMTS transmitter. A homodyne architecture avoiding the use of external filter has been chosen. Using mixed-signal CFB provides flexibility, higher integration and less area occupation than in a fully analog architecture as proved in our previous work [4].
We organize this paper as follows. In section II, the mixed-signal feedback architecture and its limitation is described. Section III highlights the new power amplifier linearization architecture and the design of its components.
Simulations and synthesis results are presented in section IV, and a conclusion is drawn in section V.
II. MIXED-SIGNAL CARTESIAN LOOP
The idea of using CFB Loop to linearize power amplifiers has been discussed at least as early as the 1970's [5]. It is called Cartesian feedback because the feedback is based on the Cartesian coordinates of the baseband symbols, I and Q, as opposed to the polar coordinates. Several studies have shown that the forward and the feedback paths are not completely decoupled. Hence, I and Q components, related to the feedback path, undergo an angular deflection which severely affects system stability and loop’s linearization capability. Why for, a phase-corrector stage is added in the feedback path in order to guarantee that CFB operates correctly [6]. As mentioned in [4], implementing the phase- corrector stage in the digital domain has many advantages like reducing cost, ensuring low power consumption and offering better linearization results.
This research is funded by laboratoire de l’intégration du matériau au système, IMS, and STMicroelectronics
978-1-4673-0859-5/12/$31.00 ©2012 IEEE
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φ
φ
Figure 1: Mixed-signal Cartesian Loop design
Figure 1 depicts such a typical system made up of both analog and digital building blocks. Quadrature baseband signals (I, Q) are directly up-converted to RF frequency by mixers associated with a local oscillator. The resulting RF signal is then strengthened by the power amplifier. In the feedback path, the PA output is attenuated, down-converted and filtered out. After converting analog signals to the digital domain using analog to digital converters (ADC), a phase adjustment is applied to IFB and QFB signals in order to cancel phase deviation around the loop. Feedback signals are subtracted from the input quadrature components to provide return signals Ipd and Qpd. These signals include the forward path non linearity. By loop effect, forward path non linearity is subtracted from input signals. Thus, input I/Q components are predistorted to provide a linearized PA output. Despite the various advantages provided by this solution, designing such method for high operating frequency systems and wideband transmitters remains a hard task due to two factors:
• Delays generated by components.
• Latency caused by the digital stage.
The Mixed-Signal CFB’s principal limitation is its inability to handle wideband signals. In practice, it is difficult to make a feedback system respond to signal-envelope changes much greater than several MHz, because of the delay (Δts) of the amplifier and associated signal-processing components. As mentioned in [7] the signal bandwidth (BWs) must satisfy:
1
ts
4*
BW
sΔ ≤
(1) To avoid distortions generated on adjacent channels and to improve ACPR, the linearization bandwidth should be wider than the signal bandwidth. According to that the loop delay must satisfy:
1 1 4*1.5* 6*
ts
s s
BW BW
Δ ≤ ≤
(2) This equation can be fulfilled when the loop’s bandwidth doesn’t exceed 5 MHz. However, for wideband systems like long term evolution systems (LTE) CFB linearization become an impossible task.Another limitation of Mixed-Signal CFB is the important latency caused by the digital stage especially when a high operating frequency is used. In fact, the HDL design of such
system necessitates the use of a pipelined architecture which allows reaching the desired frequency 220 MHz and increases the stage latency by , ,k the number of added registers as depicted in Figure 2. Therefore, for a stage inputx n( ), the corresponded output value will bey n k( + )and noty n( ). To remedy this problem, the digital stage must operate at k*220 MHz in order to generates the good output stage. However, increasing frequency necessitates much more registers and this will inevitably increase latency. Using an iterative architecture reduces the system latency but limits the system frequency.
To push and encourage industry to implement Mixed- signal CFB for wideband transmitters, we build on the previous work [4] by improving the Mixed-CFB’s architecture so as to benefit from its advantages and remedy its drawbacks. What we propose in the next section is a smart design that compensates latency in the digital stage and makes the feedback and forward paths independent in order to support much more delay in the loop.
III. OPEN MIXED-SIGNAL LOOP DESIGN
Figure.2 illustrates our open Mixed-Signal loop predistortion concept. The Cartesian Random Access Memory (RAM) directly transforms a pulse-shaped baseband constellation into a predistorted constellation, which cancels out the PA nonlinearity. Feedback path is used only for RAM training and updating. We applied this design to an UMTS homodyne transmitter. The transmitter is always made up of two paths composed of analog and digital blocks as mentioned in Figure 3. In the forward path, the pulse-shaped baseband (I, Q) components are copied in FIFOI and FIFOQ before feeding the Cartesian RAM so as to generate a new predistorted couple (Ipd, Qpd). These predistorted components are directly up-converted to the appropriate RF frequency (1.95 GHz). Then, the RF signal is strengthened by the power amplifier before driving the antenna. We note that distortions are compensated thanks to the existing values in the RAM.
Thereby, the forward path comes to be completely independent from the feedback path and the signal bandwidth supported by the CFB becomes dependent to the characteristics of the used filters. In the feedback path, the PA’s output is attenuated, down converted, filtered out then sampled by the analog to digital converter (ADC). The resulting components (Ifb, Qfb) are digitally processed in order to compensate variations and phase distortions. Then, the processed components are used to improve the system’s linearization capability by updating the RAM.
Figure 2: Latency and operating frequency relationship
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Figure 3. Open mixed-signal loop design Beyond the basic predistortion and phase correction concepts,
there are some design issues that must be well-thought-out when putting together the overall system. The fact that the feedback path no longer needs to be fast permits some simplification, and some optimization to improve the digital- stage‘s accuracy. The precision of all values in the RAM is improved as well as the transmitter operates. In the following sections, we treat these issues in detail.
A. Open mixed-signal loop digital-stage design
As described above, the digital stage is designed to ensure three tasks:
1) Phase estimation
The phase estimation consists of performing atan function of both couples (I, Q) and (Ifb, Qfb) then subtracting the two obtained values in order to generate the angular distortion.
Subtraction result must be standardized to avoid a possible overflow due to phase computing.
A scrupulous study depending on different hardware implementations of atan function has shown that adopting a not fully pipelined CORDIC design allows reaching high frequencies and has a small computation complexity [4, 8, 9].
We note that nine iterations were needed to perform an accuracy of 1°.
2) Vector rotation
Unlike the atan function which uses the CORDIC’s vectoring mode, this function uses the CORDIC’s rotation mode to perform vector rotation. The rotation is computed using a serial of specific incremental angles whose sum is equal to the desired angle of rotation.
Figure 4: The phase corrector design
Each elementary rotation is performed only by using a shift- and -add operations. The same pipelined architecture was used. Nine iterations were required to perform accuracy.
3) Cartesian RAM updating
At this level, we can calculate precisely the whole latency in our digital stage. Eleven cycles were needed to obtain the first coherent result related to the first system entry. That’s why predistortion, as mentioned in figure 3, must be done based on the eleventh couple (I, Q) stored in the FIFOI and FIFOQ lookup tables. The predistortion result must be stored into the Cartesian RAM. Indexing the RAM by the same couple (I, Q) used in subtraction is compulsory to ensure high linearization results. We note that, as mentioned in [10], updating the RAM by averaging the old and the new values is a smart way to reduce noise caused by the feedback path. However, this technique will increase the time needed for convergence.
B. Feedpath design issues and specifications
The fact that the forward path is becoming independent permits us to enhance the computing accuracy of the feedback path. In fact, we can reduce the operating frequency of the ADC in the feedback path so as to enhance its resolution. Using fourteen or sixteen bits will increase the system accuracy and will improve the precision of the Cartesian RAM. Moreover, reducing the operating frequency of the feedback path will decrease the number of iterations of the CORDIC algorithm. So we can save both energy and surface area of the whole circuit.
The size of the designed RAM depends in essence on the dynamic range of I and Q components after pulse shaping. In our case we have found that 16 bits, 8 bits for each component, are sufficient to index the RAM. Hence, the whole occupied memory is 1.6 Mbits.
IV. SYSTEM VALIDATION AND ASIC SYNTHESIS RESULTS In this section, we present our system validation results;
mainly, we focused on the validation of the digital stage. All given results were obtained by performing ASIC synthesis and VHDL simulations. We regard testing the analog part and
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realizing the transmitter on a SoC as perspectives for our ongoing research.
Digital stage simulation results are shown in Figure 5. For simplification, we have initialized the random memory with zeros instead of the forward (I, Q) values. Then, we have applied two types of sinusoidal signals; the first one is composed of five identical periods (i.e. each period is composed of the same samples) and the second one is also composed of five periods but samples values change from one period to another. The first signal allows us to verify that our HDL design functions correctly and the second signal will show the training RAM capability.
As depicted in Figure 5, the simple line signal corresponds to the in phase components issued from the baseband stage. The discontinuous line signal corresponds to theoretical predistortion process computed by MATLAB. The signal plotted with circles, Ipd1, shows HDL result based on the first sinusoidal signal type. We note that our digital stage operates correctly with precision equal to 0,1%. When processing the first values, the delivered signal is not predistorted, Ipd and Qpd are equal to zero, but the RAM is being updated by the computed values. Hence, the other values are all well predistorted. The signal plotted only with dotes, Ipd2, corresponds to HDL simulation result using the second sinusoidal signal type. Even though the signal seems to be correctly predistorted, some values remains not predistorted because the first values used in the first period are not sufficient to update the RAM. To remedy to this problem we can initialize the RAM with theoretical values based on the mathematical model of the power amplifier.
Table I summarizes ASIC synthesis results on 65nm low power technology (CORE65LPSVT) in terms of area occupation and energy consumption for our considered solution. ASIC synthesis of the proposed architecture shows that a frequency of 230 MHz is reached with lower power consumption than the fully analog solution.
0 100 200 300 400 500 600
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
Samples
Amplitude
System validation of the predistortion design
I VHDL Ipd2 VHDL Ipd1 MATLAB Ipd
Figure 5: System validation of the new predistortion design Table 1: ASIC synthesis results
Table 2: ASIC synthesis results Occupation Power
consumption Memory size Our design
232 MHz 2.05 mm2 25,86 uW/MHz
1.6 (Mbits) These results can be improved by reducing the operating frequency in the feedback path. Accordingly, the number of used registers in the digital stage will decrease and so the dynamic power consumption. Moreover, making the feedback path operates only when necessary by disabling the digital stage allows reducing power consumption.
The most important issue provided by this design is its ability to overcome bandwidth limitation thanks to the independence of the two paths of the loop.
V. CONCLUSION
The problem of phase alignment and bandwidth limitation has stood as the primary barrier to the widespread use of the Cartesian feedback technique. In this paper an enhanced Mixed-Cartesian feedback loop predistortion design for microwave power amplifier has been presented and evaluated for the UMTS standard. This mixed-signal architecture is less energy than the full analog architecture. Moreover the proposed design allows the linearity constraints on the subtractor, on the phase corrector and also on the DACs to be relaxed.
REFERENCES
[1] 3GPP, “User Equipment (UE) radio transmission and reception,”
Universal Mobile telecommunications System (UMTS), vol. TS 125 101, V9.4.0, 2010.
[2] Steve Cripps, “RF Power Amplifiers for Wireless Communications“, Chapter 14, ARTECH HOUSE,INC 2006.
[3] Claire Tassin, Patrice Garcia, Jean-Baptiste Bégueret, Romaric Toupé, Yann Deval, Didier Belot,” A Mixed-Signal Cartesian feedback linearization system for a ZERO-IF WCDMA transmitter handset IC”, Research in Microelectronics and electronics, IEEE, December 2005 [4] W.Sanaa, N Delaunay, B. Le Gal, D. Dallet, C. Rebai, N. Deltimple, D.
Belot, E. Kerherve, “ Design of a Mixed-Signal Cartesian FeedBack Loop for a Low Power Zero-IF WCDMA Transmitter”, LASCAS 2012, in press.
[5] B. Razavi. RF Microelectronics. Prentice-Hall, Inc., Upper Saddle River, NJ, 1998.
[6] Joel L. Dawson and Thomas H. Lee, “Automatic Phase Alignment for a Fully Integrated Cartesian Feedback Power Amplifier System,” IEEE, Solid-State Circuits, vol. 38, pp. 2269-2279, 2003.
[7] A. Katz, “Linearization: reducing distortion in power amplifiers”, IEEE, Microwave magazine, p.9, December 2001.
[8] Jack E. Volder, “The CORDIC Trigonometric Computing Technique,”
IRE Trans, Electronic Computing, vol. EC-8, pp. 330-334, 1959.
[9] R. Andraka, “A survey of CORDIC algorithms for FPGA based computers”, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, pages 192-200, New York, NY, USA, 1998. ACM Press.
[10] SungWon Chung, Jack W. Holloway, and Joel L. Dawson,” Open-Loop Digital Predistortion Using Cartesian Feedback for Adaptive RF Power Amplifier Linearization”, Microwave symposium, 2007.
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