Mixed Cartesian feedback for Zero-IF WCDMA transmitter
N. Delaunay•M. Abid• B. Le Gal• D. Dallet• C. Rebai•N. Deltimple• D. Belot• E. Kerherve
Received: 17 August 2011 / Revised: 17 July 2012 / Accepted: 23 July 2012 / Published online: 23 August 2012 Springer Science+Business Media, LLC 2012
Abstract In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a classic WCDMA zero-intermediate frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB) loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feed- back I/Q demodulator, and a digital stage adjusting the phase rotation around the loop. The whole system con- sumes 500 and 2.94 mW, respectively, for the analog and the digital part. System level simulation gave a maximum improvement of 35 dBc at 5 MHz from the carrier for the W-CDMA signal.
Keywords Cartesian feedback loopWCDMA transmitterArchitecture matching algorithm CMOS 65 nm technology
1 Introduction
Abundant research focuses on the improvement of power amplifier’s (PAs) linearity performances [1]. Linearization techniques remain an important and hot domain of research
with universal mobile telecommunications system (UMTS) standards [2] and the future 4G standards called long term evolution (LTE). These standards have been created for high data rate wireless communication and use a non- constant envelope modulation like hybrid phase shift key- ing (HSPK) for UMTS. As a consequence, both linearity and efficiency performances in the design of a cellular PA are becoming harder to reach. A useful parameter to observe the complexity of a modulation is the power average to peak ratio (PAPR). The PAPR of GSM, UMTS, and LTE are 3 dB, from 3.5 to 7 dB, and from 5 to 8.5 dB, respectively.
Hence, designing a linear and efficiency PA is a difficult task regarding to the PAPR value. Those modulations require high linear radio-frequency (RF) PA, whereas, power efficiency is maximized when the PA operates at its non-linear region. The trend consists of designing a mod- erately linear PA and employing a linearization technique.
The amplifier operates as close as possible to the saturation region, maximizing its power efficiency, and the lineari- zation system maximizes the spectral efficiency in this near-saturated region. Many methods (analog or digital) are proposed to reduce the effects of nonlinearities like pre- distortion [3], post-distortion [4], feedback [4], and feed- forward [3] techniques. Among these, Cartesian feedback (CFB), which forms an alternative feedback technique, is an attractive option for two mains reasons: first it auto- matically compensates all process variations; and secondly its linearization process is applied to all components in the loop.
Nevertheless, historically the technique has suffered from practical shortcoming since a phase corrector is mandatory to compensate delay around the loop. In addi- tion, the analog implementation of phase corrector is dif- ficult to realize in order to have an automatic correction. In N. Delaunay (&)M. AbidB. Le GalD. Dallet
N. DeltimpleE. Kerherve
Laboratoire IMS, CNRS UMR 5218, IPB, Universite´ de Bordeaux, 351 crs de la Libe´ration, 33405 Talence, France e-mail: delaunay.nicolas@gmail.com
N. DelaunayD. Belot
STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France
M. AbidC. Rebai
CIRTA’COM Research Laboratory, SUP’COM, University of 7th November at Carthage, Tunis, Tunisia
DOI 10.1007/s10470-012-9937-1
this paper, we propose a new solution to overcome this problem with a digital phase rotator approach. Due to the increasing demand of cost reduction, a zero-intermediate frequency (Zero-IF) architecture avoiding the use of external filter has been chosen. Moreover, CFB with a Zero-IF architecture brings few additional components for an efficient linearity improvement. Full-analog CFB architecture has been studied and realized [4]. There are some drawbacks associated with this solution such as high area and high power consumption. Delegating the phase rotation adjustment processing to a digital stage provide flexibility, higher integration and less area size than in full- analog architecture.
We propose to apply the analog and digital CFB tech- nique to an integrated transmitter in a 65 nm CMOS technology from STMicroelectronics. This linearization technique has already been realized with discrete compo- nents or III–V technology for base-station [5,6], but for the best of our knowledge, a CMOS transmitter using CFB has not been reported in the literature for mobile handset. Thus, the main challenge is to make a single chip on 65 nm CMOS technology with the main objective to increase performances of the transmitter for UMTS standard com- munication in a low cost technology.
Specifications and precautions to design the CFB is presented in the Sect.2. Analog and digital implementation on Silicon is detailed on the Sect. 3. Section4 proposes simulations results of the analog and the digital part in order to present the whole system simulation results.
2 CFB transmitter
Linearity of PAs is of major importance for the scientific community during these last years. This trend has increased with the emergence of standards using non-constant envelope modulations [5, 7, 8]. Moreover, keep a good linearity for a PA becomes increasingly complex with the size of the transistors decreasing. Indeed, if we do not take care of the linearity of PAs, send data via the transmitter may contain errors. Using CFB allows enhancing trans- mitter performances.
2.1 Linearization technique
Proposed linearization technique architecture based on a digital CFB implementation is shown in Fig.1. Quadrature baseband signals are directly up-converted to 1.95 GHz.
The RF signal is then amplified thanks to the PA.
In the feedback path, the PA output is attenuated, down- converted to the baseband quadrature signals and filtered out. After the analog to digital convertor (ADC), a phase adjustment is applied to IFB and QFB in order to cancel
phase rotation around the loop. Feedback signals are sub- tracted from the input to provide return signals Ireturn and Qreturn. These signals include the forward path non linear- ity. By loop effect, forward path non linearity is subtracted from input signals. Thus, input I/Q signals are pre-distorted to provide a linearized PA output.
Using the CFB has several advantages among which the flexibility is the most important. Indeed, the CFB corrects nonlinearities of any type of PA. This system, due to the feedback path, works directly on the signal, according to the behavior changes of the PA (bias, temperature, aging etc.), and the changes related to the PA upstream compo- nents of the direct path. Another important advantage is the possibility to implement the system on a single chip. In order to make the integration easier, and thus reduce the cost of production, some parts of the system can be implemented on the digital domain (e.g., phase correction).
And last one, the CFB is able to correct not only the amplitude distortions (AM/AM) but also the phase distor- tions (AM/PM). The main drawback concerns the stability of the system. This is why a carefully study of the CBF stability has been done.
2.2 CFB digital part and design consideration
Delay in the loop can lead to error vector magnitude (EVM) degradation and instability [4]. The baseband loop filters in the feedback path leads to delay and symbol rotation when feedbacks signal and input signal are sub- tracted. Phase variations are canceled by using the circular transformation given in (1), wherehis the phase correction value (Fig.2).
IC QC
¼ cosð Þh sinð Þh sinð Þh cosð Þh
IFB QFB
ð1Þ his estimated by comparing forward and feedback paths phases. Two architectures are evaluated for the circular Fig. 1 Zero-IF WCDMA transmitter with digital CFB loop
transform implementation. The first architecture uses lookup tables (LUT) and multiplier resource which is a costly solution in terms of area occupation. The main advantage of this solution is to do not introduce a large delay into the loop.
The second architecture uses a coordinate rotation digital computer (CORDIC) algorithm [9] which requires less area than multiplier based architecture when the data path exceeds 10 bits. Pipelined CORDIC architecture introduces latency in the loop, which revealed a tradeoff between area occupation, latency and throughput. A fine- tuning of the implementation variables will lead to an optimal solution. Delay in the loop is limited by period of WCDMA data (Tchip) for stability consideration [4]. The input/output of the digital stage are synchronized with the DAC and ADC frequency specifications, set to 242 MHz (Fig.1).
2.3 CFB analog part and design consideration
The analog part remains important because it gives non- linearity behavior of the system. In fact, the analog part has a crucial role on the linearity’s improvement of the trans- mitter because it receives corrected signals. Moreover, due to the feedback path, the analog part has to send the non- linear signals taking from the output of the PA. It remains very important to take care of the linearity of this feedback path. In fact, this path will introduce non desire distortions on the digital part. This non linear behavior has as a con- sequence to make the correction of the digital part harder.
Design consideration has been done in CMOS 65 nm from STMicroelectronics [14]. The realization of this part has to focus on the improvement of the linearity, decreasing the power consumption and the die area.
3 CFB implementation
The linearized transmitter depicted in Fig.3is made up of both analog and digital building blocks. Indeed, as decreasing the cost of production remains an important objective for industry, operations of subtraction and phase alignment were moved in the digital domain.
3.1 Digital implementation
As previously mentioned, the main task of the digital stage is to perform the vector rotation. The angle of rotation, which is defined as the difference between the phase of the direct channel I/Q and the return channel IFB/QFBone, has to be estimated. Therefore, the digital CFB architecture decomposed in three blocks as shown in Fig.2.
• Phase estimation,
• Vector rotation,
• Subtraction.
3.1.1 Phase estimation
Regarding phase estimation, it is very important to notice that phase subtraction must be done ‘‘modulo 2p’’ to keep the same range of variation of the angle applied to the next block (vector rotation). It implies that the phase estimation block is divided into two sub functional units: ‘atan’ unit for the direct and feedback phase estimations, and ‘mod- ulo-2p’ unit.
3.1.1.1 ‘atan’ Based architecture Different implementa- tions of the digital ‘atan’ function are proposed in the lit- erature [10] and one of them, which is the most trivial, uses a look up table (LUT) [11]. This solution seems to be over- sized and very tasty in Silicon area consumption comparing with other alternatives implementation such as the COR- DIC algorithm. A comparative study regarding imple- mentation of these two solutions is presented, as well as output performances.
LUT based architecture
LUT based solution, illustrated in Fig.3, consists first making the division of ‘‘Q’’ to ‘‘I’’ and then going through an interpolation table (LUT) where all the values of the
‘atan’ function are stored. LUT length is function of the phase estimation precision so ‘‘1’’ deg precision leads to 1,440 bits ROM. Thanks to symmetry properties of ‘atan’
function, size of the LUT can be limited to the half [6].
To implement the division, multitude algorithm solu- tions can be considered. The so-called algorithm Fig. 2 Digital stage architecture
Fig. 3 LUT based solution
‘‘Restoring Division Algorithm’’ [12] is used since it allows a very adequate operating frequency. This algorithm requires that the operands are positive and the numerator greater than or equal to the denominator. Additional developments can process negative operands. Division by
‘‘0’’ results in saturation at the maximum value.
CORDIC based architecture
Another alternative for ‘atan’ function implementation is to use an iterative algorithm called ‘‘CORDIC algo- rithm’’ [9]. CORDIC based solution does not require division as shown in Fig.4. It takes as input the two coordinates of the vector and provides its phase [9]. This algorithm was designed to use adder and subtractor resources only as presented in Fig.5. It was subsequently improved in order to calculate trigonometric functions (exp., cos, sin, atan…) and this is done by configuring wisely its inputs variables.
Implementation of CORDIC algorithm can be done with several ways [13]. A tradeoff between throughput and design area is required by application as specified in Sect.
2. The small computation complexity of the algorithm and its modularity give considerable flexibility in the
implementation phases. That is why a full-pipelined architecture was chosen.
3.1.1.2 ‘‘Modulo’’ function implementation Due to the extensive range of phase variation, the subtraction can overflow and so, it should be standardized to be adequate for the input of the next stage. It consists in calculating modulo 2pfunction. The idea is to calculate the remainder of the Euclidean division of the wanted angle by K*2p. A smart implementation of this function can be described by an algorithm organized as follows. First, a sign test is realized to benefit from the symmetry property of this function. Then the angle value is tested if it has exceeded a full circle turn. If so, 2pis subtracted from it and the test continues, else this value is retained as the output result.
3.1.2 Vector rotation
3.1.2.1 LUT and multipliers solution This first solution consists in following precisely the mathematical function of the rotation vector as it is described in Eq. (1). Figure3 shows an implementation example. Thanks to the phase cosine and sinus values, the complex multiplication can be done. To compute those coefficients, LUTs that contains the values of sine and cosine function can be used. An optimization step uses a single LUT (e.g., cosine) and trigonometric relationships to move from one function to another. A second optimization step exploits quarter wave symmetry.
3.1.2.2 CORDIC based solution As shown in Fig. 4, the CORDIC algorithm can perform a vector rotation without multiplier resources allocation. A simple initialization on his entries, with the vector on which we rotate: namely IFB/QFB and the angle to perform.
3.1.3 Subtraction
Subtraction is simple enough to be implemented in digital.
Indeed, it is necessary to calculate the twos’ complement of the second operand and then use an adder.
3.2 Analog implementation 3.2.1 Building block description
Components making the transmitter (converters, mixers, attenuator, filters, and PA) have been designed in CMOS 65 nm technology. All the active circuits have been mea- sured and the results are illustrated in Table1.
The design of the PA has been realized and measured by STEricsson. At 1.95 GHz, the power gain of the PA is equal to 24 dB. It offers a saturation power of 27 dBm with Fig. 4 CORDIC based solution
Fig. 5 CORDIC example implementation
an output compression point (OCP1) of 21 dBm shown in Fig.6. These large signal characteristics fulfill the W-CDMA standard—27 dBm for the Class 2, 24 dBm for the class 3 and 21 dBm for the class 1—in terms of output power and operating frequency. General infor- mation of the PA and other components are summarized in Table1.
With this table, a 2.7 mm2 analog core (without con- verters) areas can be targeted without PAD ring, consum- ing 868 mW with 75 % coming from the PA.
3.2.2 Whole analog part
The whole analog circuit is shown in Fig.7. The matching of PA is external and will be include on the PCB. The circuit has a die area of 292 mm2, local oscillators for the up and down conversion are also external.
4 System validation results
Digital blocks have been developed in hardware descriptive language (HDL) with ModelSim. Analog blocks have been designed in CMOS 65 nm technology with Agilent software First, simulations have been per- formed for each blocks. Then whole system level sim- ulations can be realized in order to validate the overall architecture.
Figures8 and9 depict the output spectrum of the PA with and without CFB technique for a same output power.
The Fig.9 exhibits clearly a decreasing of the distortions on the adjacent channels due to CFB loop. The ACPR receives an improvement of 35 dB at 5 MHz from the carrier. In fact comparing with the mask defined by the standard UMTS, the output spectrum for a Zero-IF archi- tecture is out of specifications, in opposite with the output spectrum of the CFB loop.
Table 1 Measurement results of analog and mixt components
Circuits Architecture Relevant measures Consumption Core area
DAC: 12 bits Current steering Bandwidth 80 MHz @Fs=242 MHz Analog part: 26 mW 0.476 mm2(with PADs) Digital part: 2.5 mW
Active filter Butterworth 2nd order Cutoff frequency: 7 MHz Gain: 14 dB 20.5 mW 0.129 mm2
Active mixer Gilbert cell Gain: 16 dB; Psat: 10 dBm 63.3 mW 0.103lm2
Power amplifier Double cascoded class AB Gain: 24 dB; Psat: 27 dBm; OCP1: 21 dBm 658 mW 2 mm2 Attenuator Resistive structure Gain:-6 to-20 dB (simulated) 1.25 mW 0.004 e-3 mm2 Passive mixer Ring structure Gain:-4 dB; output noise: 5 nV ffiffiffiffiffiffi
pHz
None 132 e-6 mm2
ADC: 12 bits Parallel pipeline Bandwidth: 162 MHz @Fs: 324 MHz Analog part: 100 mW \0.3 mm2 Digital part: 1 mW
Gain and Pout
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
-24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 Pin SMA (dBm)
dB/dBm
Pout SMA Pgain
Fig. 6 Gain and output power of the power amplifier
Fig. 7 Die area of the analog part in CMOS 65 nm technology
4.1 Digital implementation results
To validate the digital stage, we compared results obtained by floating simulation on Matlabwith those provided by HDL on ModelSim.
Figure10 shows results of the phase alignment stage simulation. Note that the impact of the resolution (number of bits chosen) ensures the convergence. The algorithm begins to track the desired value with acceptable accuracy after certain latency fixed by the number of internal reg- isters. We also note that the algorithm oscillates around the solution when the values are close to ‘‘0’’. To respect the real-time constraint, the circuit is synthesized at 242 MHz defined converters of the transmitter.
Table2 summarizes ASIC synthesis results on 65 nm technology (CORE65LPLVT1.00V) in terms of area and energy consumption for our two considered solutions (CORDIC and LUT). Two power types are presented: the dynamic power which depends on throughput and the leakage power whose consumption is constant.
LUT based solution consumes less energy in compari- son with the CORDIC one with almost likely surface occupation; therefore it is more adequate for our applica- tion. Nevertheless, hybrid architecture could be considered Fig. 8 Output spectrum without CFB
Fig. 9 Output spectrum with CFB loop
Fig. 10 Outputs stage simulation
Table 2 ASIC synthesis results
CORDIC LUT
Phase estimation Area 6,656lm2 4,480lm2 Dynamic power 1.01 mW 0.46 mW Leakage power 2.95lW 2.09lW
Rotation Area 9,477lm2 14,935lm2
Dynamic power 1.4 mW 1.19 mW Leakage power 4.17lW 5.72lW
Subtraction Area 613.6lm2
Dynamic power 0.098 mW Leakage power 0.277lW
Whole solution Area 23,402lm2 24,461lm2 Dynamic power 3.77 mW 2.94 mW Leakage power 10.35lW 10.24lW
Fig. 11 ACPR at 5 MHz from the carrier with and without linearization
by combining the LUT solution for the phase estimation bloc and the CORDIC one for the vector rotation bloc. It is important to notify that the proposed solution consume three time less energy than the full-analog one; 2.94 mW for our solution compared to 8.8 mW in the case of full- analog architecture [4].
4.2 Analog simulation results
As we said before, all building blocks making the linear- ized transmitter had been designed in CMOS 65 nm tech- nology, and had been characterized stand-alone using ADS software.
As a result we can observe that the ACPR at 5 MHz from the carrier for UMTS standard must be less than -33 dBc, as explained in Sect. 2. To illustrate it, the Fig.11shows the evolution of the ACPR according to the output power of the PA.
The Fig.11 shows the improvement with and without linearization technique. The curve of the open loop (in green) represents simulations of the analog part realized and explained in Sects.2.2and2.3. We can observe non-linearities given by the direct path (up-mixer and the PA). The curve of the closed-loop (in purple) has been done with ADS software, according performances given by each blocks, and making, by consequence, a whole simulation. The CFB transmitter shows an improvement of the output power at the limit given by the W-CDMA standard. Using this linearization technique, the transmitter has an output power improved by 12 dB and has a maximum improvement of 35 dB.
Another important parameter to evaluate the linearity is the EVM. Input and output constellations of the PA are presented in Fig.12: on the left figure we can see the non- linearity of the signal at the input of the transmitter, whereas the constellation on the right shows that the non linearity are compensated at the output of the PA. Indeed, the signals added to the non linearity given by the direct path of the transmitter result in a linear signal or spectrum.
5 Conclusion
The problem of phase alignment has stood as the primary barrier to the widespread use of the CFB technique. In this paper a CFB direct conversion transmitter with digital processing has been presented and evaluated for a Zero-IF WCDMA transmitter. This mixed-signal architecture allows the linearity constraints on the subtraction, on the phase corrector and also on the DACs to be relaxed.
Moreover, the analog part of the transmitter using the CFB technique shows a significant improvement of the output power. This result can lead designer to focus on the satura- tion power of the PA while the CFB deals with the linearity.
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N. Delaunay was born in Rennes, France, in 1983. He received the M.S. degree in microelectronics from the Sci- ences University of Bordeaux, France, in 2007. He is currently working as a Ph.D. student in microtechnology with the Uni- versity of Bordeaux and STMi- croelectronics, France, since 2007. He is doing his Ph.D. work at both, the Laboratory of Bor- deaux (IMS), France and STMi- croelectronics, Crolles, France.
His main research focuses on the linearity of power amplifier for wireless applications.
M. Abidreceived the Telecom- munications Engineering degree from Higher School of Commu- nications of Tunis (SUP’COM–
Tunisia) in 2010. He was at IMS Laboratory, University of Bor- deaux–Institut Polytechnique Bordeaux (France 2010–2011) for training in the advanced data converters team. He is currently a Masters’ student and researcher at CIRTA’COM research labora- tory at SUP’COM. His main research activities focus on digital signal circuit design and signal processing. His interests include also microcontrollers based platform design.
B. Le Galwas born in 1979, in Lorient France. He received his Ph.D. degree in information and engineering sciences and tech- nologies from the Universite´ de Bretagne Sud, Lorient, France, in 2005 and the DEA (M.S. Degree) in Electronics in 2002. He is cur- rently an Associate Professor in the IMS Laboratory, ENSEIRB-
MATMECA Engineering
School, Talence, France. His research focuses on system design, high-level synthesis such as High-Level Synthesis (HLS), SoCs design methodologies, and Application Specific Instruction Pro- cessors (ASIP) for signal and video processing applications.
D. Dallet (M’95) received the Ph.D. degree in electrical engi- neering from the University of Bordeaux, Talence, France in 1995. He is currently a Full Pro- fessor with the IMS Laboratory, University of Bordeaux–Institut Polytechnique Bordeaux, Ecole Nationale Supe´rieure d’Electro- nique, Informatique Te´le´com- munications, Mathe´matiques et Me´canique de Bordeaux (IPB ENSEIRB-MATMECA). His main research activities, carried- out at the IMS laboratory, focus on mixed-signal circuit design and testing, digital and analog signal processing, and programmable devices’ applications. His interests include also digital design and its application in BIST structures for the characterization of embedded A/D converters.
C. Rebaireceived the Electrical Engineering degree from National Engineering School of Sfax (ENIS–Tunisia) in 1999 with honors, the M.S. and Ph.D.
degrees of Microelectronic sci- ences from University of Bor- deaux (France), in 2000 and 2002, respectively, and the Habilitation degree in communication and information technologies from Higher School of Communica- tions (SUP’COM–Tunisia) in 2009. He was at IMS institute (France) from 1999 to 2002 as member of technical staff in the advanced data converters team. He was a visiting researcher at ST-Microelectronics (Grenoble-France) from 2002 to 2003. Since 2004, he has been with Electronics, Physics, and Propa- gation Department of SUP’COM where he is a Full Professor and the Head of Department. From 2005, he is founding member of CIR- TA’COM research laboratory at SUP’COM, managing the software radio team and working on mixed-signal design for wireless communi- cations applications, with special emphasis on software radio system and circuit’s design. Since 2004, he is a senior technical manager of inter- national R&D program for power line communication for smart grid program funded by Analog Devices Inc., (USA). His research led to over 70 publications.
N. Deltimplereceived the Ph.D.
degree in Electrical Engineering from the University of Bordeaux, France, in 2005. She is currently an Associate Professor at the Electronic Engineering School of Bordeaux (ENSEIRB-MATME- CA), a school of the Polytechnic Institute of Bordeaux. Her main research activities, carried-out at the IMS laboratory, the Labora- tory of Integration, from Materi- als to Systems of the University of Bordeaux, are in the domain of analog, radiofrequency, and mm- wave integrated circuits on the power amplifier design in CMOS and BiCMOS technology. Dr. Deltimple is currently a member of the IEEE International wireless Symposium (IWS) Technical Program Committee and IEEE NEWCAS Steering Committee and has been involved in the organization of several international conferences in the domain of circuit and system design.
D. Belot received the ‘‘D.U.T Electronique’’ degree from the
‘‘Institute Universitaire de Tech- nologie’’ of Grenoble, Grenoble France in 1982, and the M.S.
degree from the ‘‘Ecole Nationale Superieure d’Electronique et de Radioelectricite de Grenoble’’, Grenoble France in 1991. In 1983, he joined the Bipolar Device Characterization and Modelisation group, Thomson Semiconductor. In 1986, he joined Thomson ‘‘Etude et Fab- rication de Circuits Integres Speciaux’’, where he was involved with digital CMOS design. In 1988, he
was involved with the design of high speed ECL/CML data communi- cation ICs at STMicroelectronics. In 1996 he moves to the Radio Fre- quency design. From 1999 to 2005 he managed an RF-Analog design group which has developed WPAN and 3G transceivers in BiCMOS and CMOS processes. Presently he manages the Minatec Advanced R&D Analog RF team which develops new solutions for early RF and mmW standards for STMicroelectronics, Crolles & Minatec Grenoble, France.
E. Kerhervereceived the Ph.D.
degree in Electrical Engineering from University of Bordeaux, France in 1994. He joined ENS- EIRB-MATMECA and the IMS Laboratory in 1996, where he is currently Professor in Microelec- tronics and Microwave applica- tions. His main areas of research are the design of RF, microwave, and millimeter-wave circuits (power amplifiers and filters) in silicon GaAs and GaN technolo- gies. He is or was involved in several European projects (Medea?UPPERMOST, Medea?QSTREAM, Catrene PANAMA, FP6 MOBILIS, ENIAC MIRANDELA), to develop silicon RF/mmW power amplifiers and BAW duplexer. He has authored or co-authored more than 190 technical papers in this field, and was awarded 22 patents.
He has organized seven RFIC and EuMC workshops on advanced silicon technologies for radiofrequency and millimeter-wave applications. He is involved in the technical program committees of various international conferences (ICECS, IMOC, NEWCAS, EuMIC, SBCCI, LASCAS) and he was the general co-chair of the International IEEE ICECS’ 2006 and IEEE NEWCAS’ 2011 conferences. He is co-editor of Special Issues for IEEE-ICECS’ 2006, IEEE-ICECS’ 2007, IEEE-LASCAS 2010. He was 2 years associate editor of IEEE Transactions on Circuits and Systems II (TCAS II). He is IEEE senior member and member of the IEEE-CAS, IEEE-MTT and IEEE SSCS societies.
