VHDL Coding

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RTL HARDWARE DESIGN USING VHDL

Coding for Efficiency, Portability, and Scalability

PONG P. ^CHU

Cleveland State University

A JOHN WlLEY & SONS, INC., PUBLICATION

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RTL HARDWARE DESIGN

USING VHDL

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~ ~~ ~ ~~ ~

RTL HARDWARE DESIGN USING VHDL

Coding for Efficiency, Portability, and Scalability

PONG P. ^CHU

Cleveland State University

A JOHN WlLEY & SONS, INC., PUBLICATION

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Published by John Wiley & Sons, Inc., Hoboken, New Jersey.

Published simultaneously in Canada.

No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 1 11 River Street, Hoboken, NJ 07030, (201) 748-601 1, fax (201) 748-6008, or online at http://www.wiley.com/go/pennission.

Limit of LiabilityiDisclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages.

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Library of Congress Cataloging-in-Publication Data:

Chu, Pong P., 1959- p. cm.

RTL hardware design using VHDL I by Pong P. Chu.

Includes bibliographical references and index.

“A Wiley-Interscience publication.”

ISBN-13: 978-0-471-72092-8 (alk. paper) ISBN-10: 0-471-72092-5 (alk. paper)

1. Digital electronics-Data processing. 2. VHDL (Computer hardware description language). I. Title.

TK7868.D5C46 2006 621.39‘2-4~22

Printed in the United States of America.

2005054234

1 0 9 8 7 6 5 4 3 2 1

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To

my

parents Chia-Chi and Chi-Te, my wife Lee, and my daughter Patricia

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IEEE

stdlogic-1164 package Operators over an array data type

Data types in the

IEEE

numeric-std package The stdlogic-arith and related packages 3.6 Synthesis guidelines

53 56 58 60 64 65 65 66 66 66 4 Concurrent Signal Assignment Statements of VHDL 69

4.1 Combinational versus sequential circuits 4.2 Simple signal assignment statement

4.2.1 Syntax and examples 4.2.2 Conceptual implementation 4.2.3

4.3 Conditional signal assignment statement 4.3.1 Syntax and examples

4.3.2 Conceptual implementation 4.3.3 Detailed implementation examples 4.4.1 Syntax and examples

4.4.2 Conceptual implementation 4.4.3 Detailed implementation examples

Conditional signal assignment statement versus selected signal assignment statement

4.5.1 4.5.2

Signal assignment statement with a closed feedback loop

4.4 Selected signal assignment statement

4.5

Conversion between conditional signal assignment and selected signal assignment statements

Comparison between conditional signal assignment and selected signal assignment statements

4.6 Synthesis guidelines 4.7 Bibliographic notes

Problems

5 Sequential Statements of VHDL 5.1.1 Introduction

5.1.2 5.1.3

5.1 VHDL process

Process with a sensitivity list Process with a wait statement 5.2 Sequential signal assignment statement

69 70 70 70 71 72 72 76 78 85 85 88 90 93 93 94 95 95 95 97 97 97 98 99 100

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5.3 Variable assignment statement 5.4 If statement

5.4.1 Syntax and examples 5.4.2

5.4.3

5.4.4 Conceptual implementation

5.4.5 Cascading single-branched if statements 5.5.1 Syntax and examples

5.5.2

5.5.3 Incomplete signal assignment 5.5.4 Conceptual implementation 5.6.1 Syntax

5.6.2 Examples

5.6.3 Conceptual implementation

Comparison to a conditional signal assignment statement Incomplete branch and incomplete signal assignment

5.5 Case statement

Comparison to a selected signal assignment statement

5.6 Simple for loop statement

5.7 Synthesis of sequential statements 5.8 Synthesis guidelines

5.8.1

5.8.2 Guidelines for combinational circuits Problems

Guidelines for using sequential statements 5.9 Bibliographic notes

6 Synthesis Of VHDL Code

6.1 Fundamental limitations of EDA software 6.1.1 Computability

6.1.2 Computation complexity 6.1.3 Limitations of EDA software 6.2.1 Realization of logical operators 6.2.2 Realization of relational operators 6.2.3 Realization of addition operators 6.2.4

6.2.5

6.2.6 An example implementation Realization of VHDL data types 6.3.1

6.3.2 6.3.3

6.4.1 RT-level synthesis 6.4.2 Module generator 6.2 Realization of VHDL operators

Synthesis support for other operators

Realization of an operator with constant operands 6.3

Use of the std-logic data type Use and realization of the ’Z’ ^value Use of the

’-’

^value

6.4 VHDL synthesis flow

101 103 103 105 1 07 109 110 112 112 114 115 116 118 118 118 119 120 120 120 121 121 121 125 125 126 126 128 129 129 129 130 130 130 131 133 133 133 137 139 139 141

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CONTENTS Xi

6.4.3 Logic synthesis 6.4.4 Technology mapping 6.4.5

6.5.1 Propagation delay

6.5.2 Synthesis with timing constraints 6.5.3 Timing hazards

6.5.4

Effective use of synthesis software 6.5 Timing considerations

Delay-sensitive design and its dangers 6.6 Synthesis guidelines

6.7 Bibliographic notes Problems

7 Combinational Circuit Design: Practice Derivation of efficient HDL description 7.2.1 Sharing example 1

7.2.2 Sharing example 2 7.2.3 Sharing example 3 7.2.4 Sharing example 4 7.2.5 Summary

7.3.1 Addition-subtraction circuit

7.3.2 Signed-unsigned dual-mode comparator 7.3.3 Difference circuit

7.3.4 Full comparator

7.3.5 Three-function barrel shifter 7.4.1 Reduced-xor circuit

7.4.2 Reduced-xor-vector circuit 7.4.3 Tree priority encoder 7.4.4 Barrel shifter revisited 7.5.1 Gray code incrementor 7.5.2 Programmable priority encoder 7.5.3 Signed addition with status

7.5.4 Combinational adder-based multiplier 7.5.5 Hamming distance circuit

7.1

7.2 Operator sharing

7.3 Functionality sharing

7.4 Layout-related circuits

7.5 General circuits

7.6 Synthesis guidelines 7.7 Bibliographic notes

Problems

142 143 148 149 150 154 156 158 160 160 160 163 163 164 165 166 168 169 170 170 171 173 175 177 178 180 181 183 187 192 196 196 199 20 1 203 206 208 208 208

8 Sequential Circuit Design: Principle 21 3

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8.1

8.2

8.3 8.4

8.5

8.6

8.7

8.8 8.9

Overview of sequential circuits

8.1.1 Sequential versus combinational circuits 8.1.2 Basic memory elements

8.1.3 Synchronous versus asynchronous circuits Synchronous circuits

8.2.1 8.2.2

8.2.3 m e s of synchronous circuits Danger of synthesis that uses primitive gates Inference of basic memory elements 8.4.1 D latch

8.4.2 DFF 8.4.3 Register 8.4.4

RAM

Simple design examples 8.5.1 Other types of FFs 8.5.2 Shift register

8.5.3 Arbitrary-sequence counter 8.5.4 Binary counter

8.5.5 Decade counter

8.5.6 Programmable mod-rn counter

Timing analysis of a synchronous sequential circuit 8.6.1 Synchronized versus unsynchronized input 8.6.2 Setup time violation and maximal clock rate 8.6.3 Hold time violation

8.6.4 Output-related timing considerations 8.6.5 Input-related timing considerations Alternative one-segment coding style 8.7.1 Examples of one-segment code 8.7.2 Summary

Use of variables in sequential circuit description Synthesis of sequential circuits

Basic model of a synchronous circuit Synchronous circuits and design automation

8.10 Synthesis guidelines 8.1 1 Bibliographic notes

Problems

9 Sequential Circuit Design: Practice 9.1 Poor design practices and their remedies

9.1.1 Misuse of asynchronous signals 9.1.2 Misuse of gated clocks

9.1.3 Misuse of derived clocks 9.2 Counters

213 213 214 216 217 217 218 219 219 221 22 1 222 225 225 226 226 229 232 233 236 237 239 239 240 243 243 244 245 245 250 250 253 253 253 254

257 257 258 260 262 265

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CONTENTS Xiii

9.3

9.4

9.5 9.6

9.2.1 Gray counter 9.2.2 Ring counter 9.2.3

9.2.4 Decimal counter

9.2.5 Pulse width modulation circuit Registers as temporary storage 9.3.1 Register file

9.3.2 Register-based synchronous FIFO buffer 9.3.3 Register-based content addressable memory Pipelined design

9.4.1 Delay versus throughput 9.4.2 Overview on pipelined design 9.4.3

9.4.4

Synthesis guidelines Bibliographic notes Problems

LFSR (linear feedback shift register)

Adding pipeline to a combinational circuit Synthesis of pipelined circuits and retiming

10 Finite State Machine: Principle and Practice 10.1 Overview of FSMs

10.2 FSM representation 10.2.1 State diagram 10.2.2 ASM chart

10.3 Timing and performance of an FSM 10.3.1 Operation of a synchronous FSM 10.3.2 Performance of an FSM

10.3.3 Representative timing diagram 10.4 Moore machine versus Mealy machine

10.4.1 Edge detection circuit

10.4.2 Comparison of Moore output and Mealy output 10.5 VHDL description of an FSM

10.5.1 Multi-segment coding style 10.5.2 Two-segment coding style 10.5.3 Synchronous FSM initialization

10.5.4 One-segment coding style and its problem 10.5.5 Synthesis and optimization of FSM 10.6.1 Overview of state assignment 10.6.2 State assignment in VHDL 10.6.3 Handling the unused states

10.7.1 Buffering by clever state assignment 10.6 State assignment

10.7 Moore output buffering

265 266 269 272 275 276 276 279 287 293 294 294 297 307 308 309 309 31 3 3 13 314 315 317 32 1 321 324 325 325 326 328 329 330 333 335 336 337 338 338 339 341 342 342

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10.7.2 Look-ahead output circuit for Moore output 10.8 FSM design examples

10.8.1 Edge detection circuit 10.8.2 Arbiter

10.8.3 DRAM strobe generation circuit 10.8.4 Manchester encoding circuit 10.8.5 FSM-based binary counter Problems

11 Register Transfer Methodology: Principle 1 1.1 Introduction

11.1.1 Algorithm

1 1.1.2 Structural data flow implementation

1 1.1.3 Register transfer methodology

11.2.1 Basic RT operation

11.2.2 Multiple RT operations and data path 11.2.3 FSM as the control path

11.2.4 ASMDchart

1 1.2.5 Basic FSMD block diagram

11.3 FSMD design of a repetitive-addition multiplier

1 1.3.1 Converting an algorithm to an ASMD chart 11.3.2 Construction of the FSMD

11.3.3 Multi-segment VHDL description of an FSMD 11.3.4 Use of a register value in a decision box

11.3.5 Four- and two-segment VHDL descriptions of FSMD 11.3.6 One-segment coding style and its deficiency

11.4 Alternative design of a repetitive-addition multiplier 11.4.1 Resource sharing via FSMD

1 1.4.2 Mealy-controlled RT operations

11.5 Timing and performance analysis of FSMD

1 1.5.1 Maximal clock rate 11.5.2 Performance analysis 1 1.6 Sequential add-and-shift multiplier

1 1.6.1 Initial design 11.6.2 Refined design

1 1.6.3 Comparison of three ASMD designs 1 1.2 Overview of FSMD

11.7 Synthesis of FSMD 1 1.8 Synthesis guidelines 11.9 Bibliographic notes

Problems

344 348 348 353 358 363 367 369 369 373

373 373 374 375 376 376 378 379 379 380 382 382 385 386 3 89 39 1 394 396 396 400 404 404 407 407 408 412 417 417 418 418 418

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CONTENTS XV

12 Register Transfer Methodology: Practice 12.1 Introduction

12.2 One-shot pulse generator 12.2.1 FSM implementation

12.2.2 Regular sequential circuit implementation 12.2.3 Implementation using RT methodology 12.2.4 Comparison

12.3.1 Overview of SRAM

12.3.2 Block diagram of an

SRAM

controller 12.3.3 Control path of an SRAM controller 12.4 GCD circuit

12.5 UART ^receiver

12.6 Square-root approximation circuit 12.7 High-level synthesis

12.8 Bibliographic notes 12.3 SRAM controller

Problems

13 Hierarchical Design in VHDL 13.1

13.2

13.3 13.4

13.5

13.6

13.7

Introduction

13.1.1 Benefits of hierarchical design

13.1.2 VHDL constructs for hierarchical design Components

13.2.1 Component declaration 13.2.2 Component instantiation

13.2.3 Caveats in component instantiation Generics

Configuration 13.4.1 Introduction

13.4.2 Configuration declaration 13.4.3 Configuration specification

13.4.4 Component instantiation and configuration in VHDL 93 Other supporting constructs for a large system

13.5.1 Library 13.5.2 Subprogram 13.5.3 Package Partition

13.6.1 Physical partition 13.6.2 Logical partition Synthesis guidelines 13.8 Bibliographic notes

421 42 1 422 422 424 425 427 430 430 434 436 445 455 460 469 470 470 473 473 474 474 475 475 477 480 48 1 485 485 486 488 488 489 489 49 1 492 495 495 496 497 497

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Problems 497 14 Parameterized Design: Principle

14.1 Introduction 14.2 q p e s of parameters

14.2.1 Width parameters 14.2.2 Fearue parameters 14.3 Specifying parameters

14.3.1 Generics 14.3.2 Array attribute 14.3.3 Unconstrained array

14.3.4 Comparison between a generic and an unconstrained array 14.4 Clever use of an ^array

14.4.1 Description without fixed-size references 14.4.2 Examples

14.5 For generate statement 14.5.1 Syntax 14.5.2 Examples 14.6.1 Syntax 14.6.2 Examples

14.6.3 Comparisons with other feature-selection methods 14.7.1 Introduction

14.7.2 Examples of a simple for loop statement

14.7.3 Examples of a loop body with multiple signal assignment statements

14.7.4 Examples of a loop body with variables

14.7.5 Comparison of the for generate and for loop statements 14.8.1 Syntax of the exit statement

14.8.2 Examples of the exit statement

14.8.3 Conceptual implementation of the exit statement 14.8.4 Next statement

14.9 Synthesis of iterative structure 14.10 Synthesis guidelines

14.1 1 Bibliographic notes

14.6 Conditional generate statement

14.7 For loop statement

14.8 Exit and next statements

Problems

499 499 500 500 50 1 50 1 501 502 503 506 506 507 509 512 513 513 517 517 518 525 528 528 528 530 533 536 537 537 537 539 540 54 1 542 542 542 15 Parameterized Design: Practice

15.1 Introduction

545 545

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CONTENTS XVii

15.2 Data types for two-dimensional signals 15.2.1 Genuine two-dimensional data type 15.2.2 Array-of-arrays data type

15.2.3 Emulated two-dimensional array 15.2.4 Example

15.2.5 Summary

15.3 Commonly used intermediate-sized RT-level components 15.3.1 Reduced-xor circuit

15.3.2 Binary decoder 15.3.3 Multiplexer 15.3.4 Binary encoder 15.3.5 Barrel shifter 15.4 More sophisticated examples

15.4.1 Reduced-xor-vector circuit 15.4.2 Multiplier

15.4.3 Parameterized LFSR 15.4.4 Priority encoder 15.4.5 FIFO buffer

15.5 Synthesis of parameterized modules 15.6 Synthesis guidelines

15.7 Bibliographic notes Problems

16 Clock and Synchronization: Principle and Practice 16.1 Overview of a clock distribution network

16.1.1 Physical implementation of a clock distribution network 16.1.2 Clock skew and its impact on synchronous design 16.2 Timing analysis with clock skew

16.2.1 Effect on setup time and maximal clock rate 16.2.2 Effect on hold time constraint

16.3 Overview of a multiple-clock system 16.3.1 System with derived clock signals 16.3.2 GALS system

16.4 Metastability and synchronization failure 16.4.1 Nature of metastability

16.4.2 Analysis of MTBF(T!)

16.4.3 Unique characteristics of MTBF(T,) 16.5.1 The danger of no synchronizer 16.5.2 One-FF synchronizer and its deficiency 16.5.3 Wo-FF synchronizer

16.5.4 Three-FF synchronizer 16.5 Basic synchronizer

546 546 548 550 552 554 555 555 558 560 564 566 569 570 572 586 588 59 1 599 599 600 600 603 603 603 605 606 606 609 610 61 1 612 612 613 614 616 617 617 617 619 620

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16.5.5 Proper use of a synchronizer 16.6 Single enable signal crossing clock domains

16.6.1 Edge detection scheme 16.6.2 Level-alternation scheme 16.7.1 Four-phase handshaking protocol 16.7.2 Two-phase handshaking protocol 16.8 Data transfer crossing clock domains

16.8.1 Four-phase handshaking protocol data transfer 16.8.2 Two-phase handshaking data transfer

16.8.3 One-phase data transfer 16.9 Data transfer via a memory buffer

16.9.1 FIFO buffer 16.9.2 Shared memory 16.7 Handshaking protocol

16.10 Synthesis of a multiple-clock system 16.1 1 Synthesis guidelines

16.1 1.1 Guidelines for general use of a clock 16.1 1.2 Guidelines for a synchronizer

16.1 1.3 Guidelines for an interface between clock domains Problems

16.12 Bibliographic notes

62 1 623 623 627 630 630 637 639 641 650 65 1 652 652 660 661 662 662 662 662 663 663

References 665

Topic Index 667

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PREFACE

With the maturity and availability of hardware description language (HDL) and synthesis software, using them to design custom digital hardware has become a mainstream practice.

Because of the resemblance of an HDL code to a traditional program (such as a C program), some users believe incorrectly that designing hardware in HDL involves simply writing syn- tactically correct software code, and assume that the synthesis software can automatically derive the physical hardware. Unfortunately, synthesis software can only perform transformation and local optimization, and cannot convert a poor description into an efficient implementation. Without an understanding of the hardware architecture, the HDL code frequently leads to unnecessarily complex hardware, or may not even be synthesizable.

This book provides in-depth coverage on the systematical development and synthesis of efficient, portable and scalable register-transfer-level (RT-level) digital circuits using the VHDL hardware description language. RT-level design uses intermediate-sized components, such as adders, comparators, multiplexers and registers, to construct a digital system.

It is the level that is most suitable and effective for today’s synthesis software.

RT-level design and VHDL are two somewhat independent subjects. VHDL code is simply one of the methods to describe a hardware design. The same design can also be described by a schematic or code in other HDLs. VHDL and synthesis software will not lead automatically to a better or worse design. However, they can shield designers from low-level details and allow them to explore and research better architectures.

The emphasis of the book is on hardware rather than language. Instead of treating synthesis software as a mysterious black box and listing “recipe-like” codes, we explain the relationship between the VHDL constructs and the underlying hardware structure and illustrate how to explore the design space and develop codes that can be synthesized into efficient cell-level implementation. The discussion is independent of technology and can xix

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be applied to both ASIC and FPGA devices. The VHDL codes listed in the book largely follow the IEEE 1076.6 RTL synthesis standard and can be accepted by most synthesis software. Most codes can be synthesized without modification by the free “demo-version’’

synthesis software provided by FPGA vendors.

Scope The book focuses primarily on the design and synthesis of RT-level circuits. A subset of VHDL is used to describe the design. The book is not intended to be a comprehensive ASIC or FPGA book. All other issues, such as device architecture, placement and routing, simulation and testing, are discussed exclusively from the context of RT-level design.

Unique features The book is a hardware design text. VHDL and synthesis software are used as tools to realize the intended design. Several unique features distinguish the book:

0 Suggest a coding style that shows a clear relationship between VHDL constructs and

0 Use easy-to-understand conceptual diagrams, rather than cell-level netlists, to explain

0 Emphasize the reuse aspect of the codes throughout the book.

0 Consider RT-level design as an integral part of the overall development process and introduce good design practices and guidelines to ensure that an RT-level description can accommodate future simulation, verification and testing needs.

0 Make the design “technology neutral” so that the developed VHDL code can be applied to both ASIC and FPGA devices.

0 Follow the IEEE 1076.6 RTL synthesis standard to make the codes independent of synthesis software.

0 Provide a set of synthesis guidelines at the end of each chapter.

0 Contain a large number of non-trivial, practical examples to illustrate and reinforce the design concepts, procedures and techniques.

0 Include two chapters on realizing sequential algorithms in hardware (known as “register transfer methodology”) and on designing control path and data path.

0 Include two chapters on the scalable and parameterized designs and coding.

0 Include a chapter on the synchronization and interface between multiple clock do- Book organization The book is basically divided into three major parts. The first part, Chapters 1 to 6, provides a comprehensive overview of VHDL and the synthesis process, and examines the hardware implementation of basic VHDL language constructs. The second part, Chapters 7 to 12, covers the core of the RT-level design, including combinational circuits, “regular” sequential circuits, finite state machine and circuits designed by register transfer methodology, The third part, Chapters 13 to 16, covers the system issues, including the hierarchy, parameterized and scalable design, and interface between clock domains.

More detailed descriptions of the chapters follow.

0 Chapter 1 presents a “big picture” of digital system design, including an overview on device technologies, system representation, development flow and software tools.

0 Chapter 2 provides an overview on the design, usage and capability of a hardware description language. A series of simple codes is used to introduce the basic modeling concepts of VHDL.

0 Chapter 3 provides an overview of the basic language constructs of VHDL, including lexical elements, objects, data types and operators. Because VHDL is a strongly typed language, the data types and operators are discussed in more detail.

hardware components.

the realization of VHDL codes.

mains.

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PREFACE XXi

0 Chapter 4 covers the syntax, usage and implementation of concurrent signal assign- ment statements of VHDL. It shows how to realize these constructs by multiplexing and priority routing networks.

0 Chapter 5 examines the syntax, usage and implementation of sequential statements of VHDL. It shows the realization of the sequential statements and discusses the caveats of using these statements.

0 Chapter 6 explains the realization of VHDL operators and data types, provides an in-depth overview on the synthesis process and discusses the timing issue involved in synthesis.

0 Chapter 7 covers the construction and VHDL description of more sophisticated combinational circuits. Examples show how to transform conceptual ideas into hardware, and illustrate resource-sharing and circuit-shaping techniques to reduce circuit size and increase performance.

0 Chapter 8 introduces the synchronous design methodology and the construction and coding of synchronous sequential circuits. Basic “regular” sequential circuits, such as counters and shift registers, in which state transitions exhibit a regular pattern, are examined.

0 Chapter 9 explores more sophisticated regular sequential circuits. The design examples show the implementation of a variety of counters, the use of registers as fast, temporary storage, and the construction of pipelined combinational circuits.

0 Chapter 10 covers finite state machine (FSM), which is a sequential circuit with

“random” transition patterns. The representation, timing and implementation issues of FSMs are studied with an emphasis on its use as the control circuit for a large, complex system.

0 Chapter 11 introduces the register transfer methodology, which describes system operation by a sequence of data transfers and manipulations among registers, and demonstrates the construction of the data path (a regular sequential circuit) and the control path (an FSM) used in this methodology.

0 Chapter 12 uses a variety of design examples to illustrate how the register transfer methodology can be used in various types of problems and to highlight the design procedure and relevant issues.

0 Chapter 13 features the design hierarchy, in which a system is gradually divided into smaller parts. Mechanisms and language constructs of VHDL used to specify and configure a hierarchy are examined.

0 Chapter 14 introduces parameterized design, in which the width and functionality of a circuit are specified by explicit parameters. Simple examples illustrate the mechanisms used to pass and infer parameters and the language constructs used to describe the replicated structures.

0 Chapter 15 provides more sophisticated parameterized design examples. The main focus is on the derivation of efficient parameterized RT-level modules that can be used as building blocks of larger systems.

0 Chapter 16 covers the effect of a non-ideal clock signal and discusses the synchronization of an asynchronous signal and the interface between two independent clock domains.

Audience The intended audience for the book is students in advanced digital system design course and practicing engineers who wish to sharpen their design skills or to learn the effective use of today’s synthesis software. Readers need to have basic knowledge of digital systems. The material is normally covered in an introductory digital design course,

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which is a standard part in all electrical engineering and computer engineering curricula.

No prior experience on HDL or synthesis is needed.

Verilog is another popular HDL. Since the book emphasizes hardware and methodology rather than language constructs, readers with prior Verilog experience can easily follow the discussion and learn VHDL along the way. Most VHDL codes can easily be translated into the Verilog language.

Web site Anaccompanying web site (http: //academic. csuohio. edu/chu-p/rtl) provides additional information, including the following materials:

0 Errata.

0 Summary of coding guidelines.

0 Code listing.

0 Links to demo-version synthesis software.

0 Links to some referenced materials.

0 Frequently asked questions (FAQ) on RTL synthesis.

0 Lecture slides for instructors.

Errata The book is “self-prepared,” which means the author has prepared all materials, including the illustrations, tables, code listing, indexing and formatting, by himself. As the errors are always bound to happen, the accompanying web site provides an updated errata sheet and a place to report errors.

P. P. CHU

Cleveland, Ohio January 2006

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ACKNOWLEDGMENTS

The author would like to express his gratitude to Professor George L. Kramerich for his encouragement and help during the course of this project. The work was partially supported by educational material development grant 0126752 from the National Science Foundation and a Teaching Enhancement grant from Cleveland State University.

P. P. Chu

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CHAPTER 1 INTRODUCTION TO DIGITAL SYSTEM DESIGN

Developing and producing a digital system is a complicated process and involves many tasks. The design and synthesis of a register transfer level circuit, which is the focus of this book, is only one of the tasks. In this chapter, we present an overview of device technologies, system representation, development flow and software tools. This helps us to better understand the role of the design and synthesis task in the overall development and production process.

1.1 INTRODUCTION

Digital hardware has experienced drastic expansion and improvement in the past 40 years.

Since its introduction, the number of transistors in a single chip has grown exponentially, and a silicon chip now routinely contains hundreds of thousands or even hundreds of millions of transistors. In the past, the major applications of digital hardware were computational systems. However, as the chip became smaller, faster, cheaper and more capable, many electronic, control, communication and even mechanical systems have been "digitized"

internally, using digital circuits to store, process and transmit information.

As applications become larger and more complex, the task of designing digital circuits becomes more difficult. The best way to handle the complexity is to view the circuit at a more abstract level and utilize software tools to derive the low-level implementation.

This approach shields us from the tedious details and allows us to concentrate and explore high-level design alternatives. Although software tools can automate certain tasks, they are capable of performing only limited transformation and optimization. They cannot, and

RTL Hardware Design Using ^VHDL:Coding for EfJfciency, Portability, and Scalabili@. By Pong I? ^Chu ¹ Copyright @ 2006 John Wiley & Sons, Inc.

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will not, do the design or convert a poor design to a good one. The ultimate efficiency still comes from human ingenuity and experience. The goal of this book is to show how to systematically develop an efficient, portable design description that is both abstract, yet detailed enough for effective software synthesis.

Developing and producing a digital circuit is a complicated process, and the design and synthesis are only two of the tasks. We should be aware of the “big picture” so that the design and synthesis can be efficiently integrated into the overall development and production process. The following sections provide an overview of device technologies, system representation, abstraction, development flow, and the use and limitations of software tools.

1.2 DEVICE TECHNOLOGIES

If we want to build a custom digital system, there are varieties of device technologies to choose, from off-the-shelf simple field-programmable components to full-custom devices that tailor the application down to the transistor level. There is no single best technology, and we have to consider the trade-offs among various factors, including chip area, speed, power and cost.

1.2.1 Fabrication of an IC

To better understand the differences between the device technologies, it is helpful to have a basic idea of the fabrication process of an integrated circuit (IC). An IC is made from layers of doped silicon, polysilicon, metal and silicon dioxide, built on top of one another, on a thin silicon wafer. Some of these layers form transistors, and others form planes of connection wires.

The basic step in IC fabrication is to construct a layer with a customized pattern, a process known as lithography. The pattern is defined by a mask. Today’s IC device technology typically consists of 10 to 15 layers, and thus the lithography process has to be repeated 10 to 15 times during the fabrication of an IC, each time with a unique mask.

One important aspect of a device technology is the silicon area used by a circuit. It is expressed by the length of a smallest transistor that can be fabricated, usually measured in microns (a millionth of a meter). As the device fabrication process improved, the transistor size continued to shrink and now approaches a tenth of a micron.

1.2.2 Classification of device technologies

There is an array of device technologies that can be used to construct a custom digital circuit. One major characteristic of a technology is how the customization is done. In certain technologies, all the layers of a device are predetermined, and thus the device can be prefabricated and manufactured as a standard off-the-shelf part. The customization of a circuit can be performed “in the field,” normally by downloading a connection pattern to the device’s internal memory or by “burning the internal silicon fuses.” On ^{the other} hand, some device technologies need one or more layers to be customized for a particular application. The customization involves the creation of tailored masks and fabrication of the patterned layers. This process is expensive and complex and can only be done in a fabrication plant (known as afoundry or afub). Thus, whether a device needed to be fabricated in a fab is the most important characteristic of a technology. In this book, we use

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DEVICE TECHNOLOGIES 3 the term application-speciJic ZC (ASZC) to represent device technologies that require a fab to do customization.

With an understanding of the difference between ASIC and non-ASK, we can divide the device technologies further into the following types:

0 Full-custom ASIC

0 Standard-cell ASIC

0 Gate array ASIC

0 Complex field-programmable logic device

0 Simple field-programmable logic device

0 Off-the-shelf small- and medium-scaled IC (SSVMSI) components

Full-custom ASlC Infillastom ASZC technology, all aspects of a digital circuit are tailored for one particular application. We have complete control of the circuit and can even craft the layout of a transistor to meet special area or performance needs. The resulting circuit is fully optimized and has the best possible performance. Unfortunately, designing a circuit at the transistor level is extremely complex and involved, and is only feasible for a small circuit. It is not practical to use this approach to design a complete system, which now may contain tens and even hundreds of millions of transistors. The major application of full-custom ASIC technology is to design the basic logic components that can be used as building blocks of a larger system. Another application is to design special-purpose “bit- slice” typed circuits, such as a 1-bit memory or 1-bit adder. These circuits have a regular structure and are constructed through a cascade of identical slices. To obtain optimal performance, full-custom ASIC technology is frequently used to design a single slice. The slice is then replicated a number of times to form a complete circuit.

The layouts of a full-custom ASIC chip are tailored to a particular application. All layers are different and a mask is required for every layer. During fabrication, all layers have to be custom constructed, and nothing can be done in advance.

Standard-cell ASlC In standard-cell A S K (also simply known as standard-cell) technology, a circuit is constructed by using a set of predefined logic components, known as standard cells. These cells are predesigned and their layouts are validated and tested.

Standard-cell ASIC technology allows us to work at the gate level rather than at the transistor level and thus greatly simplifies the design process. The device manufacturer usually provides a library of standard cells as the basic building blocks. The library normally consists of basic logic gates, simple combinational components, such as an and-or-inverter, 2-to-1 multiplexer and 1-bit full adder, and basic memory elements, such as a D-type latch and D-type flip-flop. Some libraries may also contain more sophisticated function blocks, such as an adder, barrel shifter and random access memory (RAM).

In standard-cell technology, a circuit is made of cells. The types of cells and the intercon- nection depend on the individual application. Whereas the layout of a cell is predetermined, the layout of the complete circuit is unique for a particular application and nothing can be constructed in advance. Thus, fabrication of a standard-cell chip is identical to that of a full-custom ASIC chip, and all layers have to be custom constructed.

Gate array ASlC In gate array ASIC (also simply known as gate array) technology, a circuit is built from an array of predefined cells. Unlike standard-cell technology, a gate array chip consists of only one type of cell, known as a base cell. The base cell is fairly simple, resembling a logic gate. Base cells are prearranged and placed in fixed positions, aligned as a one- or two-dimensional array. Since the location and type are predetermined,

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the base cells can be prefabricated. The customization of a circuit is done by specifying the interconnect between these cells. A gate array vendor also provides a library of predesigned components, known as macro cells, which are built from base cells. The macro cells have a predefined interconnect and provide the designer with more sophisticated logic blocks.

Compared to standard-cell technology, the fabrication of a gate array device is much simpler, due to its fixed array structure. Since the array is common to all applications, the cell (and transistors) can be fabricated in advance. During construction of a chip, only the masks of metal layers, which specify the interconnect, are unique for an application and therefore must be customized. This reduces the number of custom layers from 10 to 15 layers to 3 to 5 layers and simplifies the fabrication process significantly.

Complex field-programmable device We now examine several non-ASIC technologies. The most versatile non-ASIC technology is the complex field-programmable device.

In this technology, a device consists of an array of generic logic cells and general interconnect structure. Although the logic cells and interconnect structure are prefabricated, both are programmable. The programmability is obtained by utilizing semiconductor “fuses” or

“switches,” which can be set as open- or short-circuit. The customization is done by config- uring the device with a specific fuse pattern. This process can be accomplished by a simple, inexpensive device programmer, normally constructed as an add-on card or an adaptor cable of a PC. Since the customization is done “in the field” rather than “in a fab,” this technology is known as field programmable. (In contrast, ASIC technologies are “programmed” via one or more tailored masks and thus are mask programmable.)

The basic structures of gate array ASKS and complex field-programmable devices are somewhat similar. However, the interconnect structure of field-programmable devices is predetermined and thus imposes more constraints on signal routing. To reduce the amount of connection, more functionality is built into the logic cells of a field-programmable device, making a logic cell much more complex than a base cell or a standard cell of ASIC.

According to the complexity and structure of logic cells, complex field-programmable devices can be divided roughly into two broad categories: complex programmable logic device (CPLD) and field programmable gate array (FPGA).

The logic cell of a CPLD device is more sophisticated, normally consisting of a D-type flip-flop and a PAL-like unit with configurable product terms. The interconnect structure of a CPLD device tends to be more centralized, with few groups of concentrated routing lines.

On the other hand, the logic cell of an FPGA device is usually smaller, typically including a D-type flip-flop and a small look-up table or a set of multiplexers. The interconnect structure between the cells tends to be distributed and more flexible. Because of its distributive nature, FPGA is better suited for large, high-capacity complex field-programmable devices, Simple field-programmable device Simple field-programmable logic devices, as the name indicates, are programmable devices with simpler internal structure. Historically, these devices are generically called programmable logic devices (PLDs). We add the word simple to distinguish them from FPGA and CPLD devices. Simple field-programmable devices are normally constructed as a two-level array, with an and plane and an or plane.

The interconnect of one or both planes can be programmed to perform a logic function expressed in sum-of-product format. The devices include programmable read only memory (PROM), in which the or plane can be programmed; programmable array logic (PAL), in which the and plane can be programmed; and programmable logic array (PLA), in which both planes can be programmed.

Unlike FPGA and CPLD devices, simple field-programmable logic devices do not have a general interconnect structure, and thus their functionality is severely limited. They are

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DEVICE TECHNOLOGIES 5 gradually being phased out.

ROM,

PAL and PLA are now used as internal components of an ASIC or CPLD device rather than as an individual chip.

Off-the-shelf SSvMsl components Before the emergence of field-programmable devices, the only alternative to ASIC was to utilize the prefabricated off-the-shelf SSVMSI components. These components are small parts with fixed, limited functionality. One example is the 7400 series transistor transistor logic (“L) family, which contains more than 100 parts, ranging from simple nand gates to a 4-bit arithmetic unit. A custom system can be designed by a bottom-up approach, building the circuit gradually from the small existing parts. A tailored printed circuit board is needed for each application. The major disadvan- tage of this approach is that the most resources (power, board area and manufacturing cost) are consumed by the “package” but not by the “silicon,” which performs the actual computation. Furthermore, none of today’s synthesis software can utilize off-the-shelf SSI/MSI components, and thus automation is virtually impossible. As the programmable devices become more capable and less expensive, designing a large custom circuit using SSVMSI components is no longer a feasible option and should not be considered.

Summary We have reviewed six device technologies used to implement custom digital systems. Among them, off-the-shelf SSUMSI components and simple programmable devices are gradually being phased out and full-custom ASIC is feasible only for a small, specialized circuit. Thus, for a large digital system, there are only three viable device technologies: standard-cell ASIC, gate array ASIC and CPLDEPGA. In the following subsection, we examine the trade-offs among these technologies.

1.2.3 Comparison of technologies

Once deciding to develop custom hardware for an application, we need to choose from the three device technologies. The major criteria for selection are area, speed, power and cost.

The first three involve the technical aspects of a circuit. Cost concerns the expenditure associated with the design and production of the circuit as well as the potential lost profits.

Each technology has its strengths and weaknesses, and the “best” technology depends on the needs of a particular application.

Area Chip area (or size) corresponds to the required silicon real estate to implement a particular application. A smaller chip needs fewer resources, simplifies the testing and provides better yield. The chip size depends on the architecture of the circuit and the device technology. The same function can frequently be realized by different architectures, with different areas and speeds. For example, an addition circuit can be realized by a ripple adder (simple but slow), a parallel adder (complex but fast) or a carry-look-ahead adder (somewhere in-between). Once the architecture of a circuit is determined, the area depends on the device technology. In standard-cell technology, the cells and interconnects are customized to this particular application and no silicon is wasted in irrelevant functionality.

Thus, the resulting chip is fully optimized and the area is minimal. In gate array technology, the circuit has to be constructed by predefined, prearranged base cells. Since functionality and the placement of the base cells are not tailored to a specific application, silicon use is not optimal, The area of the resulting circuit is normally larger than that of a standard-cell chip. In FPGA technology, a significant portion of the silicon is dedicated to achieving programmability, which introduces a large overhead. Furthermore, the functionalities of logic cells and the interconnect are fixed in advance and it is unlikely that an application

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can be an exact match for the predetermined structure. A certain percentage of the capacity will be left unutilized. Because of the overhead and relatively low utilization, the area of the resulting FPGA chip is much larger than that of an ASIC chip.

Due to the drastic difference between the device fabrication process and the diversity of applications, it is difficulty to determine the exact silicon areas in three technologies.

However, it is important to recognize that the difference between standard-cell and gate array technologies is much smaller than that of FPGA and ASIC. In general, a gate array chip may need 20% to 100% larger silicon area than that of a standard-cell chip, but an FPGA chip frequently requires two to five times the area of an ASIC chip.

Speed The speed of a digital circuit corresponds to the time required to perform a function, frequently represented by the worst-case propagation delay between input and output signals. A faster circuit is always desirable and is essential for computation-intensive applications. At the architecture level, faster operation can be achieved by using a more sophisticated design, which requires a larger area. However, if the identical architecture is used, a chip with a larger area is normally slower, due to its large parasitic capacitance.

Since a standard-cell chip has tailored interconnect and utilizes a minimal amount of silicon area, it has the smallest propagation delay and best speed. On the other hand, an FPGA chip has the worst propagation delay. In addition to its large size, the programmable interconnect has a relatively large resistance and capacitance, which introduces even more delay. As with chip area, the speed difference between standard-cell and gate array technologies is much less significant than that between FPGA and ASIC.

Power Power concerns the energy consumed by a part. In certain applications, such as battery-operated handheld equipment, a low power circuit is of primary importance. At the architecture level, a system can be redesigned to reduce the use of power. If the identical architecture is used, a smaller chip, which consists of fewer transistors, usually consumes less power. Thus, a standard-cell chip consumes the least amount of power and an P G A chip uses the most power.

Standard-cell technology is clearly the best choice from a technical perspective. A chip constructed using standard-cell ASIC is small and fast, and consumes less power. This should not come as a surprise since the chip is highly optimized and wastes no resources on unnecessary overhead. The price associated with customization is the complexity. De- signing and fabricating a standard-cell chip is more involved and time consuming than for the other two technologies.

Cost The design of a custom digital circuit is seldom a goal in itself. It is an economic activity, and the cost is an important, if not the deciding, factor. We consider three major expenses: production cost, development cost, and time-to-market cost.

Production cost is the expense to produce a single unit. It includes two segments: non- recurring engineering (NRE) cost and part cost. NRE cost (Cnre) is the expense that occurs only once (and thus is not recurring) during the production process, regardless of the number of units sold. Thus, it is on a “per design” basis. Part cost (Cper-part), on the other hand, is on a “per unit” basis, covering the expense required for each individual unit, such as the expense of materials, assembly and manufacturing. Note that the NREi cost is shared by all the units and that the share of each part becomes smaller as the volume increases. The per unit production cost (Cper-unit) can be expressed as

c n r e Cper-unit = ^Cper-part

+

units produced

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DEVICE TECHNOLOGIES 7

unit cost

break-even point for

\ /-

^gatearray

break-even point for standard cell

\ \

\ ^\\

7

^FPGA

gate array standard

---__ --L-

7

^cell

number of units

Figure 1.1 Comparison of per unit cost.

The NRE cost of a custom ASIC chip includes the creation of the tailored masks, the development of tests and the fabrication of initial sample chips. The charge is high and can range from several hundred thousand dollars to several million dollars or more. A major factor in the

NRE

^{cost is}^thenumber of custom masks needed. A standard-cell chip may need 15 or more tailored masks and thus is much more expensive than a gate array chip, which needs only three to five tailored metal layers. On the contrary, an PGA-based design needs only an inexpensive device programmer to do customization. The

NRE

^cost

of creating a mask is negligible and can be considered as zero.

The part cost of an ASIC chip is smaller than that of an P G A chip since the ASIC chip requires less silicon real estate and has better yield. By the same token, the part cost of a standard-cell chip is smaller than that of a gate array chip since the standard-cell chip is further optimized. If we consider both part cost and

NRE

cost, the per unit production cost depends on the volume of units, as shown by the previous equation. The volume versus per unit cost plots of three technologies is shown in Figure 1.1. As the volume increases, first the gate array and then the standard-cell technologies, become cost-effective. The intersections of the curves are the break-even points for the FPGA and gate array technologies, and for the gate array and standard-cell technologies.

The second major expense is the development cost. The process of transforming an idea to a custom circuit is by no means a simple task. The expense involved in this process is the development cost. It includes the compensation for engineering time as well as the expense of the computing facility and software tools. Although the synthesis procedure is somewhat similar for all device technologies, developing ASIC requires more effort, including physical design, placement and routing, verification and testing. Since the development process is more complex for ASIC, the development cost of an ASIC chip is much higher than that of an P G A chip. Similarly, due to the high-level optimization, the development cost for a standard-cell chip is much higher than that for a gate array chip.

The third major expense is the time-to-market cost. It is actually not a cost, but the lost revenue. In many applications, such as PC peripherals, the life cycle of a product is

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Table 1.1 Comparison of device technologies

Tailored masks Area

Speed Power

NRE

^cost Per part cost Development cost Time to market Per unit cost

FPGA Gate array Standard cell

0 3 to 5 15 or more

best (smallest) best (fastest) best (minimal) best (smallest) best (smallest)

best (easiest) best (shortest)

depends on volume

very short. Eighteen months, the time required to double the chip density, is sometimes considered as the life cycle of the product. Thus, it is very important to introduce the product in a timely manner, and a shipping delay can mean a significant loss in sales. The standard- cell technology requires the most lead time to validate, test and manufacture, ranging from a few months to a year, The gate array technology requires less lead time, from a few weeks to a few months. For FPGA technology, customization involves the programming of a prefabricated chip and can be done in a few minutes.

Summary The major characteristics of the three device technologies are summarized in Table 1.1. In general, the trade-off is between the optimal use of hardware resources (in terms of chip area, speed and power) and the ease of design (in terms of NRE cost, development cost and manufacturing lead time).

The choice of technology is not necessarily mutual exclusive. For example, ASIC and FPGA developments can be done in parallel to get the benefits of both technologies. The FPGA devices are used as prototypes and in initial shipments to cut the manufacturing lead time. When the ASIC devices become available later, they are used for volume production to reduce cost.

1.3 SYSTEM REPRESENTATION

A large digital system is quite complex. During the development and production process, each task may require a specific kind of information about the system, ranging from system specification to physical component layout. The same system is frequently described in different ways and is examined from different perspectives. We call these perspectives the representations or views of a system. There are three views:

0 Behavioral view

0 Structural view

0 Physical view

A behavioral view describes the functionality (i.e., “behavior”) of a system. It treats the system as a black box and ignores its internal implementation. The view focuses on the relationship between the input and output signals, defining the output response when a particular set of input values is applied. The description of a behavioral view is seldom unique. Normally, there are a wide variety of ways to specify the same input-output characteristics.

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LEVELS OF ABSTRACTION 9 A structural view ^describesthe internal implementation (i.e., structure) of a system.

The description is done by explicitly specifying what components are used and how these components are connected. It is more or less the schematic or the diagram of a system. In computer software, we use the term net to represent a set of wires that are connected to the same node, and use the term netlist, which is a collection of nets, to represent the schematic.

A physical view describes the physical characteristics of the system and adds additional information to the structural view. It specifies the physical sizes of components, the physical locations of the components on a board or a silicon wafer, and the physical path of each connection line. An example of a physical view is the printed circuit board layout of a system.

Clearly, the physical view of a system provides the most detailed information. It is the final specification for the system fabrication. On the other hand, the behavioral view imposes fewest constraints and is the most abstract form of description.

1.4 LEVELS

OF

ABSTRACTION

As chip density reaches hundreds of millions of transistors, it is impossible for a human being, or even a computer, to process this amount of data directly. A key method of managing complexity is to describe a system in several levels of abstraction. An abstraction is a simplified model of the system, showing only the selected features and ignoring the associated details. The purpose of an abstraction is to reduce the amount of data to a manageable level so that only the critical information is presented. A high-level abstraction is focused and contains only the most vital data. On the other hand, a low-level abstraction is more detailed and takes account of previously ignored information. Although it is more complex, the low-level abstraction model is more accurate and is closer to the real circuit.

In the development process, we normally start with a high-level abstraction and concentrate on the most vital characteristics. As the system is better understood, we then include more details and develop a lower-level abstraction.

Four levels of abstraction are considered in digital system development:

0 Transistor level

0 Gate level

0 Register transfer (RT) level

0 Processor level

The division of these levels is based primarily on the size of basic building blocks, which are the transistors, logic gates, function modules and processors respectively.

The level of abstraction and the view are two independent dimensions of a system, and each level has its own views. The levels of abstraction and views can be combined in a Y-chart, which is shown in Figure 1.2. In this chart, each axis represents a view and the levels of abstraction increase from the center to the outside.

The following subsections discuss the four levels of abstraction. In the discussion, we examine the five main characteristics at each level of abstraction:

0 Basic building blocks

0 Signal representation

0 Time representation

0 Behavioral representation

0 Physical representation

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Behavioral view Structure view

register transfer operation

transistor layout cell layout module floor plan IP floor plan

Physical view

Figure 1.2 Y-chart.

Basic building blocks are the most commonly used parts at the level. These parts are the components used in the structure view. Behavioral and physical representations are the descriptions for the behavioral and physical views.

Signal and timing representations concern how to express a signal’s value and how the value changes over time. While the physical signal remains the same, the interpretation of its value and timing is different at each abstraction level. As we expect, more detailed information will be provided at lower levels.

1.4.1 Transistor-level abstraction

The lowest level of abstraction is the transistor level. At this level, the basic building blocks are transistors, resistors, capacitors and so on. The behavior description is usually done by a set of differential equations or even by some type of current-voltage diagram. Analog system simulation software, such as SPICE, can be used to obtain the desired input-output characteristics.

At the transistor level, a digital circuit is treated as an analog system, in which signals are time-varying and can take on any value of a continuous range. For example, the output response of an inverter is plotted at the top of Figure 1.3.

The physical description of the transistor level comprises the detailed layout of components and their interconnections. It essentially defines the masks of various layers and is the final result of the design process.

1.4.2 Gate-level abstraction

The next level of abstraction is the gate level. Typical building blocks include simple logic gates, such as and, or, xor and 1-bit 2-to-1 multiplexer, and basic memory elements, such

VHDL Coding

RTL HARDWARE DESIGN USING VHDL

Coding for Efficiency, Portability, and Scalability

PONG P. CHU

RTL HARDWARE DESIGN

USING VHDL

RTL HARDWARE DESIGN USING VHDL

Coding for Efficiency, Portability, and Scalability

PONG P. CHU

To

parents Chia-Chi and Chi-Te, my wife Lee, and my daughter Patricia

CONTENTS

IEEE

IEEE

’-’

RAM

SRAM

PREFACE

ACKNOWLEDGMENTS

CHAPTER 1

INTRODUCTION TO DIGITAL SYSTEM DESIGN

ROM,

+

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7

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7

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OF

PONG P. ^CHU

PONG P. ^CHU