MCS4
Microcomputer Kit
MCS~4 - INTEL'S LOWEST COST MICROCOMPUTER.
IDEAL FOR PROTOTYPE OR LOW VOLUME PRODUCTION.
The MCS-4 is a microprogrammable computer set designed for applications such as test systems, peripherals, terminals, billing machines, measuring systems, numeric and process control.
The 4004 CPU, 4003 SR, and 4002 RAM are standard building blocks.
The 4008 and 4009 are a pair of inter- face devices which expand the capa- bilities of Intel's MCS-4 microcomputer set. Now standard Intel PROMs, ROMs and RAMs may be used for the pro- gram memory of the MCS-4.
MCS-4 systems interface easily with switches, keyboards, displays, teletype- writers, printers, readers, A-D con- verters and other popular peripherals.
A system built with the MCS-4 micro- computer set can have up to 4K x 8 bit ROM words, 1280 x 4 bit RAM characters and 128 I/O lines without
4004 CPU
~"f
I 16""l
CM·RAM, MEMORYBUS CONTROL
I/O 0, CM.RAM, OUTPUTS
0, CM·RAM3
GNO Vss 5 12 Voo -15V
p~~g~~}<p, 6 II CM·ROM . OUTPUT {MEMORY CONTROL p~~~m<p, 7
Ou;~~nSYNC 8
4702A ROM
·THIS PIN IS THE DATA INPUT LEAD DURING PROGRAMMING.
requiring any interface logic. By adding a few simple gates the MCS-4 can have up to 48 RAM and ROM packages in any combination, and 192 I/O lines.
The MCS-4 has a very powerful in- struction set that allows both binary and decimal arithmetic. It includes conditional branching, jump to sub- routine, and provides for the efficient use of ROM look-up tables by indirect fetching.
The Intel MCS-4 microcomputer set (4002/3/4/8/9 and 4702A) are fabri- cated with Silicon Gate Technology.
This low threshold technology allows the design and production of higher performance MaS circuits and provides a higher functional density on a mono- lithic chip than conventional MaS technologies.
4002 RAM
""f
I 16
'j
0,BUS OUTPUT
1100, O
2 LINES
03 0 3
12 Voo -15V
p~~i~}<p, 6 II CM CONTROL {MEMORY INPUT
p~l~g}<P, 7 10 ·lHAROWIREO Po CHIPSELECT
I~~~~}SYNC 8 9 RESET INPUT
4008
MCS4 KIT A
• Programmable General Purpose Microcomputer
• 4-Bit Parallel CPU with 46 Instructions
• Instruction Set includes Conditional Branching, Jump to Subroutine and Indirect Fetching
• Binary and Decimal Arithmetic Modes
• Program Storage in 4702A Reprogrammable PROM Simulates 4001 ROM
• 2-Phase Dynamic Operation
• 10.8 Microsecond Instruction Cycle
• CPU Directly Compatible with MCS-4 ROMs and RAMs Using 4008/4009 Standard Memory ana 1/0 Interface Set
• Easy Expansion-One CPU can Directly Drive up to 32,768 Bits of ROM and up to 5120 Bits of RAM
4003SR
PULSE ~~~~*p I
PARALLEL{Oo 3 OUTPUTS
n, 13
')
a.
a PARALLEL
f
6 7 OUTPUTSPARALLEL 0 OUTPUTS 3 a.
O. 05
4009
MCS4 KIT A
SYSTEM INTERCONNECT
+5V
7400
HC-18/U (XTAL) 5.185 MHZ
~
1 50 820n 2 .01/'1Ipi
820n
74H04
.1/,1
47S1
RESET
47n
TEST
+5
11 on
11 on
5.6K
-10V
SUGGESTED CLOCK DRIVER, TEST AND RESET CIRCUITRY
TEST
1 2 3 4
~ ~ 8
7
i 4008
~ ~ Jl2 --2... F/L
-1Q... W 11 13 1415
C C C C 3 2 1 0
****
NOTES:
CONSUL T MCS 4 USER'S MANUAL.
SEE 4008/4009 DATA SHEET.
SEE 4702A DATA SHEET .
•••• THESE LINES MAY BE DECODED FOR UP TO 16 PROMS.
(Vss = +5V !5%; Voo = -10V !5%) 23 22 21 20 19 18 17 16
I
TEST 10
7'
6 16 15i C4004 14
CPU 13
1 12 3 4 81111 9f
I I 1
I 1
I
221231121131151 Vss
AO 3 4
Al 2 5
A2 1 6
A3 21
i 4702A 7
A4 20 PROM 8
A5 19 0 9
A6 18 10
Al 17 11
~ 14
24Voo
1
16'{
TO 16PROMS * * *
III III
CM-RAM 0 CM-RAM 1 CM-RAM 2 CM-RAM 3
RESET CM-ROM
SYNC DO Dl D2 D3
RDO 5
RD1 6
RD2 7
RD3 8
RD4 1
RD5 2
RD6 3
RD7 4
1.
2322 21rf
~ ~ 13
14 i 4009
~
110 { ~
~2
~6 3 910
iN OUT
' - - - - y - - - / INPUT/OUTPUT PORT CIRCUITRY
**
- -
--
- - - -
--
- - - -- - - - - - - -
--
- - - ---
--
---
r-
- - - -- - - -1 2
1
4f
8 9 7 6 PO0---;-0
Vss RAM
DATA IN
i P4002-1 o 1 2 3 161514\131
--- I I I CP I I ENABLE
1 I )., 16
~ i P4003 15 SERIAL
31416171819ttttl
00--- --- 09 ' - - - y - - - - J
PARALLEL OUTPUTS DATA OUT
INTEL CORPORATION, 3065 Bowers Avenue, Santa Clara, California 95051 (408) 246-7501
©Intel Corp. 1974jPrintec!.in U.SAjMCS-20S-0874-SK
UP TO 16 RAMS 4 RAMS *
PER BANK