HALF-BRIDGE DRIVER IR2184 4 ( )(S)

IR2184 ⁽ 4 )(S)

Typical Connection

HALF-BRIDGE DRIVER

Features

•

Floating channel designed for bootstrap operation Fully operational to +600V

Tolerant to negative transient voltage dV/dt immune

•

Gate drive supply range from 10 to 20V

•

Undervoltage lockout for both channels

•

3.3V and 5V input logic compatible

•

Matched propagation delay for both channels

•

Logic and power ground +/- 5V offset.

•

Lower di/dt gate driver for better noise immunity

•

Output source/sink current capability 1.4A/1.8A

Description

IR21844 IR2184

V_CC V_B

V_S HO

LO COM IN SD SD

IN

up to 600V

TO LOAD VCC

IN

up to 600V

TO LOAD V_CC V_B

V_S HO

LO COM IN

DT V_SS SD V_CC

SD

V_SS

R_DT

(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

Packages

14-Lead PDIP IR21844 8-Lead SOIC

IR2184S

14-Lead SOIC IR21844S 8-Lead PDIP

IR2184

The IR2184(4)(S) are high voltage, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels. Pro- prietary HVIC and latch immune CMOS technologies enable rugge- dized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for

minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.

Part Input logic

Cross- conduction prevention

logic

Dead-Time Ground Pins Ton/Toff

2181 COM

21814 HIN/LIN no none VSS/COM 180/220 ns

2183 Internal 500ns COM

21834 HIN/LIN yes

Program 0.4 ~ 5 us VSS/COM 180/220 ns

2184 Internal 500ns COM

21844 IN/SD yes Program 0.4 ~ 5 us VSS/COM 680/270 ns

IR2181/IR2183/IR2184 Feature Comparison

Symbol Definition Min. Max. Units

V_B High side floating absolute voltage -0.3 625

V_S High side floating supply offset voltage V_B - 25 V_B + 0.3

V_HO High side floating output voltage V_S - 0.3 V_B + 0.3

V_CC Low side and logic fixed supply voltage -0.3 25

V_LO Low side output voltage -0.3 V_CC + 0.3

DT Programmable dead-time pin voltage (IR21844 only) V_SS - 0.3 V_CC + 0.3

V_IN Logic input voltage (IN & SD) V_SS - 0.3 V_SS + 10

V_SS Logic ground (IR21844 only) V_CC - 25 V_CC + 0.3

dV_S/dt Allowable offset supply voltage transient — 50 V/ns

P_D Package power dissipation @ T_A ≤ +25°C (8-lead PDIP) — 1.0

(8-lead SOIC) — 0.625

(14-lead PDIP) — 1.6 (14-lead SOIC) — 1.0 Rth_JA Thermal resistance, junction to ambient (8-lead PDIP) — 125

(8-lead SOIC) — 200

(14-lead PDIP) — 75

(14-lead SOIC) — 120

T_J Junction temperature — 150

T_S Storage temperature -50 150

T_L Lead temperature (soldering, 10 seconds) — 300

V

°C

°C/W W

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V_S and V_SS offset rating are tested with all supplies biased at 15V differential.

Note 1: Logic operational for V_S of -5 to +600V. Logic state held for V_S of -5V to -V_BS. (Please refer to the Design Tip DT97-3 for more details).

Note 2: IN and SD are internally clamped with a 5.2V zener diode.

VB High side floating supply absolute voltage V_S + 10 V_S + 20

V_S High side floating supply offset voltage Note 1 600

V_HO High side floating output voltage V_S V_B

V_CC Low side and logic fixed supply voltage 10 20

V_LO Low side output voltage 0 V_CC

V_IN Logic input voltage (IN & SD) V_SS V_SS + 5

DT Programmable dead-time pin voltage (IR21844 only) V_SS V_CC

V_SS Logic ground (IR21844 only) -5 5

T_A Ambient temperature -40 125 °C

V

Symbol Definition Min. Max. Units

Dynamic Electrical Characteristics

V_BIAS (V_CC, V_BS) = 15V, V_SS = COM, C_L = 1000 pF, T_A = 25°C, DT = VSS unless otherwise specified.

Symbol Definition Min. Typ. Max. Units Test Conditions

ton Turn-on propagation delay — 680 900 V_S = 0V

toff Turn-off propagation delay — 270 400 V_S = 0V or 600V

tsd Shut-down propagation delay — 180 270

MTon Delay matching, HS & LS turn-on — 0 90

MToff Delay matching, HS & LS turn-off — 0 40

tr Turn-on rise time — 40 60 V_S = 0V

tf Turn-off fall time — 20 35 V_S = 0V

DT Deadtime: LO turn-off to HO turn-on(DTLO-HO) & 280 400 520 RDT= 0 HO turn-off to LO turn-on (DTHO-LO) 4 5 6 µsec RDT = 200k

MDT Deadtime matching = DT_{LO - HO} - DT_HO-LO — 0 50 RDT=0

— 0 600 RDT = 200k

nsec

nsec

Static Electrical Characteristics

V_BIAS (V_CC, V_BS) = 15V, V_SS = COM, DT= V_SS and T_A = 25°C unless otherwise specified. The V_IL, V_IH and I_IN parameters are referenced to V_SS /COM and are applicable to the respective input leads: IN and SD. The V_O, I_O and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO.

Symbol Definition Min. Typ. Max. Units Test Conditions

V_IH Logic “1” input voltage for HO & logic “0” for LO 2.7 — — V_CC = 10V to 20V V_IL Logic “0” input voltage for HO & logic “1” for LO — — 0.8 V_CC = 10V to 20V

V_SD,TH+ SD input positive going threshold 2.7 — — V_CC = 10V to 20V

V_SD,TH- SD input negative going threshold — — 0.8 V_CC = 10V to 20V

V_OH High level output voltage, V_BIAS - V_O — — 1.2 I_O = 0A

V_OL Low level output voltage, V_O — — 0.1 I_O = 0A

I_LK Offset supply leakage current — — 50 V_B = V_S = 600V

I_QBS Quiescent V_BS supply current 20 60 150 V_IN = 0V or 5V

I_QCC Quiescent V_CC supply current 0.4 1.0 1.6 mA V_IN = 0V or 5V

I_IN+ Logic “1” input bias current — 5 20 IN = 5V, SD = 0V

I_IN- Logic “0” input bias current — 1 2 IN = 0V, SD = 5V

V_CCUV+ V_CC and V_BS supply undervoltage positive going 8.0 8.9 9.8 V_BSUV+ threshold

V_CCUV- V_CC and V_BS dupply undervoltage negative going 7.4 8.2 9.0 V_BSUV- threshold

V_CCUVH Hysteresis 0.3 0.7 —

V_BSUVH

I_O+ Output high short circuit pulsed vurrent 1.4 1.9 — V_O = 0V,

PW ≤ 10 µs

I_O- Output low short circuit pulsed current 1.8 2.3 — V_O = 15V,

PW ≤ 10 µs V

µA

µA

V

A

Functional Block Diagrams

2184

S D

UV DETECT

DELAY

IN V S

H O V B

PULSE FILTER HV

LEVEL SHIFTER

R R S

Q UV

DETECT

PULSE GENERATOR

V S S / C O M LEVEL SHIFT V S S / C O M

LEVEL SHIFT

+5V

DEADTIME

C O M L O V C C

2 1 8 4 4

S D

UV D E T E C T

D E L A Y

IN

D T

V S S

V S H O V B

P U L S E F I L T E R HV

L E V E L S H I F T E R

R R S

Q UV

D E T E C T

P U L S E G E N E R A T O R

V S S / C O M L E V E L S H I F T V S S / C O M

L E V E L S H I F T

+5V

D E A D T I M E

C O M L O V C C

14-Lead PDIP 14-Lead SOIC

IR21844 IR21844S

Lead Assignments

8-Lead PDIP 8-Lead SOIC

Lead Definitions

Symbol Description

IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM for IR2184 and VSS for IR21844)

SD Logic input for shutdown (referenced to COM for IR2184 and VSS for IR21844) DT Programmable dead-time lead, referenced to VSS. (IR21844 only)

VSS Logic Ground (21844 only) V_B High side floating supply HO High side gate drive output V_S High side floating supply return V_CC Low side and logic fixed supply LO Low side gate drive output COM Low side return

IR2184 IR2184S

1 2 3 4

8 7 6 5 IN

SD COM LO

VB HO VS VCC

1 2 3 4

8 7 6 5 IN

SD COM LO

VB HO VS VCC

1 2 3 4 5 6 7

14 13 12 11 10 9 8 IN

SD VSS DT COM LO VCC

VB HO VS 1

2 3 4 5 6 7

14 13 12 11 10 9 8 IN

SD VSS DT COM LO VCC

VB HO VS

01-6014 01-3003 01 (MS-001AB)

8-Lead PDIP

01-6027 01-0021 11 (MS-012AA)

8-Lead SOIC

8 7

5

6 5

D B

E A

6X e

H 0.25 [.010] A 6

4 3

1 2

4. OUT LINE CONF ORMS T O JEDEC OUTLINE MS-012AA.

NOT ES:

1. DIMENS IONING & T OLERANCING PE R ASME Y14.5M-1994.

2. CONT ROLLING DIMENSION: MILLIMET ER 3. DIMENS IONS ARE SHOWN IN MILLIME TE RS [INCHES].

7 K x 45°

8X L 8X c

y

F OOT PRINT 8X 0.72 [.028]

6.46 [.255]

3X 1.27 [.050] 8X 1.78 [.070]

5 DIMENSION DOES NOT INCLUDE MOLD PROT RUS IONS.

6 DIMENSION DOES NOT INCLUDE MOLD PROT RUS IONS.

MOLD PROTRUSIONS NOT T O E XCEED 0.25 [.010].

7 DIMENSION IS T HE LE NGTH OF LEAD FOR SOLDE RING TO A SUBS TRAT E.

MOLD PROTRUSIONS NOT T O E XCEED 0.15 [.006].

0.25 [.010] C A B e1

A

8X b A1

C

0.10 [.004]

e 1 D E

y b A A1

H K L

.189 .1497

0°

.013

.050 BAS IC .0532 .0040

.2284 .0099 .016

.1968 .1574

8°

.020 .0688 .0098

.2440 .0196 .050

4.80 3.80 0.33 1.35 0.10

5.80 0.25 0.40 0°

1.27 BAS IC 5.00 4.00 0.51 1.75 0.25

6.20 0.50 1.27

MIN MAX

MILLIMET ERS INCHES

MIN MAX

DIM

8°

e

c .0075 .0098 0.19 0.25

.025 BAS IC 0.635 BAS IC

01-6019 01-3063 00 (MS-012AB)

14-Lead SOIC (narrow body)

01-6010 01-3002 03 (MS-001AC)

14-Lead PDIP

Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions SD

IN

HO

LO

IN

(HO)

tr

ton toff tf

LO HO

50% 50%

90% 90%

10% 10%

IN

(LO)

Figure 5. Delay Matching Waveform Definitions HO

50% 50%

10%

LO

90%

MT

HO LO

MT IN(LO)

IN(HO)

Figure 3. Shutdown Waveform Definitions SD

tsd

HO LO

50%

90%

Figure 4. Deadtime Waveform Definitions IN

HO

50% 50%

90%

10%

LO _90%

10%

DT_LO-HO

DT_LO-HO

MDT= - DT_HO-LO

DT_HO-LO

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 7/24/2001