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Achieving high CPU efficiency and low tail latency in datacenters

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Academic year: 2021

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Figure

Figure  1-1:  Ethernet  speeds  and  CPU  clock  frequencies  over  the  past  50  years.
Figure  2-1:  With  5  ps  intervals  between  core  reallocations,  a  Shenango  runtime achieves  higher  CPU  efficiency  than  an  optimal  simulation  of a 1  ms  core  allocator.
Figure  2-2:  Shenango  architecture.  (a)  User  applications  run  as  separate  processes and  link  with our  kernel-bypass  runtime,  directly  interacting  with hardware  NIC  and storage  queues
Figure  2-1  demonstrates  that 1  ms  core  allocation  intervals must  sacrifice either  CPU efficiency or  tail  latency
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