KA655 CPU Module Technical Manual

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KA655 CPU Module Technical Manual

Order Number EK·KA655· TM·OO1

digiti'

equipment corporation

maynlrd. mlssachuaetts

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Firat E:ditioa. January ID8ll

The information in this docum~U1t is mbject to change witho\1t nGtice- and should 110t be construed as a ~ommitment by Digital Equipment Corporation. Digital F-~uipment

Corporation a..umea no responsibility for any err~rs that may appear in this document.

The 80nware deecrlbed in this document is furnished under a license and may be used or copied onl)· in accordance with the terms of such licenae.

No responsibility is Qssumed for tht, U8e or reliability of software 01. equipment that is not lIupplied by Digital Equipment. Corporation or its affiliated companios.

Copyright @1989 by Digital Equipme~llt Corporatio~~.

The following are trademaxks of Digital Equipment Corporation:

DEC Microv:'\X II RSX

DECmate MicroVAX 3500 RT

DECUS MicroVAX 3600 UNIBUS

DECwriter PDP VAX

DIBOL PIOS VAXstation

LSl·l1 ProfesBional VMS

MASSBUS Q-bU8

vr

MicroPDP-l1 Q22·bus VT100

MicroVAX Rainbow Work Processor

MicroVAX I RSTS

FCC NOTICE: The equipment des:ribed in this manual generates, uses, and may emit radio frequency energy. The equipment has ~n type tested and found to comply with

th~ limits for a ClaM A computing device PUll)\.~.nt to Subpart J of Part 15 of FCC Rules. which are deaign&d ~ provide reasonable protection against sueh radio frequ~ncy

interference when operated in a commercial envtronmezlt. Operation of this equipment in a residential area may ^C&U5einterference. in which case the user at his own expense may be requb'ed to take measures to con-act the interference.

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1 Overview

1.1 KA655 Central Processor Module ... ⁰ ⁰ ^• ^• 1-1 1.2 Clock Functions ... ⁰ ^• e o • • • • • • s • • • • • • • • • • • .. • • • • • • • • 1-5 1.3 Central Processing Unit. . . . . . . . . . . . 1-5 1.4 Floating·Point Accelerator ... ^{co •} ^• ^• ^{• •} ^• ^• ^• ^{• •} ^• ^• ^• ^• ^• ^• ^• ^• ^{• •} 1-6 1.5 Cache Memo!"), . . . .. " ⁰ ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^..^• ^• ^• ^• ^• ^• ^• ^• ^• ^e 1--6 1.6 Memory Controller ... ^{e o . •} ^• ^• ^• ^• ^• 1-6 1.7 MicroVAX System Support Functions ... 1-7 1.8 Resident Finnware . . . ^{co •} ^{.. •} ^• ^{• • •} ^• ^• ^• ^• 1-7 1.9 Q22-bus Interface ... ~ .. . .. . . • . . . . . 1--8 1.10 MS650 .. BA Metnory Modules . . . ⁰ ^..^• ^• ^• ^• ^• ^• ^• ^• 1-8 2 Installation and Configuration

2.1 Installing the KA655 ... '.' . . . . . . .. . . . . 2-1 2.2: Configuring the KA655 ... 2-4 2.3 KA655 Connectors . • . . . . . . . . . . . . .. . . 2--4 2.3.1 Console SLU Connector (Jl) . . . 2-4 2.i!.2 Configuration and Display Connector (J2) • .. . .. . .. .. . .. . . .. 2-5 2.3.3 Memory Expansion Connect.or (J8) ... 2-7 2.4 H3600·SA CPU Cover Panel ... . • . .. .. . . .. . . . 2-8 2.5 KA630CNF Configuration Board . . . . . . . . . . . . . . . . .. . 2-9

Contents-iii

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Contents-tv

3 Architecture

3.1 Central Processor . . . ⁰ ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• 3-1 3.1.1 Processor State . . . 3-1 3.1.1.1

3.1.1.2 3.1.1.3 3.1.2 3.1.3 3.1.4 3.1.4.1 3.1.4.2 3.1.5 3.1.5.1 3.1.5.2 3.1.5.3 3.1.5.4 3.1.5.5 3.1.5.6 3.1.6 3.1.7 3.1.7.1 3.1.7.2

General Purpose Registers • . . . ..

Processor Status Longword . . . : . . . Internal Processor Registers •.••.•.... ⁰ • • • • • • • • • •

Data 'tYPes ... . Instruction Set . . . . Memory Management ... . 'I'ranslation Buffer . . . . Memory Management Control Registers . . . . Exceptions and Interrupts .... ⁰ • • • • • • • • • • • • • • • • • • •

Interrupts .... ⁰ • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

Exceptions .• . • . . . . . . . . . . . . . Infonnation Saved on a Machine Check Exception ...

System Control Block. . . .. . . . . ~ . . . . • . . . . Hardware Detected Errors . . . • . . . Hardware Halt Procedure ... . System Identification ... . CPU References ... . Instruction-Stream Read References ... ⁰ . . . .

Data-Stream Read References ... . .. . .• . . . . .. . 3.1.7.3 Write References ... ⁰ . . . .

3.2 Floating-Point Accelerator ... . 3.2.1 Floating-Point Accelerator Instructions ... . 3.2.2 Floating-Point Accelerator Data Types ... . 3.3 Cache Memory . . .. . . .. . . . .. . . . . . .. . . . .. . . .. '. • . . . . 3.3.1 Cacheable References ... ..

3.3.2 First-Level Cacht: ... ~ ... . 3.3.2.1

3.3.2.2 3.3.2.3 3.3.2.4 3.3.2.5 3.3.2.6 3.3.2.7

~"'irst-Level Cache Organization ... _ ... . First .. Level Cache Address Translation ... . First .. Level Cache Data Block Allocation ... ..

First-Level Cache Behavior on Writes ... ..

Cache Disable Register ... .. . .. . . • . . .. . Memory System Error Register • .. .. . . . ... ⁰ ^• ^• ^• ^• ^• ^{. . .} First-Level Cache Error'Detection ... .

3-2

8-3 3-4

3-9 3-9

3-10 3-11 3-11 3-12 3-12 3-15 3-18 3-24 3-26 3-27

3--29 3-31 3-31 3-31 3-32 3-32 3-32 3-32 3-33 3-33 3-34 3-34 3-36 3-37 3-38 3-38 3-41 3-43

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Contents-v

3.3.3 3.3.3.1 3.3.3.2

3.3.3.3

3.3.3.4 3.3.3.5

3.3.3_6

3.3.3.7

Second·~vel Cache . . . . Second-Level Cache Organization •....•...•..

Second-Level Cache Address Translation ... . Second-Level Cache Data Block Allocation .•..•..•..

Second-Level Cache Behavior on Writes .••..•..•..

Cache Control Register .... . . . . . . • . .. . . . • . . . . . . . Second-Level Cache Error Detectiot\ ... . Second-Level Cache as Fast Memory ... . 3.4 Main Memory System ... . Main Memory Organization ... . Main Memory Addressing . . • . . . . • . . . . . . . . . . . .. . Main Memory Behavior Qn Writes ... ..

Main Memory Error Status Regi5ter . . .. . .. . .. . . . • .. . . . . Main Memory Control and Diagnostic Status Register ...

Main Memory Error Detection and CorrectiOl1 ... . 3.4.1

3.4.2 3.4.3 3.4 .. 4 3.4.5 3.4.6

3.5

Console Serial Line ... . .. .. . . . . . .. .. . .. . ^{e ..} .. .. .. 0 • • • • .. ..

3.5.1 3.5.1.1

3.5.1.2 3.5.1.3 3.5.1.4

3.5.2

Console Registers ^e ^• ^• ^{.. •} ^• ^• ^{.. •} .. .. .. • • • • .. .. • • .. .. .. • .. • • • .. • ..

Console Receive~ ControVStatus Register ... ^II ^..

Console Receiver Data Buffer ... ⁰ . . . ..

Consl)le Transmitter ControllStatus Register.. .. .. . . . . . Console Transmitter Data Buffer .. . . .. . ⁰ ^.. ^• ^..~ ^..^• ^• ^• ^• ^• ^..

Break Response . .. .. . .... ⁰ . . . II • • .. .. • • .. .. • .. • • • .. • • • • • • .. •

Baud Rate ...•...• ^& ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• Console Interrupt Specifications. . .. .. • . .. . • .. . .. .. .. .. . . .. .. ..

Time-of .. Year Clock and Timers ... ..

3.5.3 3.5.4

3.~

3.6.1

3.6.2

3.6.3

3.6.3.1

3.6.3.2

3.6.3.3

3.6.3.4 3.7 3.7.1

3.7.2

Time .. of· Year Clock .. • .. .. . . .. . .. . .. . .. .. . . . . . . .. .. . ~ . . . . .. . Interval TImer ... ..

Programmable Timers . . . . .. . . . . . . . .. . . .. .. .. .. . . . . .. . . . Timer Con trot Regi sters .. • , . . . . .. . . . . .. .. .. .. . . . .. . ..

Timer Interval Registers ... *" .. .. .. .. .. • .. ... ..

Tim~r Next Interval Registers ... ~ ... ..

Timer Inter'!\upt Vector Registers ... . . . .. .. . .. .. .. .. . . . . . Boot and Diagnostic Facility . . . .. .. . . .. . .. .. . .. • .. .. .. .. . . . .. .. . Boot and Diagnostic Register .. • .. .. .. .. • .. .. • .. .. .. .. .. .. .. • . • .. ..

Diagnostic LED Register ... .. • .. . .. .. .. .... .. . .. .. . .. .. .. . . .. .. . .

3-43 3-44 3-46 3-47 3-48 3-48 3-50 3-51 3-52

3-55 3-55 3-56 3-56

3-60 3-62 3-64 3-64 3--65

3-00 3-67 3-69 3-69 3-70 3-70 3-71 3-71 3-72

3-72

3-73 3-75

3-75

3-76 3-76

3-77

3-79

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Contents-vi

s.

7 .. 3 ROM Memory. . . .. .. . . • . . .. . • . . . .. .. .. . . .. . . . .. .. . .. . . .. .. . 3--79 3.7.3.1 ROM Socket. . . .. . . . . .. . .. . . . . . . .. . . . 3-79 3 .. 7.3.2 ROM Address Space. . . • . . . . . .. . • .. . . . . • .... 3-80 3.7.3.3 Resident Finnware Operation .. .. . .. . . . .. . . .. .. . . .. . .. . .. 3-80 3.7.4 Battery Backed-Up RAM .. . . . . . . .. .. . .. .. .. . . .. .. . .. .. 3-81 3.7.5 KA655 Initialization. .. . . .. . . . .. .. .. . .. . . . . . . .. . .. . .. . . . . . 3-81 3.7.5.1 Power-Up Initialization . . .. .. .. .. . . . .. .. .. . .. . . . . .. . . .. .. 3-82 3.7.5.2 Hardware Reset . . .. .. .. . .. . .. . . . . . . . .. . . .. . . . . . . . . 3-82 3.7.5.3 I/O Bus Initialization . . . . .. . . . . . . .. . .. . .. . .. . . .. . .... 3-82 3.7.5.4 1/0 Bus Reset Register ... ⁰ ^• ^..^• ^.. ^..^..^• ^..^.. ^• ^..^• ^{• •} 3-82 3.7.5.5 Processor Initialization ... 3-82 3.8 Q22-bus Interface. . .. .. . .. . .. . . . • . . . . .. . . . . . . . .. .. . . .. .. 3--83 3.8.1

3.8.1.1 3.8.1.2 3.8.1.3 3.8.2 3.8.3 3.8.4 3.8.5 3.8.5.1 3.8.6 3.8.7 3.8.8 3.8.9 3.8.10

Q22-bus to Main Memory Address Translation . . . . Q22·bus Map Registers ... . Accessing the Q22-bus Map Registers ... ..

Q22· bus Map Cache .. .. . .. .. .. .. .. . . _ . . . .. . .. . .. .. . . .. . . . ..

CDAL Bus to Q22·bus Address Translation ... ..

I nterprocessor Communication Register. . • . . .. . • .. . ... ..

Q22-bus IntetTUpt Handling ... ^& . . . .

Configuring the Q22-bus Map . . . . .. .. . . Q22-bus Map Bafle Address Register ... ⁶ . . . .

System Configuration Register ... ⁶ . . . .

DMA System Error Register ... ..

Q22.bus Error Address Register ... ..

DMA Error Address Register ... ..

Ei"ror Handling ... .

3-84 3-85 3-87 3-88

3-90

~90

3-92 3-92 3-93 3-93 3-95 3-98 3-99

3-100

4 KA655 Firmware '

4.1 KA655 Firmware Features. .. .. . .. . . . . .. . .. . .. . . .. .. . . . . . .. .. . 4-1 4.1.1 Halt Entry. Exit. and Dispatch ... 4-2 4.1.1.1 iIalt Entry -Saving Processor State .. '... 4-2 4.1.1.2 Halt Exit • Restoring Processor state. . . . .. .. . . . . .. . . .. 4-3 4.1.1.3

4.1.1.4

Halt Dispatch.. . • . . .. .. • . . .. . • .. • .. .. .. • • . .. .. • • • . . .. • .. .. 4...-4 External Halts . • . . . .. . . . .. . .. . . . . . .. . . .. .. • . . . . .. .. . .. 4-5

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Conte nts-vi i

4.1.2 4.1.2.1 ~

4.1.2.2 4.1.3 4.1.4 4.1.5 4.1.6

Power-Up. . . . . • . . ^~. . . ^Of ^• ^• ^• ^• ^• ^• ^.. ^• ^• ^• ^• ^{.. •} ^{. ' . •} ^• ^• ^• ^• ^• ^• ^• ^• Initial Power-Up Test ... . Locating a C.onsole Device .•.•••••.••.•••..•.. · • Mode Switch Set to Test. . • . -~ '. . . . . ~ . . . . . .. . . . . . . • . . Mode Switch Set

w

Query -. . ^~.. .. . . . . • . • . . . . • ^~. . . • . . Mode Switch

Set

to. Nonnal ... -. ... .'. . . . . . . . . . . . . . LED Coo.es . . . . • . . . . . . . . . . . . • . . ¹⁵ ^• ^• ^• ^• ^• ^• ^• ^• ^• ^, ^• ^• ^• ^• ^• 4.2

4.2.1 4.2.2 4.2.3 4.2.4-

4.2.5

4.2.6

Console Service ..•...• "'-, ~ ~~,'._.~.:!, •• " •••• ' ... ' ... .

ConSl.)le Control Characters .. . . . . . . . . . . . . . . . . . . . . . . Console Command Syntax . . . .. • . ~. . • • . ~ • • . • • .. . • . • , • Console Command Keywords . . . .. . . . .. .. . , . .. . . . . . • Console Command Qualifiers .. . .. . ~'. • .: ~'. .. .'. .' ~ : . . . . . Command Address Specifiers .. , . . . .. • . . . • • . • . . • . . . . References to Processor Registers and Memory ... ~ . 4.2.7 Cori801e--Commands ... . 4.2.7.1 BOOT ... ,', ... '.' .. D . . . 0" • 0 ' . , ' • • • • , . . . , • • , •

4.2.7.2 CONFIGURE... ... ., ... , . ~ ... . 4.2.7.3 COl\.rnNU'E ... ⁰ • • • • • • • • • • • • <I • • • • • • • • • • • • • • •

4.2.7.4 DEPOSIT ... ⁰ . . . ~ ^{• • • •}-' • • • • ---.'00 • • • • • • • • ('II

4.2.7.5 EXA.MINE . . . .. . . . . .. '. . . . . . . .. . . • • • . . . ,. . • 4.2.7.6 FIND ... ^Q . . . t . . . ..

4.2.7.7 HALT ...• ⁰ . . . 41 • • • • • • • . . . .

4.2.7.8 HELP. . . . . . . . . . ,. .. . . . . . . . . . . . . . . . . . . .. .. . . 4.2.7.9 INITIAL!ZE . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 4.2.7.10 MOVE ... . 4.2.7.11 NEXT ... . 4.2.7.12 REPEAT . . . .. . .. .. ." . . . • . . . . .. . . 4.2.1.13 SEARCH ... '" . . . ..

4.2.7.14 SET ... . 4.2.7.15 SHOW . . . " .. e • • • • • • • • • • • • • • • • • • • • •

4.2.7.16 ST.ART ... ^II>• • • • • • • • • • • • • • • • • • • • • • •

4.2 .. 7 .17 TEST ^to ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^{.. ..} ^• ^• ^• ^.. ^.. ^• ^• ^• ^• ^,.^• ^• ^• ^{eo •} ^• ^• ^• ^{• •} ^• ^• ^• ^• 4.2.7.18 UNJAM.. • . .'. • . . . .. . . .. . . . • . • . • . .. . . . • • . . . • . . 4&2.7.19 X • Binary Load and Unload ... . 4.2.7.20 ! - Comment ... ^& . . . , . . . ' . . . ..

4.2.8 Conventions for Tables 4-5

and

4-6 . . . . . . .. . • . . . ....

4-5 1-6 4-6 4-7 4-8 4-9 4-10 4-11 4-11 4-13 4-14 4-15 4-15 4-18 4-19 4-20 4-,.22 4-23 4-24.

4--26

'-28

4-29

4-30 4--12 4-33 4-35 4-37 4-38 4-41 4-44 4-48 4-49 4-52 4-52

4-54

4-55

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Co n1a nts-v iii

4.3 Bootstrapping ... . 4.3.1 Boot Devices ... ..

4AS.2 Boot Flags ... ..

4.3.3

4.3.4 4.3.5 4.3 .. 5.1 4.3.5.2

4.3.5.3 4.3.5.4

Preparing for the Bootstrap . .. .. . .. .. .. .. . .. .. . .. . .. .. . .. . . .. . . Primary Bootstrap, ~fB . . . . .. . • .. .. .. .. .. • . . .. . .. . • .. . • • ..

Device-Dependent Bootstrap Procedures ... . Disk and Tape Bootstrap Procedure ... ..

PROM Bootstrap Procedure .. .. .. .. .. .. .. . .. . .. . . . . .. . .. . . ..

Network Bootstrap Procedure ... ..

Networ!t Listening .. . . . . . .. . .. . .. .. . .. . .. . .. .. . . . . .. . . .. . 4.4 Diagnostics ... . 4.4.1 Error Reporting ... ..

4.4.2 Diagnostic Interdependencies ... . 4.4.3 Areas not Covered . .. . . .. . • • . . . • .. .. .. . . • . . .. .. .. . .. . . • .. .

" 4.5 Operating System

Restart ... .

4.5.1 Locating tl'i:e RPB ... . 4.6 Machine State on Power-Up ... ..

4.6.1 4.6.1.1 4.6.1.2 4.6.1.3 4.6.1.4 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6

Main Memory Layout and State ... . Reserved Main Memory- .. .. • • • .. .. . .. .. .. . .. . .. .. .. .. • .. .. .. .. . PFN Bitmap ... . Scatter/Gather Map .. • .. . .. .. • .. . .. . . .. .. . .. .. . . .. .. .. .. .. • • ..

Contents of Main Memory ... . eM CTL R.egisters. .. .. .. ~ • .. .. .. .. .. .. .. .. .. .. .. . • . .. .. . . .. .. . . .. • ..

First I.,evel Cache . .. .. .. .. .. .. . .. . .. . .. . . .. .. .. .. . .. . .. .. . .. . .. .. . . 'l'ranslation Buffer .. .. .. . .. .. . .. .. .. .. .. .. • .. .. .. .. . .. ... . Second I..evel Cache . .. .. .. .. .. . .. .. .. . . . . .. . . . .. . . .. .. . .. . .. .. . Halt Protectc. ... ^j Space .. . . . .. .. . .. . .. .. . .. .. .. . .. . . . . .. .. .. .. .

4.7 4.7 .. 1

4.7.2

Public Data Structures and Entry Point~.. . .. . . . .. .. . .. .. .. .. .. .

4.7.2.1

4.7.2.2 4.7.2.3

Firmware EPROM Layout .. .. . .. .. . .. .. .. . . • . . .. .. • . .. .. .. .. .. . Can-Back Entry Points ... ..

CP$GETCltAR_R4 ... . CP$MSG_ OUl'_NOLF _R4 ... .. . .. .. . .. . . ... ..

CP$REAJ}_vrrH_PBl(PT_R4 ...•.

4-58 4-58 4-60 4-62 4-63 4-66

~6

4-67 4-t18 4-69 4-72 4-73 4-74 4-75 4-75 4-76 4-77 4:-77 4-77 4.-78 4-78 4.-79 4-79 4-79 4-80 4-80 4-80

~O

4-80 4-32 4-82 4--83 4-84

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Content9-fX

4.7.3

sse

RAM Layout. . . . . . . . . .. .. .. . . . . . . • • . . • . . . . . . . . 4-85 4.7.3.1 Public Data Structures. .. .. . . . . . . . . . . . . . . . . . . . . 4-85 4.7.3.2 Finnware Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87 4.7.3.3 Diagnostic State. . . .. . .. . . . . . . . . . . . . . . . . . . . . . . • . ~7

4.7.3.4 USER Area . . . • . . . 4-87 4.8 Error Messages . . . 4--87 4.8.1

4.8.2 4.8.3

Halt Code Messages . . . . . . . .. . • . . . . • . . . . . .. . • . .. ...

Console Error Messages . .. . . . • . .. .. . . . . • • . • . . . . . • . . . VMB Error Messages . . . • . . . • . . A

KA655 Spec:ifications

4-88 4-89

4-91

A.l Physical Specifications . . . . . . . . .. . . . . . . . . . . . . . .. , A-l A.2 Electrical Specifications . . . , . . . . . . • . .. .. A-l

A.a

Environmental Specifications. . . ... , . .. . . • . • • • • . A-2

B Address Assignments

B.1 Generul Local Address Space Map. • . . . . . .. . .. . . . .. . . . . . .. B-1 B.2 Detailed Local Address Space ~fap . . . . • . • . . . • . . . B-2 B.3 External IPRs ... ⁰ ^• B-5 B.4 Global Q22.bus Address Space Map . . . , . . B-6

C Q22-bus Specification

C.l Introduction .. , ... , , ... ..

C.I.I Master/Slave Relationship . . . ⁴ ^.. ^, . . . .

C.2 Q22 .. bus Signal Assignments .. . . . . . . .. . . , • . .. • .. ^II^• ^, ^• ^• ^• ^.. ^• C.3 Data Transfer Bus Cycles .,... ... . C.3.1 Bus Cycle Protocol ... , ... . C.3.2 Device Addressing •... , , . . . .. . .. .. . .. • . • . , • .. . • . . .•..

C.4 Direct Mentory Access .... , ... . C".4.1 DMA Pro'tocol ...•..•...•.•.••.••..••..

C.4.2 Bl()(!k Mod.e DMA- . . . • . . . . . . •.•..••.•.•••.•.•••..

C.4.2.1 DATBI Bus Cycle . . . , •..

C.4.2.2 DATBO Bus Cycle ... , .... ⁰ • • • • • • • • • • • • • •

C.4.3 DMA Guidelines ... , ... " ... ..

0-1 C-2 C-3 C-6 C-7

0-7

<.'-17 0-17 0-18

0-23

0-24 0-26

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Contents-x

c.s

C.5.1 C.5.2 C.5.S C.6 C.6.1 C.6.2 C.6.3 C.S.4 C.G.5 C.G.S C.6.7 C.7 C.7.1 C.7.2 C.7.3 C/!.4 C.7.5 C.7.6

Interrupts

...

Device Priority .. " . . . . . . . .. . . .. • . • . . . • . . .. . . . ..

Interrupt Protoool ... . Q22·bus Four-Level Interrupt Configurations ... ..

Control Functions ... ~ . . . ~

Mernory Refresh ~ . .. . . .. . .. .. . . . • . .. .. .. .. .. . . . .. .. .. .. . . . . . ..

Halt . . . . Initialization ... ... ..

Power Status .. .. . . .. . . .. .. .. .. .. .. .. .. • .. .. .. . . . .. . . . • . .. . . .. . • BDCOK H ... . BPOK H ... . Power .. Up and Power-Down Protocol ... ..

Q22·bus Electrical Characteristics .. . . . . .. . .. . .. .. .. . .. . . .. .. ..

Signal Level Specifications.. . • . . . . . . .. .. .. . .. .. . . . .. . . .. .. ..

~ad Definition ... . ^It^.. ^• ^• ^• ^• ^.. .. . . . ..

120-0hm Q22 .. bus ... ..

Bus Drivers ...•. " . ^0- . . . . 0

Bus Receivers. . . . . . ^{e •} ^• ⁰ ^• ^• ^• ^• ^• ^• ^• ^{.. •} ^• ^• ^• ^• ^• ^• ^• ^• ^• ^•

BllS Tennination ... _ . ^e^{_ •} ^• ^• ^{.. •} . . . c . . . .

C.7.? Bus Interconnecting Wiring ... . C.7.7.1 Backplane Wiring ... . C. 7 ~ 7.2 intrabackplane Bus Wiring ... . . . . • . . . .. .. .. .. . C.7.7.3 Power and Ground ... , ... .

c.s

^SystemConiigurations . .. .. .. • . . . . . . . . . . .. . • . .. .. • . .. . . .. . • Power Supply Loading .. • . . . .. . . . . .. . .. . .. .. .. • .. .. .. . • • .. ..

C.B.I

C.9 Module Contact Finger Identification ... ..

D Acronyms Index

C-27 C-28 0-28 C-32 C-34

C-34

0-34 0-34 0-35 0-35 0-35 0-35 0-36 0-36 0-37 C-37 0-37 C-38 0-38 0-39 0-40 0-40 C .. -40 0-41 C-44 0-45

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Contents-.. xi

Examples

4-1 Language Selection Menu ... 4-8 4-2 Normal Diagnostic Countdown.. . .. .. .. .. . . . .. .. . .. . . . . . .. .. .. . . 4-9 4-8 Abnormal Diagnostic Countdown .. .. .. . . .. . . .. .. . .. . .. .. . . . . .. .. 4-9 4-4 Console Boot Display with no Default Boot Device ... 4-10 4-5 Diagnostic Register Dump .. . .. .. . • .. . .. . . . • . . . .. .. .. . • .. .. . • . 4-73

Fi!iJures

1-1 J<A655 CPU Module. .. . . . . . .. .. . . .. .. . . .. . .. . .. .. .. .. .. .. .. . . . . . 1-2 1-2 1<A655 Block Diagram .. . .. .. . .. .. .. .. .. .. .. .. .. . . .. .. .. .. .. .. . . . .. .. .. .. 1-3 1-3 System Level Block Diagrar'·~ ... ^c . . . It .. .. • • • .. • .. .. 1-4 1-4 MS650-BA Memory Module ... ~ ... Ît ^.. ^• ^• ^.. ^..^..^..^• ^.. 1-9 2-1 CPU snd Memory Module Placement ... ê ^{.. •} ^{.. ..} ^{.. ..} 2-2 2-2 Cable Connections . . .. . .. .. .. . .. .. .. .. .. . . .. .. .. .. .. . .. .. .. .. .. .. . .. .. .. . 2--3 2-3 &\655 Pin and LED Orientation ... " . .. .. .. . . .. . .. 2-4 2-4 H3600-SA CPU Cover Panel ... 2-9 2-5 KA630CNF Configuration Board .. .. .. .. .. .. .. . .. .. .. .. . .. . .. .. .. .. • .. 2-10 2-.6 KA630CNF J2 and J3 Pin Orientation ... ê ^{.. •} ^• .. .. .. .. 2-10 2-7 KA630CNF Jl and J4 Pin Orientation ... ".. 2-11 3-1 General Purpose Register Bit Map ... ê ^• ^• ^{.. •} ^• ^• ^• ^• ^• ^• ^• ^{.. .. •} ^• ^• 3-2 3-2 PSL Bit Map ... ^co . . . G . . . .

3-3 I nterrupt Registers ... ... .

.;-4

Infonnation Saved on a Machine Check Exception . . . . 3-5 System Control Block Base Register ... . . . .. . . . . . . 3-6 System Identification Register ... . 3-7 System· Type Register. . . .. . . • • . . . .. . • . • . .. .. .. .. .. .... . . .. .. .. • 3-8 First-Level Cache Organization ... . 3-H First .. Level Cache Entry ... ..

~~-lO First-Level Cache Tag Block ... ..

3-11 First-Level Cache Data Block ... . 3-12 First-Level Cache Address Translation ... . 3-13 Cache Disable Register ... . 3-14 Memory System Error Register ... . 3-15 Second·Level Cache Organization ... ..

3-16 Second-Level Cache Entry . " ... ..

3-3

3-15

3-18 3-24 3-29 3-30 3-:)4

3-35 3-35 3-35 3-37 3-38 3-41 3-44 3-45

(12)

Contents-xH

3-17 Second-Level Cache Tag Block. . . . . . . . . . . . . . 3-45 3-18 Seoond-Level Cache Data Block . . . _ . . . . . . 3-45 3-19 Second-Level Cache Address Translation. . . . . . . . 3-47 3-20 Cache Control Register . . . 3-48 3-21 Fonnat for MEMCSR16 • . • . . . • . . • • . . . • . . • . • . . • . . . 3-56 3-22 Fonnat for MEMCSR17 . . . • . . . • . . . 3-60 3-23 Console Receiver ControllStatus Register . . . 3-65 3-24 Console Receiver Data Buffer . . . ⁰ ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• 3-66 3-25 Console Transln.itter ControllStatus Register. . . . . . . . 3-67 3-26 Console Transmitter Data Buffer . . . . . . . . . . . . . . . . ⁰ ^• ^• 3-69 3-27 Time-of-Year Clock . ~ . . . • . . . ⁰ 3-71 3-28 Interval TImer ... "'0 • • • e o . • • • • • • • • • • • • • • • • • • • • 3-72 3-29 Timer Control Register'S . . . . • . . . .. . . . . . . . . . . . . 3-73 3-30 Timer Interval Register .. ^°⁰^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^• ^{. .}^• ^• ^• ^• ^• ^• 3-75 3-31 Timer Next Interval Register. . . . . . .. . . . 3-75 3-32 Timer Interrupt Vector Register. ~ . . . .. . . . . . . . . .. . . . . . . . 3-76 3-33 Boot and Diagnostic Register ... " ... " .. ^& ⁰ ê ê ^{.. .. •} ^• ^• ^• ^• ^" ^.. ^{.. ..} 3-77 3-34 Diagnostic LED Register ... " . .. .. . . . . . . .. 3-79 3-35 Q22-bus to Main Memory Address TrClnslation "... . .. .. .. . 3-S4 3-35 Q22-bus Map Registers ... ê ^{.. •} ^{.. •} ^.. ^• ^• ^{.. ..} ^• ^• ^• ^• ^• .. .. .. 3-86 3-37 Q22-bus Map Cache Entry ... " ... ~ . .. .. • .. . .. 3-89 3-38 lnterprocessor Communication Register ... " . . . . . . .. .. 3-91 3-39 Q22-bus ~fap Base Address Register .. . . . . . .. .. .. .. .. . .. . . . .. .. 3-93 3-40 System Configuration Register. .. . . . . . .. . .. .. . .. .. . .. . .. . • .. .. .. 3-94 3-41 DMA System Error Register ... . .. . . .. 3-96 3-42 Q22"ôbus Errol'" Address Register ... 3-99 3-43 DMA Error Address Register .. . . . .. . .. . . ⁰ ^• ^• ^• ^.. ^..^• ^• ^{.. ..} ^• ^• ^.. ^.. ^.. 3-99 4-1 VMB Boot Flags ... ⁰ ^• ^{. .} ^• ^• ^• ^• ^• ^• ^• ^• ^{. .} ^{. .} ^• ^• ^• ^• ^• ^{. .}^{. .} ^• ^• ^{. .} ^{. .} ^{. .} 4-60 4-2 Memory Layout at VMB Exit ... " .. . .. 4-65 4-3 Boot Block Format . . .. . .. . . • .. .. .. . .. .. . . . . .. . . .. . . .. .. .. . . 4-67 4-4 RPB Signature Format ... 4-76 4-5 Memory Layout after Power-Up Diagnostics ... . .. . . .. . .. .. .. .. 4-77 4-6 KA655 EPROM Layout ... 4-81 4-7 KA655

sse

^NVRAMLayout.. .. . .. • . . . . .. .. .. . .. . .. .. .. . . ... . . 4-85 4'--8 N\TRO ... ' . . . .. . • . . . .. . • . . . .. 4-86 4 ... 9 ~'VR1 ... ~ ... ^t ^• ^• ^..^• ^• ^• ^• 4-...86

(13)

Contents-xiii

4-10 NVR2 . . . . C-l DATI Bus Cycle . .. .. .. .. . . ... ., ., ... . C-2 DATI Bus Cycle Timing ... ., ... . C-3 DA'rO or DATOB Bus Cycle . .. . . .. . ., .. . .. ., ., .. . .. . .. . . . .. . .. . ..

C-4 DATO or DATOB Bus Cycle, Timing ... " . C-5 DATIO or DATIOB Bus Cycle ... . C-6 DATIO or DATIOB Bus Cycle Timing .... " ... . e-..7 DMA Prow col . . . ⁰ ^II ^• ⁰ • • • • • II • • • • • • • •

C-8 DMA Request/Grant Timing ... ... ..

C-9 DATBI Bus Cycle Timing ... e' . . . ..

C-10 DATBO Bus Cycle Timing ... ..

C-ll Interrupt Request/Acknowledge Sequence ... ..

C-12 Interrupt Protocol Timing ... ..

C-13 Position·Independent Configuration ... " ... ., ... . C-14 Position-Dependent Configuration ... ., ... ..

0-15 Power-Up and Power-Down Timing ... ^D . . . ..

C-16 Bus Line Tenninations.. . .. .. . .. .. .. . . . .. .. .. " .. .. .. .. ⁰ . . . .

C-17 Single .. Backplane Configuration ... ~ ... . C-18 Multiple Backplane Configuration ... ..

(',...19 Typical Pin Identification System ... ., .... ..

C-20 Quad-Height Module Contact Finger Identification ... ..

0-21 Typical Q22 ... bus Module Dimensions ... ..

Tables

4--87 C-9

C-11

C-12 C-14 C-15 C-16 C-19 C-20 C-21 C-22 C-29 0-31 0-33 0-33 C-36 0-39 0-42 0-43 0-45 0-46 0-47

2-1 Console SLU Connector <Jl) Pinouts.. . . . .. .. .. .. .. .. .. .. . .. . .. .. .. 2-5 2-2 Configuration and Display Connector {J2) Pinouts ... 2-5 2--3 Memory Expansion Connector <J3l Pinouts.. .. .. . .. .. . .. . .. .. .. . 2-7 2-4 H3600 .. SA CPU Cover Panel Features and Controls .. . . .. .. 2-8 2-5 KA630CNF Switch Selections ... 2-11 2-6 KA630CNF Connector and Switches .. .. .. .. . .. .. .. .. .. .. .. .. .. . . . .. ~-12

3-1 F.A655 Internal Processor Registers ... ~ . 3-5 3-2 Category ()ne IPRs.. .. .. . .. .. .. . .. . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. 3-7

3--3 Category Two IPRs.. .. . .. .. .. .. . .. .. . .. .. . . .. .. .. .. .. .. .. .. . .. .... ... 3-8 3-4 Interrupts... .. .. .. .. .. .. .. .. .. .. . . .. .. . . .. .. .. .. . .. .. .. .. .. .. .. .. . .. .. .. .. . . 3-13 3-5 Exceptions ,. . . . . . . . .. .. . . . . . .. . .. . .. . .. .. .. . . .. .. . . 3-17 3-6 System Control Block Fonnat .... . . .. . . ..'. .. . . . . . .. ... 3-24

(14)

Contents-xiv

3-7 Unmaskable Interrupts that can Caus~! !l Halt ... . 3~28

3-8 Exceptions ,that can Cause a Halt .". . . .. 3-29 3-9 CPU Read Reference Timing . . . .. . . . .. .. . . .. .. . 3-53 3-10 CPU Write Reference Timing. . . . 3-53 3-11 Q22·bus Inte!face Read Reference Timing .. " . . .. . . . .. 3-53 3-12 Q22-bus Interface Write Reference Timing .". ^{co •} ^• ^{• •} ^• ^• ^{• .. •} 3-54 3-13 Error Syndromes ...•. ~ ... ⁰ ^• ^• ^• ^• ^• ^• 3-58 3-14 Console Registers. . . .. .. . . . . .. . . . .. . .. . . . . .. . . . . . . . 3-65 3-1fi Baud Rate Select . . . .. .. • . . . . . .. . . . .. . . . .. . . . . . . . . 3-70 3-16 Q22·bu::; Map Registers . .. .. . . . . .. . . . . • . . • . 3-86 4-1 Halt. Action Summary ... 4-4 4-2 LED Codes. . . . .. . . . .. . . . .. . .. .. . . . . .. . . . .. . . .. . . . . .. . 4-10 4-3 Command. Parameter. and Qualifier Keywords. . .. .. . .. .. .. • . 4-14 4-4 Console Symbolic Addressus ... " . 4-16 4-5 Console Comman.d Summai"Y . . . .. . . . . . .. . . . . . . . . . . .. 4-55 4-6 Connole Qualifier Summary ... ' ... ⁰ ^• ^• ^• ^..^• ^• ^• ^• ^• ^• ^• 4-57 4-7 KA655 Supported Boot Devices ... ~ . .. .. . . ... ⁰ ^• ^.. ^.. ^..^{. . .} 4-59 4-8 VMB Boot FlagG. . . . .. . .. .. .. . . . .. .. .. .. . .. .. .. . • .. .. .. . .. . . . .. . 4-61 4-9 KA655 Network !~ainienance Operations Summary .. .. . . .. 4-70 4-10 HAL'!' Messages ... . . . .. .. .. .. .. . .. . . . . .. .. .. . .. .. .. 4-88 4-11 Console Error Messages ... ^It^..^..^{• • •} ^.. ^.. ^• 1-89 4-12 VMB Error :\tessages ... . . .. . .. . .. .. .. .. . .. .. . .. . . .. .. .. . . . . 4-91 B-1 VAX Memory Space ... . .. . .. . . .. .. .. .. .. .. . .. .. .. .. . .. .. .. .. • . • .. . .. .. B-1 B-2 VAX InputJOutput Space ... " . .. .. .. . . .. B· .. l B-3 VAX Memory Space .. . .. .. . .. .. . . . .. " . .. .. . . .. . . .. . .. .. .. .. • . . . .. B-2 B-4 '~Input/Output Space .. .. . . . .. .. .. .. . .. .. .. .. .. .. .. . . .. .. .. . .. . B-2 B-5 External IPRs ... B-5 B-6 Q22·bus Memory Space Map ... '. • .. . .. . B-6 B-7 Q22·bus InpuVOutput Space with BBS7 Asserted .. .. .. .. .. .. .. . B-6 0-1 Data and Address Signal A&signments ...

C-3

0-2 Control Signal Assignments. . .. .. .. . .. .. .. .. • .. . .. .. .. .. . .. .. • . .. .. .. C-4 C-3 Power and Ground Signal Assignments. .. . .. .. . .. .. .. .. .. • .. . .. .. C-5 C-4 Spare Signal Assignments .. .. . . .. . . . .. .. .. . . .. • . .. . .. . . • .. .. .. .. C-5 C,-5 Data 'l'ransfer Operations ... C-6 C-6 Bus Signals for Data T;ansfers ... ~ . . .. .. .. . . .. .. .. .. C-6 C-7 Bus Pin Identifiers.. .. .. .... .. ... ⁰ ^..^..^..^• ^• ^• ^• ^.. ^.. ^.. ^• ^..^.. ^{. . . .} 0--47

(15)

About This Manual

The KA655 CPU Module Technical Manual documents the functional, physical, and environmental characteristics of the KA655 CPU module, a.nd includes information on the MS650-BA memory expansion module.

The manual also covers the KA655·BA CPU module. designed for workstation usage. The KA655-BA is functionally equivalent to the KA655·A.A. except that it does not support multiuser VMS and ULTRIX opera'ting system licenses.

Intended Audience

This document is intended for a design engineer or applications

programmer who is familiar with DIGITAL's extended LSI ... !1 bus (Q22·

bus) and the VAX instruction set. The raanual should be used along with the VAX Architecture Reference Manual as a programmerts reference to the module.

Organization

The manual is divided h,to four chapters and four appendixes.

Chapter 1, Overview. introduces the KA655 MicroVAX CPU module and MS650 memory modules. including module features and spooifications.

Chapter 2.

Installation and Configuration,

describes

the

installa.tion and configuration of the KA655 and MS650·BA modules in Q22·bus backplanes and system enclosures_

Chapter 3.

Architecture.

describes the KA655 registers. instruction set.

and memory.

xv

(16)

xvi About This Manual

Chapter 4, KA655

Firmware,

describes the entry/dispatch code. boot diagnostics, device booting sequencia, console program, and console commands.

Appendix A, KA655 Specification". describes the physical, electrical,

a~d envil'onmental specifications for the KA655 CPU module.

Appendix B, Addresa Aalipr:lents, provides a map of VAX memory space.

Appendix C, Q22·bus Specification, describes the low-end member of DIGITAL's bus family. All of DIGITA.I:s microcomputers, such as the MicroVAX I. MicroVAX II, MicroVAX 3500, MiLTOVAX 3600, and MicroPDP-ll, use the Q22-bus.

Appendix D,

Acronyms,

lists the acronyms used in this manual.

Conventions

This manual uses the following conventions:

Convention

[x:yl

I

^Return

I

Note Caution-

Represents a bit field. a set of lines. or signals, ranging from x through y. For example, RO <7:4> indicates bits 7 through 4 in general purpoBe register RO.

Represents a range of bytes, from y through x.

Text within a box identifies a key, such aa the

I

^Return

I

^key.

Provides general information you should be aware o£

Provides infonnation to prevent damage to equipment.

Boldface small ^Jlindicates variables.

(17)

About This Manual xvii

1 Overview

This chapter provides a brief overview of the KA655 CPU module and MS650 .. BA memory modules.

1.1 KA655 Central Processor Module

The KA655 is a quad·height VAX proc-essor module for the Q22-bus.

also known as the extended LSI .. II bus. The KA655 is designed for use in high speed. real-time applications and for multiuser, multitasking environments. The K.~655 incorporates a two-level cache to maxirnize performance.

The KA655 CPU module and MS650-BA memory

modules

combine

to form a VAX CPU/memory subsystem that uses the Q22·bus to

communicate with mass storage and I/O devices, as shown in Figure 1-3.

The KA655 and MS650-BA modules are mounted in standard Q22-bus backplane slots that implement the Q22-bus in the AB rows and the CD interconnect in the CD rows. A single KA655 can support up to four MS650·BA modules. if enough Q22 .. bus/CD backplane slots are available.

The KA655 communicates with the console device through the H3600·SA CPU cover panel, which also contains configuration switches and an LED display.

Figure 1-1 shows the KA655 CPU module. Figure 1-2 shows the major fWlctional blocks of the KA655 CPU module.

1-1

(19)

1-2 Overview

MA-0410-89

Figure 1-1 KA655 CPU Module

(20)

CPU&f:PA

"'kN"'Et,40R~·

I" Of4T RQaf 1\

'''01« YE"-ORv

l·lliR-:1"lf4·~f('T

Figure 1-2 KA655 Block Diagram

Overview 1-3

(21)

1-4 Overview

IAUOfllATf&

COf#~ATDN 5WffCHES

• DItJ IT WEII' CtS'L"~

TOO" CC.OC:I<

a"TTE'h" leAf-55 PIIIIO<:E5S0R IM1'ZSl

CIllUWI1'W lW()'lEVEL CACHf

MIMQMV IIOC)fIIESS & eoNTtIIOt.

Figure 1-3 System Level Block DIagram

MA·XOM5·'.

(22)

Overview 1-5

1.2 Clock Functions

All clock functions are implemented by the CVAX clock chip. The CVAX clock chip is a 44-pin CERQUAD surface mount chip that contains approximately 350 transistors, and provides the following functions:

• Generates two MOS clocks for the CPU, the floating-point accelerator.

and the main memory controller.

• Generates three auxiliary clocks for other miscellaneous TTL logic.

• Synchronizes reset signal for the CPU, the floating .. point accelerator.

and the main memory controller.

• Synchronizes data ready and data error signals for the CPU, floating- point accelerator, and the main memory controller.

103 Central Processing Unit

The central processing unit (CPU) is implemented by the CVAX chip.

The CVAX chip contains apPi"oximately 180,000 transistors in an B4-pin CERQUAD surface mount package. The CPU achieves a 60 ns microcycle and a 120 ns bus cycle at an operating frequency of 33 MHz.. The CVAX chip supports full VAX memory management and a 4 gigabyte virtual address space.

The CVAX chip contains all VAX ,"isible general purpose registers (GPRs), several system registers (MSER. CADR, SCBB), the first-level cache (1 Kbyte), and all memory management hardware including a 28"entry translation buffer ..

The CVAX chip provides the following functions:

.. Fetches all VAX instructions.

• Executes 181 VAX instructions.

• Assists in the execution of 21 additional instructions.

• Passes 70 floating-point instructions to the CFPA chip ..

The remaining 32 VAX instructions (including H .. floating and octaword}

must be emulated in macrocode.

The CVAX chip provides the following subset of the VAX data types:

• Byte

• Word

• Longword

(23)

1-6 Overview

• Quadword

• Character string

• Variable length bit field

Support for the remaining VAX data types can be provided by macrocode emulation.

1 .4 Floating-Point Accelerator

The floating-point accelerator is implemented by. the CFPA chip.

The CFPA chip contains approximately 60~OOO transistors in a 68·

pin CERQUAD surface mount package. It executes 70 floating-point instructions. The CFPA chip receives opcode information from the CVAX chip. and receives operands directly from memory or from the CVAX chip.

The floating-point result is always returned to the CVAX chip.

1.5 Cache Memory

The KA655 module incorporates a two·level cache to maximize CPU performance.

The first-level cache is implemented within the CVAX chip. The first-level cache js a 1 Kbyte. two-way a9sociative~ write through cache memory~

with a 60 ns cycle time.

'fhe second .. level cache is implemented using 16K by 4-bit static RAMs.

The second-level cache is a 64 Kbyte, direct mapped, write through cache memory, with a 120 ns cycle time for longword transfers~ and 180 ns cycle time for quadword transfers.

1.6 Memory Controller

The main memory controller is implemented by a vtSI chip called the CMCTL. 'rhe CMCTL contains approxhnately 25,000 transistors in a 132-pin CERQUAD surfac~ mount package. It supports up to 64 Mbytes of 360 ns ECC memory. 'l~is memory resides on one to four MS650-BA memory modules, depending on the system configuration. The MS650 ..

SA modules communicate with the KA655 through the MS650 memory

interconn~ct. w}.jch utilizes the CD interconnect and a 50-pin ribbon cable.

(24)

Overview 1-7

1.7 MicroVAX System Support FunctiO:t";s

Systam support functions are implemented by the system support chip

(sse).

The chip contains approximately 83,000 transistors in an 84-pin CERQUAD surface mount package. The

sse

^provides^console^{and boot}

code support functions, operating system support functions, timers. and many extra features, including the follovling:

• Word .. wide ROM unpacking

• 1 Kbyte battery backed-up RAM

• Halt arbitration logic

• Console serial Hne

• Interval timer with 10 ms interrupts

• VP X standard time-or-year (TODR) clock with support for battery back-up

• IORESET register

• Programmable CDAL bus timeout

• Two programmable timers similar in function to the VAX standard interval timer

\1' A register for controlling the diagnostic LEOs

1.8 Resident Firmware··

The resident firmware consists of 128 Kbytes of 16-bit wide ROM, located on one 27210 EPRCl\.f. The finnware gains control when the processor halts. and contains programs that provide the following services:

• Board initialization

• Power-up self·testing of the KA655 and MS650-BA modules

• Emulation ofa subset of the VAX standa!"d console (automatic/manual

b008t~ap, al1tomatidmanual restart, and a simple command language for examining/altering the state of the processor)

• Booting from supported Q22-bus devices

• Multilingual capability

• A configuration utility

• A KFQSA programming utility

(25)

1-8 Overview

1.9 Q22-bus Interface

'The Q22·bus interface is implemented by the CQBIC chip. Thp. CQBIC chip contains approximately 40.870 transistors in a 132.pin CERQUAD surface mount package. It supports up to IG.word. block mode transfers between a Q22·bus DMA device and main memory. and up to 2-word.

block mode transfers between the CPU and Q22··bus device.. The Q22.b,.JS interface contains the following:

.. -

• A I6-entry map cache for the 8192.~entry, main memory-resident scatter-gather mep, used for translating 22·bit Q22-bus addresses into 26 .. bit main memory addresses

• Interrupt arbit"ration logic that recognizes Q22 .. bus interrupt requests BR7 ... BR4

• Q22·bus termination (240 [I)

1.10 MS6SD-BA Memory Modules

The MS650-BA memory modules are 16 Mbyte, 360 nSt 39-bit wide arrays

<32-bit data and ' ... bit ECC) inlplemented with 1 Mbit dynamic RAMs in sunace-moWlt packages. MS650-BA melnory modules are single.

qut4d-height, Q22 .. bus modules. as shown in Figure 1-4.

(26)

Overview 1-9

MS650-BA

MA·057BS8A

Figure 1-4 MS650-BA Memory Module

(27)

1~'lstallation and Configuration 2

---.---~~~' ---~---~- This chapter descrf :es how to instaU the KA655 in a system. The chapter discusses the follow: ng topics:

• Installing the KA~r;5

• Configuring the KA65~

• KA655 connectors

• H3600-SA CPU cover panel

• KA630CNF conflguration board

2.1 Installing the KA655

The KA655 and MS650·BA modules must be installed in system enclosures having Q22·bus/CD backplane slots. These modules are not com'patible with QlQ backplane slots, and therefore should on1y be installed in Q22-buslCD backplane slots.

. .

trhe KA655 CPU module must be installed ill slot 1 of the Q22-buslCD

backplan~ (Figure 2-1). MS650-BA menlory modules must ~e installed in slots immediately adjacent to the CPU module. Up to four MS650·BA modules can be installed, occupying slots 2, 3, 4, and 5 respectively. A 50-pin ribbon cable is used to connect the KA655 CPU module and the MS650-BA memory module(s)$ as shown in Figure 2-2.

'2-1

(28)

2-2 InstaUation and Configuration

/It B C 0

SLOT 1 I ^I ^clo

-

KA6S5 CPU

SlO'r 2 02Z bus

,

INTERCONNECT

-

^MSGSONO'

StOT3 I

-

^~ MS6!50NO 2

SLOT" I

-

^MS650NO^:3

SLOTS I ... MS6!~NO C

SLOT 6 I

SLOT 7 I

SlOT8

I

SLOT 9

I

SLOT 10

I

SLOT "

SLOT 12 d, I t

I,

... ,. lions .. 14

Figure 2 ... 1 CPU and Memory Module Placement

(29)

MS6$O

MEMORY

MOOULES

Figure 2-2 Cable Connections

Installation and Configuration

2-3

KA6j5 C9U MODllLE

UA XOOS3 ,t

(30)

2-4 InstaUat~on and Configuration

2.2 Configuring the KA655

The following parameters must be configured on the KA655:

• Power-up mode

• Break enable switch

• Console serial line baud rate

These parameters are configured using either the H3600 .. SA CPU co"..'er panel, or the KA630CNF configuration board.

·2.3 KA655 Connectors

The KA655 uses three connectors (Jl, J2, and JS) and four rows of module fingers (A, Bt Ct and D) to commun~~ate with the console devjcet

main memory, and the Q22-bus. The slot pinouts on the fingers of the I{A655 are listed in Appendix C.

The orientation of connectors Jl. J2, and J3. and the LED indicator..! is shown in Figu\~ 2-3. .

9 19 49

• ••••••••••••••••••••••••

... _____ ._._. -_._._-_.-_._1

•••••••••• ^ooo~o^. • ••••••••••••••••••••••••

to ^{' } ] O} ²

t

⁸⁴²¹ ⁵⁰ ²

[

DC OK DlAGNOSTtC

Jl J2 LEO LEOS

Figure 2-3 KA655 Pin and LED Ori.n~tlon

2.3.1 Console SLU Connector (J1)

J3

,on 1 . ;Hll ,.,:. 1Q{,~ R'

The lO-pin consQle SLU connector provides the connection between the KA655 and the console terminal. Jt is connected to the inside of the H3600·SA CPt] cover panel by a lO-conductor cable~ or directly to connector JS of the KA630CNF configuration board. A cable from the outside of the H3600 .. SA or from Jl of the KA630CNF provides the external connection to the console tenninal. Table 2-1 lists the Jl . . pinouts.

(31)

Installation and Configuration

2-5

Table 2-1 Console SLU Connector (J1) Pinouts

01 Data terminal ready

02 GND Ground

03 SLU OUTL Console SLU output from the KA655

04

GND

Ground

05

GND

^Ground

()6 Key (no pin)

07 SLV IN + Console SLU differential inputs to the

08 SLU IN· ^KA655

09

GND

^Ground

10 +12V Fused +12 volts

2.3.2 Configuration and Display Connector (J2)

The KA655 has no jumper or switch settings to change or set. The module is configured through switches on the H3600-SA CPU cover panel, or the KA630CNF configuration board. The 20-pin configuration and display connector is connected to the inside of the H3GOO·SA CPU cover panel by a 20-conductor cable, or directly to connector J2 of the KA630CI\TF configuration board. Table 2-2 lists the J2 pinouts;.

T,.ble 2-2 Configuration and

Display

Connector (J2) Pinouts Pial _8ipal

01 GND

02 GND

03 GND

04 CPUCODEOL

05 CPUCODEIL

M_nin•

Ground Ground Ground

CP'U rode <01:00>. This 2 .. bit code can be configured only by Qaing switches 7 and 8 on the KA630CNF configuration board (Figure 2-7).

CPU code <01:00> configuration:

00 Normal operation 01 Reaerved

10 Reserved 11 Reaenred

tTbe KA655 moclule has 4.7K ohm pull.up resistors for the 8 input signals (pins' and 5.

13 throuSh 15. and 17 throU8h 19).

KA655 CPU Module Technical Manual