MANUAL Processor

STD 7000

7801

808SA Processor Card

USER'S MANUAL

•

e

•

AU MPm?*, 44444444M, MP $ 4¥4A4¥Gq; A

7801

808SA Processor Card USER'S MANUAL

9/81

• == ^{• l.} =e;.UOMC.4$iapapntiu"",*n=w#li <Ii:;;;.,;,;;;. n 111.,; gin"",".; ...

o

o

o

- - - ' - - -

•

•

>¥

7801 USER'S MANUAL TABLE OF CONTENTS SECTION

1 2

3

4

5

6

7

APPENDIX A B C

TITLE

INTRODUCTION THE STD BUS STD BUS Summary 7801 Pin Ut i 1 i

za

t ion Control Bus Signal Table Processor Status Codes 7801 SPECIFICATIONS Power Requirements

Drive Capability and Loading Clock Generator

Timing and Waveforms Mechanical

Environmental

80SSA ARCHITECTURE AND INSTRUCTION SET SOSSA Programming Model

SOSO/SOSSA/Z80 Compatibility 808SA vs S08S Characteristics STO Instruction Mnemonics

Instruction Cross-Reference Table SOSSA Instruction Set

Interrupts

PROGRAM INSTRUCTION TIMING Introduction

WAIT States DMA Mode

Instruction Timing Table Programmed Timing Example

MEMORY AND I/O MAPPING AND CONTROL Memory Addressing

12K-Byte Onboard Memory Input/Output Port Addressing Onboard Serial I/O Lines

PROGRAM AND HARDWARE DEBUGGING Microprocessor Logic State Analysis

Instruction Dia9no~tic Tables M82S System Analyzer

7801 STRAPPING OPTIONS

SCHEMATIC AND ASSEMBLY DIAGRAMS MS2S SYSTEM ANALYZER DATA SHEET

PRO-LOG CORPORATION A

^\c<cG\

⁰³

FORM NO. 101905

* 4 44 i ¥ # PW4 fPA r" , ^{Itt . , WMiiF ,$liCea:} ,,::"U,;===, _'"x,,; it "A#II 'Ii X==';;4M&4NMUiI&iM_

PAGE

REV

A

I

,I

I

SECTION ONE PRODUCT OVERVIEW

SOSSA PROCESSOR CARD

This card combines a buffered and fully expandable 808SA microprocessor withonboard RAM and PROM sockets.

The 7801 includes 1 K byte of RAM with sockets for up to 4K. and sockets for up to 8K bytes of ROM or EPROM. An STO BUS system using the 7801 card can be expanded to full 808SA memory and I/O':

capability The 7801 STO BUS interface may be disabled for OMA •

FEATURES

• 80SSA Processor

• 4096 bytes RAM capacity onboard

• 1024 bytes RAM included (211 4 L type)

• 8192 bytes ROM capacity onboard (2716 type)

• 3 State Address, Data, Control Buses

•

• Power-on· reset or pushbutton reset input

• Five interrupts

• Serial 1/0 lines

• All lC~s.-socket.ct

• Single +5V operation

.7801: 6_25 MHz crystal, 320ns time states .7801-1: 6_ 144MHz crystal, 325.5ns time states

• External clock input option

.. M.RO-

INTRa"

IUMO-

WAITRO'

CNTRl.

(IXT CLKI

J1 INTIRRUPT AND SIR.AL.

',0 ACCESS

",OCIISOR IOI5A

DATA IUS

ADORIIS

loSTATI IUS IU,.,'RS

loSTATt IUS IU"U

,.

7101

SHADING INOICATIS SOCKETS ONU 'INDICATES ACTIVI LOW l.OGIC

FIGURE ONE: 7801 BLOCK DIAGRAM

DATA IUS (00007) AOORISS IUS (AOoA1S'

~l..o<!.\IC."

MIMRO- lORa-

WR' MCSYNC- INTAK' IIUSAIC' STATUS O' STATUS l ' STSRn_TO

M'MlX' 10UIt·

I I

I I

10 I

o

I~---~----~~---~---~----~----~

II

PRO-LOG CORPORATION A

^{REV A} SHT '),., I'II---'---~

_

^{_ L _} OF ^{_ __l}

FOAM NO. 101905

o

•

SECTION TWO - THE STO BUS

The STO BUS standardizes the physical and electrical aspects of modular a-bit microprocessor card systems, providing a dedicated, orderly interconnect scheme.

The STO BUS is dedicated to internal communication and power distribution between cards, with all external communication made via I/O connectors which are suitable to the app1 ication. The standardized pinout and 56-pin connector lends itself to a bussed motherboard that allows any card to work in any slot.

As the system processor and primary system control card, the 7801 is responsible for maintaining the signal functionality defined by the STO BUS standard.

A complete copy of the STO BUS standard is contained in the SERIES 7000 STO BUS TECHNICAL MANUAL, available from Pro Log Corporation, 2411 Garden Road, Monterey, California 93940.

STO BUS Summary

The 56-pin STO BUS is organized into five functional groups of backplane signals:

1. Logic Power Bus pins 1-6 2. Oata Bus pins 7-14 3. Address Bus pins 15-30 4. Control Bus pins 31-52 5. Aux i 1 a ry Power pins 53-56

Figure , shows the organization and pinout of the STO BUS with mnemonic function and signal flow relative to the 7801 Processor card:

COMPONENT SIDE CIRCUIT SIDE

PIN MNEMONIC SIGNAL DESCRIPTION PIN MNEMONIC SIGNAL DESCRIPTION

FLOW FLOW

LOGIC 1 ·SV In +S Volts DC (Bussed) 2 ·SV In ·S Volts DC Bussed)

POWER 3 G~O In Digital Ground (Bussed) 4 GNO In Digital Grol.;~C Bussed)

BUS 5 -5V -S Volts DC 6 -5V -5 Volts DC

7 03 InlOut Low Order Data Bus 8 07 InlOut High Order ::Ja:a Bus

DATA 9 02 InlOut Low Order Data Bus 10 06 InlOut High Order Ca:a Bus

BUS 11 01 InlOut Low Order Data Bus 12 OS InlOut High Order Cata Bus

13 DO InlOut Low Order Data Bus 14 04 InlOut High Order Ca~a Bus

15 A7 Out Low Order Address Bus 16 A15 Out High Order A-:dress Bus

17 A6 Out Low Order Address Bus 18 Al .. Out High Order Ao:lo:lress Bus 19 AS Out Low Order Address Bus 20 A13 Out High Order AIjClress Bus

ADDRESS 21 A4 Out Low Order Address Bus 22 A12 Out High Order AOdress Bus

BUS 23 A3 Out Low Order Address Bus 24 All Out High Order Address Bus

25 A2 Out Low Order Address Bus 26 A10 Out High Order Address Bus

27 Al Out Low Order Address Bus 28 A9 Out High Order Address Bus

29 AO Out Low Order Address Bus 30 A8 Out High Order Adljress Bus

31 WR· Out Write to Memory or I/O 32 RD· Out Read to Memory or I. 0 33 lORa· Out I/O Address Select 34 MEMRO- Out Memory Address Select

35 10EXp· Out 110 ExpanSion 36 MEMEX· 'Out Memory ExpanSIon

37 REFRESH· Refresh Timing 38 MCSYNC· Out CPU MaChIne Cycle Sync

CONTROL 39 STATUS 1· Out CPU Status '. 40 STATUS O· Out CPU Status

BUS 41 BUSAK" Out Bus Acknowledge 42 BUSRO· In Bus ReQuest

43 ^INTAKo Out Interrupt Acknowledge 44 INTRO" In Interrupt ReOuest 45 WAITRO" In Walt ReQuest 46 NMIRO' In Non-MaskaOI~ I nterru pt 47 SYSRESET" Out System Reset 48 PBRESET' In Push Button ~eset 49 CLOCK" Out Clock from Processor 50 CNTRl· In AUX TimIng 51 peo Out Priority Chain Out 52 PCI In PriorIty Cha,'" In

POWER 53 AUXGNO AUX Ground (BUSSed) 54 AUXGND AUX Grouna 8'.Jssea)

BUS 55 AUX+V AUX POSitive (-12 Volts DC) 56 AUX-V AUX NegatIve -'2 Volts DC,

·Low L.evet Active Indicator

_-2.---:

^-rl\l.

^{Srp ~U} S

FORM NO. 101905 \O~~

: t AM#. WM¥4#¥W AMMM4¥AN4¢4fTM P¥ gp4M¥4QM44¢ AA 4M4hP4\#¥4#MMii# Wf#4¥MA 4T\ A A¥4A AWPW¥M4P4%?44I WM, A%#i,4 P# 4%4 P P #4 4 r

STO BUS Pin Utilization by 7801

Since the STO BUS standard does not specify timing or require that all available pins be used, the timing and signal allocation assumes many of the characteristics of the microprocessor type used. The characteristics of the 7801 are dictated by

its 8085A microprocessor, with LSTTL buffering added to enhance the card's drive capability., The b~ffers decrease memory and I/O access time slightly.

The allocation of STO BUS lines for the 7801 is given below.

1. Logic Power Bus: +5V (pins 1,2) and Logic Ground (Pins 3,4) supply operating power to the 7801. Pins 5 and 6 are open.

2. Data Bus: Pins 7 through 14 form an 8-bit bidirectional 3-state data bus as shown in Figure 2 High level active data flows between the 7801 and its peripheral cards over this bus. When the 7801 fetches data from its onboard memory sockets, this data also appears on the STD Data Bus.

With the exception of Direct Memory Access (DMA) operations, the 7801 controls the direction of data flow with its I1EHRQ,r" 10RQi" RD"" WR'':, and INTAK~r, control

signal outputs~ Peripheral cards are required to release the data bus to the high impedance state except when addressed and directed to drive the'data bus by the 7801. Note that the low-order address bits (AO-A7) are multiplexed on the

Data Bus.; AO-A7 appear on 00-07 while MCSYNC* is active. The 7801 releases the Data Bus when BUSAK* is active in response to BUSRQ*, as in DMA operations.

3. Address Bus: Pins 15 through 30 form a l6-bit 3-state address bus as shown in Figure 2 . The 7801 drives high level active l6-bit memory addresses over these lines, and 8-bit I/O port addresses over the eight low-order address 1 ines (AO through A7 on pins 15, 17, 19, 21, 23, 25, 27 and 29).

The 7801 releases the Address Bus when BUSAK* is active in response to BUSRQ~~,

as in DMA operations.

4. Control Bus: Pins 31 through 52 provide control signals for memory, I/O, interrupt, and fundamental system operations. Figure 3 summarizes these signals and shows how they are derived from 8085A signals.

The 7801 releases the Control Bus during BUSAK* in response to BUSRQ*, except for the following output signals: MEHEX,;',, 10EXPi" BUSAK;'" ^CLOCK'~', PCO.

5. Auxilary Power Bus: Pins 53 through 56 are not used by the 7801 and are electrically openc

The 7801' meets all of the signal requirements of the STD BUS standard. Detailed

timing information and specifications are in Section 3.

I

PRO-LOG CORPORATION

FORM NO. 101905

A

^{REV A SH T OF "-f}

o

o

o

e

:MNEMOt-J I C PIN IN/OUT FUNCTION IHOW DERIVED, 808SA NAME iWR ! 31 Out# Write to memory or I/O I [WR1;]

:RD*

I

^{32 Out#} Read from memory or I/O [RD*]

IORQ1 33 OUT# AO-A7 hold valid I/O address [IO/M*]*

MEMRQ"; _I 34 OUT# AO-A15 hold valid memory [IO/M*]

i I address ^,

10EXP* 35 OUT I/O expans~on control User-removabl~ ground MEMEX* 36 OUT Memory expansion control User-removable ground

REFRESH~': 37

-

: (Not used) ^I E 1 ec t rica 1 1 y open

MCSYNCr; 38 OUT# One transition per machine [ALE] * cycle; undecoded status

STATUS 1* 39 OUT# Undecoded status; Note 1 [S 1] * STATUS 0".

..

_I 40 OUT# ndecoded status, Note 1 [SO] * BUSAK* ^: I 41 OUT Acknowledges BUSRQ* i [HLDA] *

;BUSRQ* 42 IN

.

Bus request (DMA); synchronous I [HOLD]*

processor halt and 3-state

l

! _!

; driver disable

I

_...

- --

^...

----

^{. ..---}

i I NTAKr~ ^: 43 OUT# ^! Acknow 1 edges I NTRQ* and rep 1 ace~[ I NTA;'~]

e ⁱ

(MEMRQ* . RD*) to read

i ! : interrupt vector

IINTRQ* ^I 44 ^: IN Maskable interrupt request [I NTR]'':

WAITRQ* 45 IN Synchronous processor ha 1 t [ROll ~

NMIRQ* 46 IN Nonmaskab1e interrupt request j [TRAP] 1;

SYSRESET~':

!

47 ^OUT# System power-on and pushbutton ;[RST]*

reset one-shot output ^I

PBRESET~I; 48 IN Pushbutton reset input ^{:[R~': ]}

CLOCK;': 49 OUT Time State tlock ( 1 /2 cry s ta 1 I [CLOCK]

* -

user optional

,- frequency)

i

jumper connection

CNTRL~'; 50 IN External clock input (2 times :~1 - user optional jumper Time State Clock frequency) ¹ connection

i --i

-

^~

IPC I /PCO 52/51 IN/OUT Priority chain INote ~

* Low 1 eve 1 active

# Output buffer disabled when BUSAK* active [] Denotes equivalent Bo8SA signal name NOTES: t. See Figure 4 for status information.

2. Trace on 7801 connects PCI to PCO to maintain chain continuity.

FIGURE 3 ^: 7801 CONTROL BUS SIGNALS

PRO-LOG CORPORATION A

^{\OCDq,O~ REV A SHT} OF ^S

~nA'" Nn tOtQOS

- ,enM4==4I

"i.

t""; " j,,.ij IW W ^:UM 4$ M , Mg., 4 p;; . . . 1,'4

7801 Processor Status: MCSYNC*, STATUS 0*, STATUS 1* Signals

MCSYNC*, STATUS 0*, and STATVS 1* signals provide encoded status information which is peculiar to the 808SA microprocessor. These signals are useful for displaying processor status in logic sign~l analyzers, and can be used to drive certain peripheral chips and systems designed to work with the 808SA specifically.

The use of these signals is not recommended in systems where microprocessor device-type independence is a design goal.

MCSYNC* serves a dual function. Its leading edge denotes the approximate start of a machine cycle (Section 3 ). Counting the MCSYNC* transitions allows a

logic signal analyzer to select a specific machine cycle within a mUlti-cycle instruction for analysis.

The lagging edge of MCSYNC* occurs when a stable memory line address or I/O port address is present on the

sro

Data Bus. The 808SA device mu1.tiplexes jots low order address lines (AO-A7) during time state TI; -tne address information is followed by data in subseq~ent time states within the machine ~ycle. The lagging (rising) edge of MCSYNC* is used on the 7801 to latch thp low order address.

MCSYNC* is equivalent to the 80SSA's ALE (Address Latch Enable) output signal.

STATUS 0* and STATUS 1", can be decoded externa 11 y to i dent i fy the type of machine cycle in progress as shown in Figure 4:

SEE NOTE I MACHINE CYCLE TYPE :STATUS 0* STATUS ^I'~ ,MEMRQ'" I ORQi;! RDi, ; It/R,'t \ I NTAKi:

2

3

NOTES: I.

2.

3.

4.

I

Read instruction opcode 0 o

I Read memory except opcode 1 Wr i te in memory

Acknowledge INTRQ*

Acknowl edge NM I RQ": and interrupts S.5,6.5,7.5 Bus idle during ADP (Add

to H,L pair) instruction HALT instruction

o

o

o

o

a

o

o

FIGURE 4: MACHINE CYCLE STATUS SIGNALS

I

⁰

I

^{1 j 0 I 1 I 1}

o

o o

o

o

I

i

1 1

! i

I

o

^I

1,

I

*low active: Active

= a

Inactive = 1 o

The states shown for MEMRQ": and fORQi, during interrupt acknowledge cycles are those produced by the 808SA dev ice. For the ea r lie r 8085, the MEMRQi: and 10RQ":

states are reversed.

The Data Bus is idle during the second and third machine cycles machine cycles for the ADP ins t ruc t ion (I rrte 1 mnemon i cis DAD). No MCSYNC* CAlE~") signa 1 is generated during these cycles. ((808SA only).

Processor pins 10/M*, RD*, WR* are in the high impedance state.

Timing for STATUS 0* and STATUS 1* is similar to Address Bus timing (Section 3).

For additional information, refer to the 808SA manufacturer's literature.

PRO-LOG CORPORATION A

^{\o~qo~ REV A SH T OF I.p}

FORM NO. 101905

o

o

o

o

•

•

SECTION 3 - 7801 SPECIFICATIONS

Power Requirements

! RECOMMENDED OPERATING LIMITS i ABSOLUTE NONOPERATING LIMITS ^I MIN MAX UNITS

I

PARAMETER

I

MIN TVP MAX

0 5.50 ^I Volts Vcc (Note 1) 4.75 5.00 5.25

I

!

! Ampere lice (Note 2) : 11.00 1.40

I

!

FIGURE 5: 7801 POWER SUPPLY SPECIFICATION NOTES: 1. In order to guarantee correct operation, the

following power supply considerations apply:

a. Vcc rise must be monotonic, rising from +0.50 Volt to +4.75 Volts in 10 ms or

less.

b. If Vcc drops below +4.75 Volts at any time it must be returned to less than +0.50 Volt before restoration to the specified operating range.

2. Icc specification assumes that all EPROM and RAM sockets on the 7801 are loaded. Subtract

75 rnA per 2716 EPROM and SOmA per 2114L RAM for each device not used. (typical values)

I ,

I

f i i

Both the 8085A and 2114L devices require 10 milliseconds minimum after initial power-on for stabilization of internal bias oscillators. The 780l's power-on reset one-shot provides adequate stabilization delay, only if Vcc risetime is less than 10 milliseconds.

Drive Capability and Loading

The 780)IS STD BUS Edge Connector Pin List (Figure 6 ) and Serial I/O and Interrupt Socket Jl (Figure 7 ) give input loading and output drive capability in LSTTL loads as defined by the SERIES 7000 TECHNICAL MANUAL.

In general, input lines and disabled 3-state outputs present 5 LSTIL loads maximum (one LSTTL or MOS input plus 4.7K pullup resistor). Output 1 ines can drive

a minimum of 50 LSTIL loads. Pins which are unspecified in Figures 6 and 7 are electrically open.

Exceptions to· the general loading rules are:

PRO-LOG

FORM NO. 101905

a. WAITRQ* input, which is 15 LSTTL loads.

b. PBRESET* input, which is 1 uF typical in parallel with 2 LSTTL loads •

c. CLOCK* output, which can drive 10 LSTTL loads.

d. PCI and PCO, which are connected to each other but to nothing else on the 7801.

REV

CORPORATION A

A ^{SHT OF}

ⁱ

FIGURE 6 7801 STD BUS EDGE CONNECTOR PINOUT AND LOADING

o

STD/7801 EDGE CONNECTOR PIN LIST

PIN NUMBER PIN NUMBER

OUTPUT (LSTTL DRIVE) OUTPUT :(LSTTL DRIVE)

INPUT (LSTTL LOADS) INPUT (LSTTL LOADS)

MNEMONJC MNEMONIC

+5 VOLTS

^IN

2

^{1 IN}

+5 VOLTS

GROUND

^IN

4 3

^IN

GROUND

-5V 6 5 -5V

D7 s

^'iO

8

7 50 5

D3

D6

5 50

10

9 50 5

02

D5

₅

so 12 11

_{50 5}

01

D4

₅ c;n

14 13

50 5

DO

A15

_{5 'iO}

16 15

50 5

A7

A14

_{5 'in}

18 17

_{50 5}

A6

A13

₅ 50

20 19

50 5

A5 o

A12

₅ 50

22 21

_{50 5}

A4

A11

₅ 50

24 23

50 5

A3

A10

₅ 50

26 25

50 5

A2

A9

₅ 50

28 27

50 5

A1

A8

₅ 50

30 29

50 5

AO

RD*

₅ 50

32 31

5J 5

WR*

MEMRO*

₅ 50

34 33

⁵⁾ 5

IORO*

MEMEX*

^{(GROUND) OUT}

36 35

^OUT

IOEXP*

^(GROUND)

MCSYNC*

(ALE~~) 5 50

38 37 REFRESH*

STATUS O·

(SOi: ) 5 50

40 39

⁵⁰ 5

STATUS 1·

^{(S 1 ;':)}

-.

BUSRO*

(HOLD;':) 5

42 41

⁵⁰ 5

BUSAK*

^(HLDAi':)

INTRO*

(I NTRi:) 5

44 43

^{50 5}

INTAK*

^(INTAi:)

NMIRO·

(TRAPi: ) 5

46 45

¹⁵

WAITAO*

^(READY)

PBRESET*

^(R;':) 1 iJF

48 47

^{50 5}

SYSRESET*

_(RST;':)

CNTAl * -

EXT eLK IN

50 49

10

ClOCK*

PCI

IN

52 51 OUT PCO

AUX GND 54 53 AUX GND

AUX-V 56 55 AUX +V o

*Designates Active Low Level Logic () Designates equivalent 8085A pin names

•

e

•

Jl SERIAL I/O AND INTERRUPT PIN OUT AND LOADING PIN NUMBER PIN NUMBER

OUTPUT ( LSTTL) OUTPUT .( LSTTL)

I NPUI_ (LSTTL) INPUT (LSTTL)

INTERFUPT 7.5

~

*

^{5 1 16 OUT GROUND}

I NTERF'.UPT 6.5

*

^{5 2 15 OUT GROUND}

INTERRUPT 5.5

*

^{5 3 14 OUT GROUND}

SOD": 50 _{4· 13} OUT GROUND

SID": ₅ 5 ^{12 OUT GROUND}

(SPARE) 6 1 1 OUT GROUND

(SPARE) 7 10 ^{OUT GROUND}

(SPARE) 8 9 OUT GROUND

*Low Level Active

FIGURE 7 : SERIAL I/O & INTERRUPT CONNECTOR PINOUT AND LOADING NOTE: Pads are provided at spare pins for user-connected signals

PRO-LOG CORPORATION A

FORM NO. 101905

.= ____ " ..

^{* __} ":.45:::",,; l6.,ml:I,#' #.$ 4T4¥ $

REV

A ^SH r:..,

OF

AlMA ( ",iLk It .-

Clock Generator

The 7801 's 8085A microprocessor has an internal clock oscillator that serves as the primary timing element in a 7801-based system. The oscillator's output is divided by two to produce the time state clock. The time state clock's period is the shortest program-related period of interest in the system. Instruction execution times are computed as whole multiples of the time state clock period (see Section 5 ).

The 7801 is shipped with a crystal installed which sets the system's time state period. The only difference between the 7801 and 7801-1 is the resonant frequency of th i s crys ta ^{1 •}

If desired, the user can substitute a different crystal or replace the crystal with a TTL-compatible clock signal generated externally. Details of this option are given in Append~x A. The frequency/period characteristics of the crystal or external clock signal are shown in Figure 8

! CRYSTAL OR

I

^RESULTING

i

EXTERNAL CLOCK TIME STATE

FREQUENCY PERIOD COMMENT

I

!

6.250 MHz ^j 320.00 ns 7801 operating rate;

I

I

fastest allowable rate for

8085A with onboard crystal

i

6.144 MHz 325.52 ns 7801-1 operating rate;

I

compatible with SBC-type ^!

I

systems and divisible to i I standard Baud rates I 6.000 MHz 333.33 ns _I Fastest recommended externall , _I user-provided clock signal

I

,

I

wi th crys ta 1 removed

I

I

I I

1.000 MHz 2000.00 ns

I

SlowesX allowable crystal or:

i

_{j j} external clock signal for ^I

8085A ^!

! I ^,

FIGURE 8 7801 Clock Oscillator Freguency Summary

"

PRO-LOG CORPORATION A

\0<0'\03 ^REV

A

::lRM NO. 101905

o

o

o

SHT ID

OF

e

0

•

Timing Specifications (Based on 320ns ± 0.05% time states)

An understanding of the 7801's signal timing characteristics is necessary for the selection of speed-compatible memory devices, I/O functions, and other peripheral STO BUS cards, and for real-time logic analysis of 7801-based STD BUS card systems.

The 7801 's timing characteristics are established by its 808SA microprocessor, with add it i ona 1 de 1 ays added by LSTTL bu ffe.rs. The bas i c opera t ions performed

by the 7801 and the signals controlling these operations are shown in Figure 9.

SIGNALS OPERATION WAVEFORM

MEMRQ*, RD*& Read from memory Figure

AO-Al5

MEMRQ1: , WR*,& Write to memory Figure

AO-A15

10RQ*, RD*

.&

Read from an input port Figure AO-A7

10RQ*, WR*

.&

Write to an output port Figure AO-A7

I NTAK* Read an interrupt instruction Figure (in response to INTRQ* only)

FIGURE 9 ^: BASIC 7801 OPERATIONS

.&

Note that· the fa 110wi ng signa 1 s. a 11 have i dent i ca I t imi ng character i st i cs:

ADDRESS BUS A8-A 15 MEMRQ~':, I ORQ*, STATUS O~':, STATUS 1 *.

The waveforms on the following pages show timing measurements as a 5-1etter code as follows:

__ ---First letter is always T for Timing measurement.

--- Second letter is the abbreviation of the signal which starts the measurement. (0 = Data Bus)

10 11 10 11 10

- - - Third letter is the condition of the start signal. (V=Val id)

Ir

Fourth letter is the abbreviati"on of the signal which

, ,U

ends the measurement. (R=RD~':)

TOVRH+4---Fifth letter is the condition of the end signal. (H=High) For example, rDVRH stands for· lime from .Q.ata y'alid until ~D~':(READ) High inactive.

Specific abbreviations are given in the Legend on each page of the specificat1on .

*

Denotes low level active signal

PRO-LOG CORPORATION

FORM NO. 101905

'_."'iM,.'4I, ^{t I I ",4R i 4i#A4 4A4 lap ,m}

A

^{REV ~ SH T II OF}

tt¥A4lAM . • ' iA;a; ^I II '- ; $\4

M.

^{Q.« Ii; .. $.,. iMwur}

\

I

'II I 'II

"

I:

I(

II

I

I_ ^,V\AC~ (,'JE.. c,ycLE..-· ~!

I ^J

I _T1

^{I TZ-}

^T3

)

71

! j

J ^{\ / \}

^{I \ i \}

CLCG~* ,

\ ^/

^\

\

,

,

-

_._ .. _-^...

_----

^- --- - - " /

:' r""~~("r- ,.

t

f"'r..,-.,; \ -... __ . J ....

VAL.l !) ,..\t!> ~',. .::-

-+

,:..:'; -A:!, __ I, ^/1\ I

I ^•

^{::-:~1 z,y .... 1}

I---

^{T~HM- ~!}

.'vl

=

^{i\'\ ~:;: 7 -~.: 'j . -I-}

::.~ :.;: I~ .:.'

\"

^I _! ^{( ---}

I ___

^{.. ~RL II~ T~l.DV ;...}

51

~:~ ~r

*

,

!

: : .' • ....,;'~ ~(~ ^.,!.'

I:

I - . 1 ^{~/.· .. :-.}

T~L.l:>~ -sa-;4-

1...-

^I

i \

~

^...

(~

^{... I}

i ^{.,I ,.--t I}

", ~L

I

( pAr.to. I

~... .. .... -" _~~ .

J

. J r. ...

.

Ao-.47 ^0(..1;-

t--. -'--'--'

^{.. - \}

.

^to!

" -

SYMBOL' PARAt1ETER iMIN MAX UN ITS !

L:2GEND _t ^;

Address val id before bus data

!

⁵²⁵

j

TAVDV ^{l !}

A Any Address :must be va 1 i d ns

i

j ~. AO-~~t;

.

I ^I

I

_;0 Any Data ^{E~RQ'-: ,I ~db':} TRlDV ^I RD* act ive before bus data must: ^{i I} _{\ 250} i ^{, l i}

(

i

I

be val id ns I

1 i ne 00-07 ^I , _I i

I ^I TRlRH RD* pulse width 385 ^!

I

:R RD": 1 i ne \ i , ns

:l low state TDVRH Data _setup time ^{i 100 ,} _i ^! _ns i _I

! ^j

I

H High state ^{, I}

I TRHDV Data hold time 0 ^I

:v

^{Va lid} ; , ^{I 1 ns I I}

iZ High TRlDZ ^, Data bus dr i vers OFF (high ^{I I}

I ^\ j ^f

I imEedance i impedance read mode) after 0 ⁱ ns RD,': active

I

TRHAX Address hold time after ^{RDi: I t} !

i nact ive ¹³⁵ !

i

^ns

FIGURE 10: READ TIMING - MEMORY FETCH, INPUT PORT, INTERRUPT INSTRUCTION NOTE: In onboard memory read operations (Section 6) the Data Bus does not enter

the high impedence read mode; instead the ⁷⁸⁰¹ drives data fetched from the onboard memory sockets onto the Data Bus to facilitate logic state analysis. The access time for onboard memory devices may not exceed the values shown for TAVDV and TRlDV shown above.

•

PRO-LOG CORPORATION A

^{lOic'10~ REV SHT 12.J OF}

~ORM NO. 101905

o

o

o

o

e

•

•

I'I!.- ,-, ^{. 1 '} 11'",'

.u:

^{' . ,' ...} -^{~. L •} .

T:L I

_-?

,<

'--

^{; ...."}

\

/ I ^\ ! ^\

- - J

..

^{, I}

\ \

- I ' -

~~/---;V

----1i

/":'::"/:1 A:;.':.'(·~ - 7\'-_ _ _ _

... ^~·~r -._

- '-'-

^{: ....}

... -.

~ .

... ^,.. ...

LEGEND

. A. Any address

. I

^{Line AO-A 15}

MEMRQ'~ '. I ORQ*

o

^{Any data}

1 i ne 00-07

\.J

I

^{WRi: 1 i ne}

H i High state V Va 1 id X Don't care

... - - - TAVw H

---aa..!

~

^-r-/

"* :"':========-TD-V-""-J-!-, ---~-I..._jw ^:f

^{i-; D}

x.~ I

~tr-,.-.':.O-.--A.-7-0-v~-! ---·t-])-.4-i-i4:--!;-~-1

.-.. --- .. ---.----..

- - - \ j r - - - -

- \ 0'---J""·---

SYMBOL

I

PARAMETER ; MIN , MAX UNITS ^;

j

!

i I

ns i TAVWH

I

Address va 1 i d before wr i te

I

strobe (WR* r is i ng edge)

I

625

.. TOVWH Data setup time and WR* pulsewidth; 400 ^{1 ns}

l

^TWHDX Data (and address) hold time

i

^{85 ! ns}

FIGURE 11 : WR~TE TIMING - MEMORY AN~ OUTPUT PORT

PRO-LOG CORPORATION A

FORM NO. 101905

-_=_"A4 ^{EAM I} := , :

REV

A

#.4WM;_MA##MMU "";';"'+'

SHT \0

OF

..

A 1"' :... ~' • • • , .

,£1;. '. . -~ _ :: J>

- \

LEGEND

I

A

.

Any address

! 1 ine AO-A1S,

/'11 4 c.,:.J/;'j E - , - ! . . -^{~,# ' . ' - • t:}

T1. T2.

I

IW

I

\

^{J I}

^/ \

\~_/

SYMBOL TAVQL

j

l....-rc.LoJ-/

- - - -

PARAMETER

Auo('ess val id before WA I TRQ-;'t mus t ee ac t i ve to insert

,

•

/

I MIN

,

185

~~EMRQ* , 10RQ": WAIT state in this cycle ⁱ iQ ' ',,;'AITRQ*

jc

CLOCK":

iL Low state

!H High state

Iv

^{Val id}

TQLCL WA I ^TRQ~I: setup time pr ior to i clock transition fn T2(for ^; 110

!

first WAIT state) or in TW.

TCLQH \vAITRQ* hold time after clock i ^t

transition in T2(for first

a

WAIT state) or

.

ⁱⁿ TH. I

NOTE: ^MEMRQ~'t and 10RQ": timing is identical to Address Bus timing.

FIGURE 12: WAITRQ~': TIMING (One WAIT state show!!.l

..

^;

- 1

~-;1'

J ~ .1

\

_•

_,~

_ ... _-.J\I..---

v

MAX

,

\

I

I I

I

I I /

UNITS ns

ns ns

I

_t

I !

I i

! I

o

01

WAIT REQUEST

I

The WAITRQ* input allows the 7801 to enter the WAIT state in any memory, I/O or interrupt acknow~edge cycle while a slow memory device responds, or until a control function such as an analog-to-digital converter finishes. WAITRQ*

can also be used to single-step the 7801.

PRO-LOG eORPORATION A

^{REV A}

FOAM NO. 101905

!

1° I

SHT H

OF

o

•

B !

I

!

L H

z

V I I

Address Bus, Data Bus \ Contro 1 Bus!

Low state

I

High state High imp- edance Va 1 i d

I'

) I

I

J

.,..",

I~

\

\

,'" A 'J-i f; \ / =.

I

^T3

J

\

T

_i

^{\\-__ ._l}

:1 I

^{I I i}

^f

^,

--..---_

^...

^_-

;

^~f

^I

~--~~---~:~

~ ^~

^·1

^(~5

^_______

^f

Ti<LCH~ - - -

. . 1'1(L.B~. i~ - a - rJ(~S'/ ..--,-_ _ _

p/::WrN \J-~~---~---.----\(

/ ' " - - - -

---~

! SYMBOL PARAMETER MIN MAX UNITS

TQLCH TCHQH TKLCH TKLBZ

BUSRQ* active prior to T3 (BUSRQ* setup time) BUSRQ* active after start

of T3 (BUSRQ* hold time)

I

BUSAK* asserted prior to TH (Note 1)

;

200

I

I

o 125 ;

i ns

;

!

ns

L

ns : Address Bus, Data Bus, and

most Control Bus (Note 2) outputs float after BUSAK;'~

50 ns is asserted, allowing DMA operations

TKHBV

I

^! 7801 resumes drive 6n the

Address, Data, and Control

I

50 I ns

I

Busses after BUSAK* goes inactive

NOTES: 1. TH time states are clock periods during which the 7801 has relinquished the STO BUS, allowing DMA operations to proceed with an alternate controller card. Equivalent to 808SA Hold mode.

2. The following Control Bus 1 ines are floated when

BUSAK~\- is active: WR*, R01:, 10RQ;':, MEMRQ":,

I

! I

MCSYNC1:, STATUS 11:, STATUS 0":, INTAK:;':, SYSRESET,':, DATA BUS 00-D7? ADDRESS BUS AO-AlS.

FIGURE 13 : 7801/STO BUS TIMING FOR DIRECT MEMORY ACCESS (DMA) OPERATIONS

PRO-LOG CORPORATION A

^{REv A SH T I£) OF}

FOAM NO. 101905

_ " • • #:=,;0.;'1#; q 4

-

^{4.4 :at 4F i. Aa; #4 4#41$}

Mechanical

The 7801 meets all STO BUS mechanical specifications. Refer to the Series 7000 Technical Manual for outline dimensions.

If the Interrupt and Serial I/O access socket Jl is used, one additional open card slot on the component side of the 7801 may be needed for ribbon

cable access, depending on the connector and cable type used.

Environmental

PARAMETER

Free Air Ambient Operating Temperature Absolute Nonoperating Free Air Ambient Temperature

Relative Humidity, Noncondensing

Absolute Nonoperating Relative Humidity, Noncondcnsing

MIN TYP

o

25 -40

5

o

FIGURE 14: ENVIRONMENTAL SPEC1FtCATIONS

MAX UNITS 55 ^°Celsius 75 ^°Celsius

95 %

100 %

PRO-LOG CORPORATION A

^REV

^A

FOAM NO. 101905

SHT J~

OF

o

o

4·\,,;

o

()

•

"

(

,

1

• I I

• I

..

,

_, , , ,

1 1

,

I I 1 I

SECTION 4 - 808SA ARCHITECTURE .Atm INSTRUCTION SET

.

co LOM STA STP

RWM MEMOR¥

.:

)

I ' ~=, ~ ==~i=:l I

^{'7 -}

I

^V

A~M ~CA~L~U~;tl~~~l:JjrE":j::r]i!t~I/I~O~D~A~T~A~:

If 5, :P' 17Tns: 5 4 3 2 I 0 ^{_ _}

~

^{_ _}

~--:::--f ~I:"=:---".

4 t - - - - 4

~T.c: ^{II.!tU RRAJ "\ - :}

I "" -

^~~=====:

I . __

Mr-A.,.S_K,...,. ... _ ~C RRA ' 1 1 - - - .

r ' ^{1 LOM 1} .£.t---_-e

~~--r_ ... --J ALM ^It

I ^~

^LDMII

^tJ~DR

^•.

R,,~=:;;;:;;:;:;:;::l==l-.

ri ^\T'C~ I'OU'H" PS.Pl

I

OUTPUT PORT

.... ---~,

I

^{r __}

~<?!:~~!~!

^_______

~A~:~ _______ ^~ __ L_J --- ^---~:jl

INST~UCTION

^:

I '

^IPA:'

IN.T_E

J":':RIR~U_PT

^_____

.·~>~I:..I_./~I, ^--- j irr ^{i II - T~I-} _:.:-:...;.-:. __ ::e

• 2 JPN _ ~

'-=-

43 t - - - - e

+. _I ~ ₍ .... ---_ ... , ₁ 2 t - - - - e

ROM • 1 1 l l - - - e

; I"

^{JP - I STACK 1 ~ - -}

MEMORY ~~ :

"'----j;---.,---t--",

^ADDRESS:

I

INPUT PORT

: OIRECTI JI ." 1 "

.. ADDRESS' RT . . , +1 INOfRECT'1

: t-~~~-"...1 ^401)01(5S 1

I

1 ^{1 1} ADDRESS ^PROGRAM 1514:13;12:"'10:9.8 ^{I . !} 7:6:5'4')'2:1 O~ ^{ADDRESS • I 1}

I

. . , • COUNTER r 1

"" t . .; . . . • I ,

'---.-~---"""---

_I ^{- ---}

^{_ --~----J I--- ___ ~---_-J )}

I

....

..

^{~ ~}

I ^~~ I

FIGURE 15 : 808SA PROGRAMMING MODEL

Data flow

Memory or Port Address

PRO-LOG CORPORATION A

^{REV A}

FORM NO, 101905

.1'_;; .. #:;"4#;;""::::.,3£ ; Ma;mW# P .4# 4

SHT 11

OF

- - - _ ^.. _--_._---_ .. _-_ ^... _-_ ^..

808SA Architecture

The 808SA processor (figure 15 ) consists of an 8-bit instruction register, a 16-bit Program Address Counter, a 16-bit Stack Pointer, six 8-bit General Purpose Registers that can be paired to form three 16-bit Register Pairs, and an 8-bit Arithmetic/Logical Unit (ALU) containing an 8-bit Accumulator Register and a 5-bit Flag Register. An 8-bit interrupt regis.ter provides serial

I/O capability and additional interrupt control.

Instruction Register: The 8-bit Instruction Register provides storage and decoding for instruction operation codes (opcodes) as they are read from program memory.

The second and third words of mUltiple word instructions bypass the Instruction Register. These provide either data or addressing information and are routed directly to the General Purpose Registers, the Accumulator, or the Program Address Counter as required.

o

Program Address Counter: The 16-bit Program Address Counter (PC) keeps track

·of the location of the next instruction to be executed from the program memory.

The PC increments automatically for each instruction word; the JUMP and RETURN instructions modify the PCls address content by loading a new address.

Stack Pointer: A l6-bit auto-counting Stack Polnter (spl provides the address of

the subrout i ne return address stack loc~t i on ~n RAM memory·. The SP is us·ed for

0

controll ing subroutines and interrupts, and can also be used to "push!' and

"pull" data in memory at high speed.

Subroutine return addresses are automatically stored on the stack when a

jump-to-subroutine (JS) instruction is executed, and are retrieved when return (RT) instruction is executed. Interrupts in 808SA systems are generally

treated as subroutine jumps.

All of the General Purpose Register Pairs and the Accumulator/Flag Register pair can be stored and fetched from memor-y using the SP as an indirect address

register. 16-bit data movement and address autocounting in the SP result in fast data manipulation.

The address stored in the SP can be brought into the HL Register Pair for arithmetic manipulation with the ADP HL,SP instruction and restored with the

LOP HL,SP instruction.

General Purpose Register~: Consists of six 8-bit regfsters (S.C,O,E.H,L) which can be treated as three 16-bit Reqister Pairs (SC. DE. HL). Soecific

instructions regard them as individual registers, while other instructions treat them as pairs. These registers are useful for the temporary storage of 8-bit or 16-bit data, and as pairs can be used as indirect address registers.

Data can be transferred from register to register, register to memory, memory to register, or from the second -word of the instruction (8-bit) or second and

third words of the instruction (l6-bit pair). Individual registers and register

0

pairs can be incremented, decremented, and added. In 16-bit arithmetic, a carry . propagates automatically from the lower register to the higher.

PRO-LOG CORPORATION A

^{IOCDCloS REV A SHT} OF ^I~

FORM NO. 101905

o

•

The HL register pair forms the indirect memory address for register, arithmetic, and logical operations with any memory location. HL can also be exchanged with pair DE or the top of the stack and loaded to the Stack Pointer and Program Counter (indirect jump). The BC and DE pairs can also be used for indirect addressing with the Accumulator (A) register only.

Arithmetic/Logical Unit (ALU): The Accumulator (Register A) and five status flags (Register F) with associated control logic form the ALU. The ALU provides add and subtract with or without carry/borrow), and the logical operations AND, OR, Exclusive OR, complement, and shift. Arithmetic/logical operations are performed on the A register using data from the other registers, or from memory,· or from the second byte of the instruction (immediate data).

The A regtister can be decimally adjusted and rotated right or left, with or without the carry bit.

All I/O operations involve the data contained in Register A (unless the system uses memory-mapped I/O).

The Flag Register contains five status flags (see figure 20):

1. Carry/Borrow (C) 2. Zero Result (Z) 3. Sign (S)

4. Pa r i ty (p)

5.

Decimal half-carry (D)

Toe C,Z,S,P flags can all be tested by the conditional jump and return instructions for decision-making. The 0 flag affects the decimal-adjust operation. The C flag is affected by arithmetic, logical, and rotate

instructions and has its own set, clear, and complement instructions.

Memory: The .16-bit register pairs, the Stack Pointer, and the Program Counter allow addressing of 64K bytes of memory which can be any combination of ROM and RAM (See Section 6). RAM is required for stack

operations to allow the use of subroutines and interrupt. The instruction set allows long direct addressing (16-bit memory address is part of the

instruction); immediate (8-bit or l6-bit data is part of the instruction); and indirect (16-bit memory address is contained in one of the register pairs or the Stack Pointer). I/O port addressing is always direct unless I/O is memory- mapped. Figure 21 shows automatic memory allocation for certain instructions.

Interrupt: The 808SA has a single maskab1e, vectorab1e interrupt (STO BUS line INTRQ":) and a single nonmaskable, implied vector interrupt (NMIRQ1:).

Three additional maskable, implied vector interrupts are provided at the

7801 's J1 socket. Figure 23 shows the addresses implied by these interrupts, and figure 22 shows how the interrupt mask is programmed for these inputs.

The vectorab1e INTRQ* input, when acknowledged, causes INTAK*to be asserted.

INTAK* is used to read an instruction (supplied by the interrupting device) into the processor via the Data Bus. This may be any 1, 2, or 3-byte instruction;

if a multibyte instruction, fNTAK* will be asserted one or two more times after the opcode to read in the entire instruction. (The instruction's execution time is unchanged when supplied during interrupt.) The Jl (jump-to-interrupt,

or RESTART) instructions are an efficient means of handling up to eight interrupts without polling; see Figure 19B

PRO-LOG CORPORATION A

^REV

^A

^{SH T}

l"

OF

FORM NO. 101905

_u.a.ina, ",MitiNi,dUM # ... $4 qp $, $.$ Aau A 4;. J 4 .A"U:: . M,M i· Q ,j A" ij - I ._.$4'- .... ,; M4;;:;;0

Inputs and Outputs (I/O): Separate I/O instructions and control signals allow I/O to be mapped separately from memory. The OPA instruction writes data from the Accumulator to the specified output port, and the fPA instruction re~ds data from the specified input port to the Accumulator. Ports are specified by the second byte of the IPA or OPA instruction, allowing up to 256 each input and output ports. In the 7801, all ports are provided on external cards.

One serial input line and one serial output line are provided at the 7801 's Jl interface connector. These lines are operated by the LOA I and LDI A instructions as shown in Figure 22.

8080/808S/Z80 Compatibility

Both the 8085 and the Z80 instruction sets include the 8080's instructions as a subset. Programs wr j tten exc Ius i ve 1 yin 8080 assembly codes will execute norma 11 y

in the 8085 and the z80. Note, however, that all three processors require a dif- ferent number of time states in some instances to execute otherwise identical

instructions, and in most systems the processors use different time state clock frequencies. Accordingly, programmed timing (such as count-and-test time delays) witl require modification when running an 8080 or Z80 program on an 8085, and vice versa.

Note that only the 8085 instructions which are not part of the 8080 set are the LOA I and LOI A (RIM and SIH) serial I/O and interrupt mask instructions.

S08SA vs 8085 Characteristics

The 8085A differs from the 8085 in the following characteristics:

a. ALE (Address Latch Enable; ALE*

=

MCSYNC* on the 7801)

In the 8085A, ALE is not generated during machine cycles 2 and 3 for the ADP (Add ^Pair) instruction only (equivalent to Intel mnemonic DAD). This applies only to the ADP instruction.

In addition, ALE does not float during reset, DMA operations, and in WAIT states. Note, however, that MCSYNC* is floated on the STD BUS during DMA opera t ions.

b. INTERRUPTS

The 808SA asserts 10RQ* during any interrupt acknowledge machine cycle, while the 8085 asserts MEMRQ*.

In the 808SA, NMIRQ* (nonmaskable interrupt, or Trap) does not destroy the previous iriterrupt enable status. The LOA ( instruction (load accumulator with interrupt mask register, or RIM) must be executed

after response to NMIRQ* in order to restore the previous interrupt status.

PRO-LOG CORPORATION

~ORM NO. 101905

A

^{REV A SHT} OF ^2.0

o

o

o