Packaging and Integration Activities at Laboratoire Ampère -- CPES Seminar

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Packaging and Integration Activities at Laboratoire

Ampère – CPES Seminar

Cyril Buttay

To cite this version:

Cyril Buttay. Packaging and Integration Activities at Laboratoire Ampère – CPES Seminar. Doctoral. United States. 2019. �hal-02968805�

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Packaging and Integration Activities at

Laboratoire Ampère

CPES Seminar

Cyril Buttay Laboratoire Ampère, Lyon, France

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Who am I?

2004 PhD Electrical Engineering (Lyon, France)

2005 – 2007 Research associate

(Sheffield and Nottingham, UK) 2008 – 2019 Researcher at CNRS

(Lyon, France)

Since 2019 Senior Researcher (eq. Prof.) at CNRS

You can contact me at ◮ _{cyril.buttay@insa-lyon.fr} ◮ _{(540) 998 6694}

◮ _{Office 151, Whittemore Hall}

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Where do I come from?

◮ _{Laboratoire Ampère}

(named after André-Marie Ampère, born in Lyon) ◮ _{180 people (Faculty, Support, PhD students)} ◮ _{Academic research lab focusing on:}

◮ _{Bio-engineering, biology}

◮ _{Automation, System engineering} ◮ _{Electrical Engineering}

◮ _{EE activities:}

◮ _{High voltage engineering} ◮ _{WBG devices design and test} ◮ _{Magnetics (material/design)} ◮ _{EMC, Packaging, Integration.}

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Outline

Packaging for High Temperature (> 200◦_C)

Thermal stability of SiC devices High Temperature Packaging

New Packaging Structures for Power Modules

Macro-post Micro-Post PCB Embedding

Packaging for High Voltage

Fail-to-short Packaging for SiC High Voltage Substrates

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Outline

New Packaging Structures for Power Modules Macro-post

Micro-Post PCB Embedding

Packaging for High Voltage Fail-to-short Packaging for SiC High Voltage Substrates Conclusion

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Operating Temperature Limits

0°C 500°C 1000°C 1500°C 2000°C 2500°C 3000°C 10 V 100 V 1 kV 10 kV 100 kV 1 MV Junction temperature Breakdown voltage Silicon 3C−SiC 6H−SiC 4H−SiC 2H−GaN Diamond

Source: C. Raynaud et al. “Comparison of high voltage and high temperature performances of wide bandgap semiconductors for vertical power devices” Diamond and Related Materials, 2010, 19, 1-6

Some limits:

660℃ Aluminium melts ≈300℃ Die Solder melts 200 – 250 ℃ Silicone gel degrades

≈200℃ Board solder melts

◮ _{For Wide-Bandgap devices, limits set by packaging} ◮ _{Additional packaging issues with thermal cycling}

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Outline

Packaging for High Temperature (> 200◦_C) Thermal stability of SiC devices

High Temperature Packaging

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High temperature behaviour of SiC devices – [1, 2]

Static Characterization of 490 mΩ JFET

0 2 4 6 8 10 12 Forward voltage [V] 0 2 4 6 8 10 12

Forward current [A]

-50 ◦_C -10 ◦_C 30 ◦_C 70 ◦_C 110 ◦_C 150 ◦_C 190 ◦_C 230 ◦_C 270 ◦_C 300 ◦_C

VGS = 0 V , i.e. device fully-on

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High temperature behaviour of SiC devices – [1, 2]

Static Characterization of 490 mΩ JFET

0 2 4 6 8 10 12 Forward voltage [V] 0 2 4 6 8 10 12

Forward current [A]

-50 ◦_C -10 ◦_C 30 ◦_C 70 ◦_C 110 ◦_C 150 ◦_C 190 ◦_C 230 ◦_C 270 ◦_C 300 ◦_C

VGS = 0 V , i.e. device fully-on

50 0 50 100 150 200 250 300 Junction temperature [C] 0 20 40 60 80 100 120 140 Dissipated power [W] 2.0 A 4.0 A 6.0 A 8.0 A 10.0 A

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High temperature behaviour of SiC devices – [1, 2]

Thermal Run-away mechanism ◮ _{The device characteristic} ◮ _{Its associated cooling system} ◮ _{Two equilibrium points: one}

stable and one unstable ◮ _{Above the unstable point,}

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High temperature behaviour of SiC devices – [1, 2]

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High temperature behaviour of SiC devices – [1, 2]

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High temperature behaviour of SiC devices – [1, 2]

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High temperature behaviour of SiC devices – [1, 2]

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High temperature behaviour of SiC devices – [1, 2]

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High temperature behaviour of SiC devices – [1, 2]

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High temperature behaviour of SiC devices – [1, 2]

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High temperature behaviour of SiC devices – [1, 2]

50

0

50 100 150 200 250 300

Junction temperature [C]

0

20

40

60

80

100

120

140 Dissipated power [W]

2.0 A

4.0 A

6.0 A

8.0 A

10.0 A

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High temperature behaviour of SiC devices – [1, 2]

50

0

50 100 150 200 250 300

Junction temperature [C]

0

20

40

60

80

100

120

140 Dissipated power [W]

1K/W

2K/W

4.5K/W

2.0 A

4.0 A

6.0 A

8.0 A

10.0 A

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High temperature behaviour of SiC devices – [1, 2]

Buttay et al. “Thermal Stability of Silicon Carbide Power JFETs”, IEEE Trans on Electron Devices, 2014

100 150 200 250 300 350 time [s] 30 40 50 60 70 80 power [W] current changed from 3.65 to 3.7 A

Run-away SiC JFET:

◮ _{490 mΩ, 1200 V} ◮ _R

ThJA = 4.5 K /W ◮ _{135 ℃ ambient} ◮ _{On-state losses}

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Outline

Thermal stability of SiC devices

High Temperature Packaging

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High Temperature die attaches

The problem with solders

S tr engh /Hardn ess Homologous Temperature 0.4 0.6 1 Properties little aﬀected by

temperature Creep range

Unable to bear engineering loads Solders operate in this region 0 Source: ❤tt♣✿✴✴✇✇✇✳❛♠✐✳❛❝✳✉❦✴❝♦✉rs❡s✴t♦♣✐❝s✴✵✶✻✹❴❤♦♠t✴ Homologous temperature: T_H = TOper[K ] TMelt[K ] Example: ◮ _{AuGe solder: T} Melt = 356℃ = 629 K ◮ _T H = 0.8 ➜ TOper = 503 K = 230 ℃ ◮ _{High temperature solder alloys not practical}

◮ _{Need to decorrelate process temperature and melting point:}

◮ _{Sintering (solid state, process below melting point)}

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High Temperature die attaches

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High Temperature die attaches

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High Temperature die attaches

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High Temperature die attaches

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High Temperature Die Attaches –

PhD A. Masson

◮ _{development of the} sintering process ◮ _{Nano-particles paste}

from NBE Tech ◮ _{Evaluation of many parameters}

◮ _{Sintering pressure} ◮ _{Surface roughness} ◮ _{Thickness of stencil} ◮ _{Substrate finish. . .}

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High Temperature Die Attaches –

PhD A. Masson

◮ _{Once set, process is robust}

0 10 20 30 40 50 60 70 A’ B C D E F J N O T

Shear strenght [MPa]

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High Temperature Die Attaches –

PhD A. Masson

◮ _{Once set, process is robust}

Ag SiC Cu 0 10 20 30 40 50 60 70 A’ B C D E F J N O T

Shear strenght [MPa]

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High Temperature Die Attaches –

PhD S. Hascoët

◮ _{“Pressureless” sintering process} ◮ _{Based on micro-particles}

◮ _Findings:

◮ _{Oxygen is necessary} ◮ _{Bonding on copper (oxide)} ◮ _{Standard Ni/Au finish not ideal}

◮ _{Confirmed by several teams} ◮ _{weak bonds at Ag/Au interface}

◮ _{Bond strength lower} ◮ _{Porosity higher}

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High Temperature Die Attaches – [3]

◮ _{All-sintered assembly} ◮ _{Half-Bridge structure} ◮ _{SiC JFETs}

◮ _{Integrated gate drivers (Ampère)} ◮ _{Ceramic capacitors} 49.0 48.8 48.6 48.4 time [µs] 50 0 50 100 150 200 250 Vou t [V] 0.2 0.0 0.2 time [µs] 310°C 0 1 2 3 4 5 Iout [A ] 310°C

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High Temperature Die Attaches –

Silver migration, R. Riva [4] 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 1E-3 1E-2 1 /t ( h -1) Electric Field (V/mm) Without parylene Parylene SCS HT T = 300°C Stop parameter

◮ _{Causes: electric field, high temperature and oxygen} ◮ _{Large differences between similar test vehicles:} ◮ _{Short life without encapsulation (100–1000 h)}

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High Temperature Die Attaches –

Silver migration, R. Riva [4] 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 1E-3 1E-2 1 /t ( h -1) Electric Field (V/mm) Without parylene Parylene SCS HT T = 300°C Stop parameter

◮ _{Causes: electric field, high temperature and oxygen} ◮ _{Large differences between similar test vehicles:} ◮ _{Short life without encapsulation (100–1000 h)}

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Conclusion on Packaging for High Temperature

SiC devices can operate at high temperature (>300℃) ◮ _{With efficient thermal management!}

◮ _R

Thmust remain low

Silver sintering for high temperature die attaches ◮ _{Compatible with standard die finishes}

◮ _{High thermal/electrical performance}

◮ _{Research: long-term behaviour at elevated temperature}

◮ _{pressureless processes may be a good model} ◮ _{not presented here: cycling and storage tests [5, 6, 7]}

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Outline

Macro-post Micro-Post PCB Embedding

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Outline

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New Structures – Macro post

(R Riva) [8, 9] Vbus OUT GND JH JL

◮ _{Two ceramic substrates, in “sandwich” configuration} ◮ _{Two SiC JFET dies (SiCED)}

◮ _{assembled using silver sintering} ◮ _{25.4 mm×12.7 mm (1 in×0.5 in)}

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New Structures – Macro post

(R Riva) [8, 9] SiC JFET Alumina 0.2 mm 0,3 m m 0.16 mm 0,1 5 m m Copper

0.15 mm _Source _Gate _Source

Drain

0.3 mm

Scale drawing for 2.4×2.4 mm2_die

◮ _{Etching accuracy exceeds} standard design rules

◮ _{Double-step copper etching for} die contact

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New Structures – Macro post

(R Riva) [8, 9]

plain DBC board

◮ _{Final patterns within 50}_{µm of desired size} ◮ _{Two designs, for 2.4 mm and 4 mm dies}

◮ _{Die top metallized (PVD) with Ti/Ag} ◮ _{Total copper thickness 300}_µm,

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New Structures – Macro post

(R Riva) [8, 9]

plain DBC board 1a - Photosensitive resin coating

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New Structures – Macro post

(R Riva) [8, 9]

1b - Exposure and Development

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New Structures – Macro post

(R Riva) [8, 9]

2 - Etching

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New Structures – Macro post

(R Riva) [8, 9]

2 - Etching

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New Structures – Macro post

(R Riva) [8, 9]

2 - Etching 3a - resin coating

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New Structures – Macro post

(R Riva) [8, 9]

3b - Exposure and Developpment

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New Structures – Macro post

(R Riva) [8, 9]

3b - Exposure and Developpment 4a - Photosentive ﬁlm

laminating

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New Structures – Macro post

(R Riva) [8, 9]

3b - Exposure and Developpment 4a - Photosentive ﬁlm laminating 4b - Exposure and Development

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New Structures – Macro post

(R Riva) [8, 9]

3b - Exposure and Developpment 4a - Photosentive ﬁlm laminating 4b - Exposure and Development 5 - Etching

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New Structures – Macro post

(R Riva) [8, 9]

3b - Exposure and Developpment 4a - Photosentive ﬁlm laminating 4b - Exposure and Development 5 - Etching 6 - Singulating

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New Structures – Macro post

(R Riva) [8, 9]

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New Structures – Macro post

(R Riva) [8, 9]

◮ _{Good form factor achieved using the two-step copper etching process} ◮ _{Satisfying alignment}

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Outline

Macro-post

Micro-Post

PCB Embedding

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New Structures – Micro posts

(B Mouawad) [10, 11]

◮ _{First studies during L. Ménager’s PhD}

◮ _{Copper posts growth on die (electroplating)}

◮ _{Original die/DBC assembly technology: SnCu diffusion bonding}

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New Packaging Structures – Micro posts

Direct Copper-to-Copper Bonding [12] Parameters: ◮ _{SPS press} ◮ _{Cu/Cu bonding} ◮ _{5 or 20 min} ◮ _{200 or 300℃} ◮ _{16 or 77 MPa}

◮ _{Very good bond, without any interface material} ◮ _{All configuration but one yield to bonding}

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New Packaging Structures – Micro posts

◮ _{Very good bond, without any interface material}

◮ _{All configuration but one yield to bonding}

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New Packaging Structures – Micro posts

◮ _{Very good bond, without any interface material}

◮ _{All configuration but one yield to bonding}

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New Structures – Micro posts

(B Mouawad) [10, 11] 10 15 20 25 60 90 120 150 180 210 240 ◮ _{“Wafer”-level process}

◮ _{Based on copper electroplating}

◮ _{Assembly of DBC/die/DBC “sandwiches”} ◮ _{No damage to dies observed}

Die Die

Micropost

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New Structures – Micro posts

(B Mouawad) 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Forward Voltage [V] 0 50 100 150 200 F or w ar d C ur re nt [A ] To 247 Sandwich package

◮ _{Higher elec. resistance than expected}

◮ _{Due to seed layer/die topside interface} ◮ _{Would not happen with suitable dies}

◮ _{Simple and reproducible process}

2000 4000 6000 8000 10000 12000 14000 16000 Int ens it y 02 T i Al2 AlO2 T iO CuO

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Conclusions on “Sandwich” ceramic structures

◮ _{Several sandwich configurations:}

◮ _{Solder [13, 14]} ◮ _{Silver sintering}

◮ _{Direct Cu/Cu bonding (Micro-posts)} ◮ _{More suited to direct liquid cooling}

◮ _{Solid/liquid interface}

◮ _{Homogeneous compressing force} ◮ _{No issue with flatness}

◮ _{Remaining issues:}

◮ _{Dies topside finish}

◮ _{Mechanical relief structures}

◮ _{Intrinsic thermo-mechanical reliability}

(65)

Conclusions on “Sandwich” ceramic structures

◮ _{Direct Cu/Cu bonding (Micro-posts)}

◮ _{More suited to direct liquid cooling}

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Conclusions on “Sandwich” ceramic structures

◮ _{Direct Cu/Cu bonding (Micro-posts)}

◮ _{More suited to direct liquid cooling}

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Outline

Macro-post Micro-Post

PCB Embedding

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New Structures – PCB Embedding [17, 18]

CDM LDM LDM EMI Filter VDC VS Is LPFC PFC PPB LCM LCM CCM CCM

◮ _{Bidirectionnal, Power Factor Converter for 3.3 kW applications} ◮ _{Designed through an optimization procedure [15, 16]}

◮ _{Based on SiC power devices} ◮ _{180 kHz switching frequency} ◮ _{4 interleaved cells}

◮ _{Discussed here: PFC cell}

(69)

New Structures – PCB Embedding [17, 18]

Physical Structure Inductor PCB (4.5 mm-thick)

}

Driver PCB (4.5 mm-thick) TIM (0.2 mm-thick) Dies PCB (0.7 mm-thick) Heatsink (25 mm-thick)

}

TIM (0.2 mm-thick) TIM (0.2 mm-thick) HF Die Magnetic Core 3-PCB structure

◮ _{Magnetic component on top} ◮ _{Heatsink on bottom}

( natural convection)

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New Structures – PCB Embedding [17, 18]

Two board structures are used: Thin PBC (1 mm)

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

for bare dies

Thick PCB (4 mm) for SMD devices and inductors

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New Structures – PCB Embedding [17, 18]

for bare dies

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New Structures – PCB Embedding [17, 18]

for bare dies

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New Structures – PCB Embedding [17, 18]

for bare dies

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New Structures – PCB Embedding [17, 18]

for bare dies

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New Structures – PCB Embedding [17, 18]

for bare dies

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New Structures – PCB Embedding [17, 18]

for bare dies

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New Structures – PCB Embedding [17, 18]

for bare dies

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New Structures – PCB Embedding [17, 18]

for bare dies

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New Structures – PCB Embedding [17, 18]

◮ _{PFC inductor (Thick)} ◮ _TIM

◮ _{Gate driver (thick)} ◮ _TIM

◮ _{Power devices PCB (thin)} ◮ _{Thermal Interface Material (TIM)} ◮ _Heatsink

◮ _{Board-to-board interconnects using wires soldered in through-holes} ◮ _{Final cell dimensions: 7 × 7×3.5 cm}3

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

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New Structures – PCB Embedding [17, 18]

◮ _{4 PFC cells for a full converter} ◮ _{DC capacitor bank for test only} ◮ _{4-stage EMC DM filter}

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New Structures – PCB Embedding [17, 18]

For SiC dies

◮ _{good quality of microvias}

◮ _{No damage to dies} ◮ _{Uniform thickness} ◮ _{Good alignment}

◮ _{Gate contact} 500×800 µm2

◮ _{Good electrical perf.}

◮ _{Consistent R}

DSon (80 mΩ)

◮ _{No change in V} th ◮ _{Low leakage current}

(max 1.6 nA @ 1200 V) ◮ _{Very good yield}

(97% on 44 dies)

SiC MOSFET

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New Structures – PCB Embedding [17, 18]

For SiC dies

◮ _{No damage to dies} ◮ _{Uniform thickness}

◮ _{Good alignment}

DSon (80 mΩ)

◮ _{No change in V} th ◮ _{Low leakage current}

(max 1.6 nA @ 1200 V) ◮ _{Very good yield}

(97% on 44 dies)

Drain

Source

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New Structures – PCB Embedding [17, 18]

For SiC dies

DSon (80 mΩ) ◮ _{No change in V}

th

◮ _{Low leakage current} (max 1.6 nA @ 1200 V) ◮ _{Very good yield}

(97% on 44 dies) 0 2 4 _V 6 8 10 d s (V) 0 5 10 15 20 Ids (A) V GS= 10 V V_GS= 17 V V_GS= 15 V V_GS= 5 V

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New Structures – PCB Embedding [17, 18]

For SiC dies

DSon (80 mΩ) ◮ _{No change in V}

th

◮ _{Low leakage current} (max 1.6 nA @ 1200 V) ◮ _{Very good yield}

(97% on 44 dies) Voltage (V) 0 0.2 0.4 0.6 0.8 1 1.2 Current (A ) 0 0.5 1 1.5 2 Diode 1 Diode 2 Diode 3 Diode 4 Voltage (V) -800 -700 -600 -500 -400 -300 -200 -100 0 Current (A ) x10-5 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 Diode 1 Diode 2 Diode 4

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Operation of the PFC converter

0 0.01 0.02 0.03 0.04 Time (s) -1.5 -1 -0.5 0 0.5 1 1.5 Current (A)

◮ _{4 interleaved PFC cells (target power 4×825 W=3.3 kW)} ◮ _{Operation at reduced power because of losses in inductors}

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Conclusions – Exploiting the PCB Embedding

◮ _{“All-embedded”, interleaved PFC designed}

◮ _{includes dies, driver, inductors} ◮ _{Very good production yield} ◮ _{Only issue: embedded inductors} ◮ _{Next step: better use of embedding}

◮ _{Keep some components on the surface} ◮ _{Improve design for manufacturing} ◮ _{Improve design tools}

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Conclusions – Exploiting the PCB Embedding

◮ _{“All-embedded”, interleaved PFC designed}

◮ _{includes dies, driver, inductors} ◮ _{Very good production yield} ◮ _{Only issue: embedded inductors}

◮ _{Next step: better use of embedding}

◮ _{Keep some components on the surface} ◮ _{Improve design for manufacturing} ◮ _{Improve design tools}

(106)

Outline

Fail-to-short Packaging for SiC High Voltage Substrates Conclusion

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Outline

Packaging for High Voltage Fail-to-short Packaging for SiC

High Voltage Substrates Conclusion

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Fail-to-Short Packaging for HVDC Applications

Source: I. Yaqcub PhD thesis, 2015 [19]

HVDC Converters ◮ _{Rated at 100s kV}

(ex 320 kV for France-Spain link) ◮ _{Series of 100s of transistors}

(800 for same converter) ◮ _{Transistors fail randomly}

◮ _{Should not stop converter} ◮ _{Failed device turned to short}

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Fail-to-Short Packaging for HVDC Applications

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Fail-to-Short Packaging for HVDC Applications

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Fail-to-Short Packaging for HVDC Applications

circuit

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Fail-to-Short Packaging

◮ _{Standard packaging: Fail-to-Open} ◮ _{Wirebonds act as fuses or blown away} ➜ Need for massive contacts

◮ _{“Press pack”-type packages introduced} ◮ _{Initially for single die, now for multichip} ◮ _{When failure occurs:}

◮ _{Temperature rises}

◮ _{Die and surrounding metal melt} ◮ _{They form a conductive area} ◮ _{Strong package contains explosion}

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Fail-to-Short Packaging

source: Gunturi, S. et al. Innovative Metal System for IGBT Press Pack Modules (ISPSD 2003) [20]

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Fail-to-Short Packaging

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Fail-to-Short Packaging

◮ _{Die and surrounding metal melt} ◮ _{They form a conductive area} ◮ _{Strong package contains explosion} Is a FTS package Possible for SiC?

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Fail-to-Short Packaging – test on SiC dies [21]

◮ _{Dies fracture because of} failure

◮ _{SiC and metal remain} separate

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Fail-to-Short Packaging – test on SiC dies [21]

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Fail-to-Short Packaging – test on SiC dies [21]

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Fail-to-Short Packaging – test on SiC dies [21]

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Fail-to-Short Packaging – test on SiC dies [21]

◮ _{Tiny metal filaments form}

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Fail-to-Short Packaging – Design of a module [22]

◮ _{“Micro-Posts”: massive interconnects} ◮ _{Silver sintering: high temperature bonding} ◮ _{Salient features: for topside contact}

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Fail-to-Short Packaging – Test samples [22]

Sample Encapsulant Clamp Switch

Module A None Yes MOS 1

MOS 2

Module B Silicone Yes MOS 1

MOS 2

Module C Epoxy No MOS 1

MOS 2

Module D Silicone Yes MOS 1

–

◮ _{Dies tested individually}

◮ _{“Clamp” used for modules A, B and D} ◮ _{MOS 2 of module D not connected}

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Fail-to-Short Packaging – Results [22]

E Rinit Rfinal Failure

Encapsulant Clamp Switch [J] [mΩ] [mΩ] mode

A None Yes MOS 1 – 186 77 SC

MOS 2 8.8 201 128 SC

B Silicone Yes MOS 1 20 165 120 SC

MOS 2 1 188 167 SC

C Epoxy No MOS 1 9.7 – – OC

MOS 2 – – – –

D Silicone Yes MOS 1 2.24 180 158 SC

– – – – –

◮ _{Module C separated during first test, causing open circuit} ◮ _{All other modules exhibited stable short circuit}

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Fail-To-Short Packaging – Conclusions

◮ _{Fail-to-Short behaviour with SiC dies requires:}

◮ _{to prevent the Ceramic tiles from separating} ➜ a strong mechanical clamp/frame

➜ soft encapsulant probably better for gases to escape ◮ _{To provide massive interconnects:}

◮ _{wirebonds would act as fuses}

◮ _{to supply metal to fill the cracks in the dies}

(125)

Fail-To-Short Packaging – Conclusions

◮ _{Fail-to-Short behaviour with SiC dies requires:}

◮ _{to prevent the Ceramic tiles from separating} ➜ a strong mechanical clamp/frame

➜ soft encapsulant probably better for gases to escape

◮ _{To provide massive interconnects:}

◮ _{wirebonds would act as fuses}

◮ _{to supply metal to fill the cracks in the dies}

(126)

Outline

Fail-to-short Packaging for SiC

High Voltage Substrates

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HV Substrates – Thermal stability of SiC MOSFETs

◮ _{Considering only conduction losses}

◮ _P_{= R}

DSonI

2

D

◮ _{Considering only mobility reduction}

◮ _R DSon(TJ) = RDSon,273× _T J 273 2.4 [23]

➜ Strong increase of losses with TJ

0 50 100 150 200 0 1 2 3 4 Junction Temperature (oC) R on (normalized) 3.3 kV MOSFET (polyfit) 10 kV MOSFET (polyfit) Rdson(Tj/273)2.4

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HV Substrates – Thermal stability of SiC MOSFETs

◮ _{Considering only conduction losses}

◮ _P_{= R}

DSonI

2

D

◮ _{Considering only mobility reduction}

◮ _R DSon(TJ) = RDSon,273× _T J 273 2.4 [23]

➜ Strong increase of losses with TJ

0 50 100 150 200 0 1 2 3 4 Junction Temperature (oC) R on (normalized) 3.3 kV MOSFET (polyfit) 10 kV MOSFET (polyfit) Rdson(Tj/273)2.4

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HV Substrates – Thermal/Electrical trade-off

Packaging of SiC dies ◮ _{Backside cooling} ◮ _{Electrical insulation of}

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HV Substrates – Thermal/Electrical trade-off

Packaging of SiC dies ◮ _{Backside cooling} ◮ _{Electrical insulation of}

baseplate

Ceramic substrate Ensures ◮ _{Electrical insulation} ◮ _{Heat conduction}

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HV Substrates – Materials and Geometric Issues [24]

Source: Dielectric properties of ceramic substrates and current developments for medium voltage applications, L. Laudebat et al., MVDC Workshop 2017

Ceramic materials ◮ _{BeO discarded (toxic)} ◮ _{AlN next best thermal}

conductivity

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HV Substrates – Materials and Geometric Issues [24]

Source: Dielectric properties of ceramic substrates and current developments for medium voltage applications, L. Laudebat et al., MVDC Workshop 2017

Copper Resin

Ceramic materials ◮ _{BeO discarded (toxic)} ◮ _{AlN next best thermal}

conductivity

◮ _{AlN best electrical strength} Substrate structure

◮ _{“Triple point”}

◮ _{Sharp edge of metallization} ➜ Electric field reinforcement

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HV Substrates – New Geometry [24]

“Protruding” structure ◮ _{Shielding of triple point} ◮ _{Rounded electrodes} ◮ _{Ideally, encapsulant and}

ceramic with matchedǫR

l h t R_C εr Aluminium Nitride Copper Encapsulant Triple point ǫ encapsulant=1 ǫ encapsulant=9

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HV Substrate – Manufacturing [24]

Copper Aluminium nitride Excess solder Triple point 40 mm

40 mm

◮ _{Active Metal Brazing between ceramic and copper (no} voiding observed)

◮ _{Excess solder flowed along copper, not ceramic}

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HV Substrate – Results and conclusion [24]

◮ _{Clear improvement of protruding over “standard” substrate}

◮ _{Same total ceramic thickness (1 mm), same ceramic provider}

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Outline

Packaging for High Voltage Fail-to-short Packaging for SiC High Voltage Substrates

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Summary

◮ _{Packaging for high temperature, high voltage or high density}

◮ _{Ceramic and silver sintering technologies for HT/HV}

◮ _{Currently: development of a HVDC “MMC submodule” (A. Boutry)} ◮ _{Converter-level rather than pure packaging}

◮ _{Printed Circuit board for integration}

◮ _{Fully custom designs (no more modules)}

◮ _{Embedding to overcome thermal/electrical limitations}

◮ _{Any of these topics is open for discussion/collaboration}

◮ _{Please see me for more information on any of them} ◮ _{References at the end of the presentation}

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Summary

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Summary

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Summary

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Summary

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Summary

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Summary

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Acknowledgements

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