ARM ARM710

Advanced RISC Machines

ARM

Document Number: ARM DDI 0024E Issued: Dec 1994 Copyright Advanced RISC Machines Ltd (ARM) 1994 All rights reserved

ARM710

Data Sheet

Proprietary Notice

ARM, the ARM Powered logo, BlackICE, and ICEbreaker are trademarks of Advanced RISC Machines Ltd.

Neither the whole nor any part of the information contained in, or the product described in, this datasheet may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this datasheet is subject to continuous developments and

improvements. All particulars of the product and its use contained in this datasheet are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded.

This datasheet is intended only to assist the reader in the use of the product. ARM Ltd shall not be liable for any loss or damage arising from the use of any information in this datasheet, or any error or omission in such information, or any incorrect use of the product.

Change Log

Issue Date By Change

A July 1993 TP Unified FrameMaker version created.

B Sept 1993 PM Corrected TOC.

C July 1994 EH General corrections.

D Aug 94 BJH Updated linefetch diagram.

E Dec 94 PB Edited.

Preface

ii ARM710 Data Sheet

The ARM710 is a general purpose 32-bit microprocessor with 8kByte cache, write buffer and Memory Management Unit (MMU) combined in a single chip. The ARM710 offers high-level RISC performance yet its fully static design ensures minimal power consumption, making it ideal for portable, low-cost systems.

The innovative MMU supports a conventional two-level page-table structure and a number of extensions which make it ideal for embedded control, UNIX and Object Oriented systems. This results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip.

Applications

■ Personal computer devices e.g.PDAs

■ High-performance, real-time control systems

■ Portable telecommunications

■ Data communications equipment

■ Consumer products

■ Automotive

Feature Summary

■ High performance RISC

25 MIPS sustained @ 33 MHz (33 MIPS peak)

■ Fast sub-microsecond interrupt response for real-time applications

■ Memory Management Unit (MMU) support for virtual memory systems

■ Excellent high-level language support

■ 8kByte of instruction & data cache

■ Big and Little Endian operating modes

■ Write Buffer

enhancing performance

■ IEE 1149.1 Boundary scan

■ Fully static operation, low power consumption ideal for power sensitive applications

■ 144 Thin Quad Flat Pack (TQFP) package

■ Low-power CMOS process 1.5mA/MHz@3.3V

■ 3V and 5V operation

Address Bus

ARM7

Write MMU

8Kbyte

Control CPU

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Higher Address 31 24 23 16 15 8 7 0 Word Address

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7 6 5 4 4

3 2 1 0 0

Lower Address

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General Registers and Program Counter Modes

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC)

User32 FIQ32 Supervisor32 Abort32 IRQ32 Undefined32

CPSR CPSR

SPSR_fiq

CPSR SPSR_svc

CPSR SPSR_abt

CPSR SPSR_irq

CPSR SPSR_und

Program Status Registers

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0 1 2 3 4 5 6 7 8 27

28 29 30 31

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C Z N

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Carry / Borrow / Extend Zero

Negative / Less Than

Mode bits FIQ disable IRQ disable

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flags control

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c&e<c&c&c&c&c&c&&V ,(lYX ,(lYX

Table 3: Vector Summary

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31 28 27 24 23 20 19 16 15 12 11 8 7 5 4 3 0

Cond 0 0 Opcode

21

S Rn Rd Operand 2 Data Processing

PSR Transfer Multiply Single Data Swap Single Data Transfer Undefined

Block Data Transfer

Coproc Data Transfer Branch

Coproc Data Operation Coproc Register Transfer Software Interrupt

26 25 22

I Cond

Cond Cond Cond Cond Cond Cond Cond Cond Cond

0 0 0 0 0 0 A S Rd Rn Rs 1 0 0 1 Rm

1 0 0 1 Rm 0 0 0 0

Rd Rn

0 0 0 1 0 B 0 0

offset Rd

Rn B W L I P U 0 1

0 1 1 XXXXXXXXXXXXXXXXXXXX 1 XXXX

1 0 0 P U S W L Rn Register List

1 0 1 L 1 1 0

offset

1 1 1 0 0 CRm

1 1 1 0 CP Opc L N W L

P U Rn CRd CP# offset

1 1 1 1

CP Opc CRn CRd

CRn Rd

CP#

CP#

CP

CP 1 CRm

ignored by processor

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Cond

31 28 27 0

Condition field

0000 = EQ - Z set (equal) 0001 = NE - Z clear (not equal)

0010 = CS - C set (unsigned higher or same) 0011 = CC - C clear (unsigned lower) 0100 = MI - N set (negative) 0101 = PL - N clear (positive or zero) 0110 = VS - V set (overflow) 0111 = VC - V clear (no overflow)

1000 = HI - C set and Z clear (unsigned higher) 1001 = LS - C clear or Z set (unsigned lower or same)

1010 = GE - N set and V set, or N clear and V clear (greater or equal) 1011 = LT - N set and V clear, or N clear and V set (less than)

1100 = GT - Z clear, and either N set and V set, or N clear and V clear (greater than) 1101 = LE - Z set, or N set and V clear, or N clear and V set (less than or equal) 1110 = AL - always

1111 = NV - never

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}~ ¢¡ £¢ ¢HI å Z £2¤ ?¥¦ =G? EfE :I å §

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¯ ë ô¯&ë4¥¼š¬i¨ õ ¥¼ ››[½i¤9ž¨©¤y¹dÀ

Cond 101 L offset

31 28 27 25 24 23 0

Link bit

0 = Branch 1 = Branch with Link

Condition field

¨ ü

ïYŸ/¤y¶·¨6 ¡ª‘š§¤9¦[«Ÿ/ ¦i¡š›À<ïYŸ®¤y¶·¨} ¡

¨

©u¶ž¨<Ÿ½i¤9«§¤y¨<¤y¡ŸBÀ

‰}ˆ‡}ˆ‰¬«ŽŸ}”˜ ’­…y˜

here BAL here ; assembles to 0xEAFFFFFE (note effect of PC offset) B there ; ALways condition used as default

CMP R1,#0 ; compare R1 with zero and branch to fred if R1 BEQ fred ; was zero otherwise continue to next instruction BL sub+ROM ; call subroutine at computed address

ADDS R1,#1 ; add 1 to register 1, setting CPSR flags on the BLCC sub ; result then call subroutine if the C flag is clear,

; which will be the case unless R1 held 0xFFFFFFFF