I=AIRCHIL.D A Schlumberger Company

© 1983 Fairchild Camera and Instrument Corp.

Microprocessor Division 3420 Central Expressway Santa Clara, CA 95051

January 1983

I=AIRCHIL.D

A Schlumberger Company

The Advance Product Information designation on a Fairchild publication indicates that the product described is not characterized. The specifications presented are based on design goals or preliminary part evaluation and, as they are subject to change, are not guaranteed. Fairchild

Microprocessor Division should be contacted for current information on these products.

The information furnished in this publication is believed to be accurate and reliable. However, Fairchild cannot assume responsibility for its use, or for use of any circuitry described, other than circuitry entirely embodied in a Fairchild product.

No license is granted or implied under any Fairchild patents or trademarks.

Fairchild reserves the right to make changes in the circuitry or specifications presented in this publication at any time and without notice.

iii

Table of Contents

Section 1 Introduction

General. . . ... 1·3 Product Line ... 1·3 Data Book... ... 1·3

Section 2 Ordering and Package Information

General. . . ... 2·3 Temperature Range ... 2·3 Package Types and Outlines ... 2·3

Section 3 F8 Microcomputer Family

General. . . ... . . ... 3·3 Memory Interface Devices ... 3·3 Input/Output Devices ... 3-3 Bus Structure ... 3-3 Instruction Set. ... 3·3 F3850 Central Processing Unit. ... 3·7 F3851 Program Storage Unit. ... 3·31 F3861 Peripheral Input/Output. ... 3·55 F3871 Peripheral Input/Output. ... 3-67

Section 4 Controller Family

F387X Family ... 4·3 Part Numbers ... , ... 4·3 Descriptions ...•... 4·3 F3870 Single·Chip Microcomputer ... 4·5 F3870AlF3870B High·SpeedSingle·Chip Microcomputer ... 4·27 F38C70 Single-Chip Microcomputer ... 4·29 F38E70 Single·Chip Microcomputer ...•. 4·47 F38E70·21 Single·Chip Microcomputer ... 4-67 F38721F38L72 Single·Chip Microcomputer ... 4·71

v

Section 5 F6800 Microprocessor Family

General ... 5-3 Instruction Set. ... 5-5 F6800/F68AOO/F68BOO 8-Bit Microprocessing Unit. ... 5-11 F6801/F6803 Single-Chip Microcomputer ... 5-51 F6802/F6808/F6882 Microprocessor With Clock and RAM ... 5-57 F6809/F68A09/F68B09 Central Processing Unit. ... 5-81 F6809E/F68A09E/F68B09E Central Processing Unit. ... 5-83 F6810/F68A10/F68B10 128 x 8-Bit Static RAM ... 5-87 F6820 Peripheral Interface Adapter ... 5-93 F6821/F68A21/F68B21 Peripheral Interface Adapter ... 5-107 F6840/F68A40/F68B40 Programmable Timer ... 5-119 F6844 Direct Memory Access Controller ... 5-135 F6845/F6845A CRT Controller ... 5-155 F6846 ROM-I/O-Timer ... 5-179 F6847 Video Display Generator ... 5-199 F6850/F68A50/F68B50 Asynchronous Communications Interface Adapter ... 5-211 F6852/F68A52/F68B52 Synchronous Serial Data Adapter ... 5-223 F6854/F68A54/F68B54 Advanced Data Link Controller ... 5-243 F6856 Synchronous Protocol Communications Controller ... 5-267 F38456/F68456 Multiple Protocol Communications Controller ... 5-297 F68488 General Purpose Interface Adapter ... 5-301

Section 6 16-Bit

1

³

l

Bipolar Microprocessor Family

GeneraL ... 6-3 Instruction Set. ... 6-3 F9414 4-Chip Data Encryption Set. ... 6-13 F9423 FIFO Buffer Memory ... 6-27 F9443 Floating Point Processor ... 6-47 F9444 Memory Management and Protection Unit. ... 6-49 F9445 16-Bit Bipolar Microprocessor ...•... 6-51 F9446 Dynamic Memory Controller ... 6-79 F9447 1/0 Bus Controller ... 6-81 F9448 Programmable Multiport Interface ... 6-89 F9449 Multiple Data Channel Controller ... 6-95 F9450 Single-Chip Microprocessor ... 6-109 F9451 Memory Management Unit. ... 6-111 F9452 Block Protect RAM ... 6-113 F9470 Console Controller ... 6-115

vi

Table of Contents

Section 7 F16000 Microprocessor Family

General. ... 7-3 Addressing ... 7-3 Virtual Memory ... 7-3 Symmetry ... 7-3 High-Level Language Support ... 7-4 Modularity ... 7-4 Slave Processors ... 7-4 System Protection ... 7-4 Future Expansion ... 7-4 F16032 High Performance Central Processing Unit. ... 7-7 F16081 Floating Point Unit. ... 7-13 F16082 Memory Management Unit. ... 7-15 F16105 Very Intelligent Peripheral Controller. ... 7-17 F16201 Timing Control Unit. ... " ... 7-19 F16202 Interrupt Control Unit. ... 7-21 F16203 Channel Controller ... 7-23 F16204 Bus Arbiter ... 7-25 F16413 CRT Controller ... 7-27 F16425 Packet Switching Frame Level Controller ... 7·31 F16456 Multiple Protocol Communications Controller ... 7-35 F16488 GPIB Controller ... 7·39 F16802 Local Area Network Controller ... 7-41 Section 8 ROM Products

F3532/F68332/F3533 32K ROM ... 8-5 F3564 64K ROM ... 8-11 F3565 64K ROM ... 8-13 F3566 64K ROM ... 8-15 F3568 64K ROM ... 8-17 F3569 64K ROM ... 8-19 F3570 64K ROM ... 8·21 F35316/F68316 16K ROM ... 8-23 Section 9 Development Systems and Software

EMUTRAC ... 9-5 F38E70 Programming Board ... 9-9 Formulator ... 9·11 FS·I. . . .. . ... 9-13 PEp·38 ... , ... 9·19 PEP-45 ... 9-21 PEP-68 ... 9-23 Software ... 9-31

vii

Section 10 Applications

Matrix Printer ...•... 10-5 PLL System ... '.' ... 10-19 Solar Controller ... 10-31 F9414 Data Encryption ... , ... 10·33 CCO 3000 Camera ...•... 10-45 Section 11 'Resource and Training Centers

Section 12 Sales Offices

vIIi

INTRODUCTION

r-;;-\2

IORDERING AND PACKAGE

~ INFORMATION

IrulF8

MICROCOMPUTER FAMILY

101

CONTROLLER FAMILY

1~IF6800

MICROPROCESSOR FAMILY

101F16000

MICROPROCESSOR FAMILY 1

[!] I

ROM PRODUCTS

I [!QJ

¹ APPLICA nONS

I [I!] I

RESOURCE AND TRAINING CENTERSI 1

[!!J I

SALES OFFICES

FAIRCHILD

A Schlumberger Company

General

A microprocessor is essentially an integrated circuit logic replacement device that performs the functions of the cen- tral processing unit (CPU) of a computer system. The overall task of the microprocessor is to receive digital data and store it for later processing, to perform arithmetic and logic operations on the data in accordance with instruc- tions contained in a stored program, and to present the results of these operations to the user through some form of output mechanism.

The program is a definable and non-varying specification for any given application. It normally resides in a read only memory (ROM) or program storage unit (PSU). Variable data that is to be operated upon by the microprocessor is nor- mally stored in a random access memory (RAM) or other transient data storage element.

Although architectural details vary depending upon manufacturer and technology, a typical microprocessor comprises the following functional areas:

1. Instruction decoding to interpret program instructions.

2. An arithmetic and logic unit (ALU) to perform binary addition, subtraction, etc., and Boolean logic operations.

3. Registers to temporarily store frequently manipulated data.

4. Address buffers to provide the next program instruction address.

5. InpuUoutput (I/O) buffers to read information into or write information out of the microprocessor.

Microprocessors are generally used in conjunction with support devices that perform timing, program and transient data memory, I/O signal interface, and other functions. A wide range of configurations is possible with a

microprocessor and its related devices; each configuration represents a full microcomputer system.

A single-chip microcomputer incorporates CPU, memory, I/O, control, and other functions into one integrated circuit.

Typically, such devices have facilities for enhancement of

1-3

Section 1 Introduction

capabilities by interconnection with external devices.

The Fairchild Microprocessor Division product line encom- passes microprocessors and their support devices, single- and multi-chip microcomputers, and systems to emulate and develop hardware and software.

Product Line

The Microprocessor Division product line includes a wide range of devices to meet the specific needs of four broad application areas:

1. 8-bit microprocessors

2. 8-bit single-chip microcomputers 3. 16-bit microprocessors

4. Development aids

Within these areas, the Division offers a blend of in- novative, state-of-the-art devices and proven, well- established devices. For example, the members of the F6800 family, and of the F8 family, can be configured to create a variety of 8-bit computer systems that have a wide range of capabilities. Similarly, the F9445 family com- ponents can create extremely fast 16-bit computer systems that are exceptionally resistant to harsh environments, and the F16000 family members can be used in configurations that are ideally suited to communications applications. (The F16000 has a 16-bit I/O structure and a 32-bit

internal architecture.)

To the user, the Microprocessor Division line represents a single source of cost-effective solutions to the full spectrum of application problems.

Data Book

This data book presents a complete technical description of the Fairchild Microprocessor Division product line.

Where devices have been characterized, specific informa- tion is presented in the form of data sheets. Information on partially characterized devices, and on devices currently under development, is in the form of advance product infor- mation sheets. More complete data can be obtained from the Product Marketing Department.

II

1-4

1

[!J

1 INTRODUCTION

101F8 MICROCOMPUTER FAMILY

ICTIICONTROLLER FAMILY

1 0 1 F6800 MICROPROCESSOR FAMILY

J

101F16000 MICROPROCESSOR FAMILY

1

~ I

ROM PRODUCTS

InIg

I DEVELOPMENT SYSTEMS AND

L!J

^SOFTWARE

I [!QJ

I APPLICA nONS

I[!TIIRESOURCE AND TRAINING CENTERSI

I @ ] I SALES OFFICES

F=AIRCHIL.D r..

Schlumberger Company

General

Section 2

Ordering and Packaging Information

Package Types and Outlines Specific ordering codes, as well as the temperature ranges

and package types available, are included in each data sheet of sections 3 through 8.

The basic package type of a device, such as dual-in-line • plastic or dual-in-line ceramic, is indicated by the ordering code for that device. To accommodate various die sizes and pin numbers, different package forms exist within each

Temperature Range package type.

The basic temperature ranges typically available are: The package forms indicated by device ordering codes are illustrated in the following detailed outline drawings.

C L M

Commercial (O°C to 7S0C) Automotive (- 40°C to 8S°C)

Military (- SsoC to 12S0C)

Selected products are optionally available in 44- and 68·pin lead less chip carriers. Contact your local sales office for more information.

24-Pin Ceramic Dual·ln-Line

r---

1.290132.7661----1 11\1\1\/1.235131.3691 \1\1\1\ 1

112

.570 (14.478)

.515IL4"~~~~~~~.,g..J

---1

L

.100 12.5401 .040 (1.016) .190 14.8261

.lt6~1;:;;;;;:;;::;:;;;;:;;;;;:;:;::;:;J

NOTES:

.03710.9401

II

.02010.5081 .027 10.686dl--.016 10.4061 STANDOFF

WIDTH

All dimensions are in inches bold and millimeters (parentheses).

Pin material is nickel gold·plated kovar.

Cap is kovar.

Base is ceramic.

Package weight is 6.5 grams.

2·3

24-Pin Plastic DIP

28·Pin Ceramic Dual·ln·Line

r---

1.260 (32.004)

----1

I

1\1\1\1,

.240 (31.496) ,1\1\1\

I

.560 (14.224)

1'2

.540 (13.716)

.055 R (1.40) .050 (1.27)

Ll¥ii=ii~=rr=n=;;=ir'ii=i~

L

.085 (2.16) .070 (1.78) .165(4.19) .050 _(1.27) NOM _-

II

_-

.150 (3.81

+

_r) ¹⁼ ;;:;:;;:;:;;;:;:;;:~g.020 ^{MIN (.508)}

NOTES:

- - L SEATING

~

----'--PLANE

.037(.940)

II

.020 (.508) .027 (.686)

-II-

.016(.406) STANDOFF

WIDTH

All dimensions are in inches bold and millimeters (parentheses).

Pins are tin·plated kovar.

Package material is plastic.

NOTES:

1 __ .110 (2.79)

.090 (2.271 __ .037(0.94)

_II __ ~

.027 (0.68> .016 !O.41) STANDOFF

WIDTH

All dimensions are in inches bold and millimeters (parentheses).

Pin material is nickel gold·plated kovar.

Cap is kovar.

Base is ceramic.

Package weight is 6.5 grams.

2·4

28·Pln Plastic Dual·ln·Llne

Ordering and Packaging Information

~----.'4.5137.2'1 MAX-~

=E[::::::::::r-"""=-"~

y 1 I w .050TVP ---1

I

40·Pin Ceramic Dual·ln·Line

~ 1---

^11.271 -, !--.07511.91ITVP

r ..

0011 •. 2 4 I j

066 !1 40) NOM

E

'60(~'06)MAX :045 (1:141-'1

r.

-~::,~'" _~-SEATING

-PLANe

.011 (0.28) ...- .009 (O.23) .100 12.541.--' TVP -I 1'_

III h

^---"i

Ih

^+,30 .115(2.92)

3.3011---;~82",1

NOM ---1 ^I

:g~~

:g:::l

.018 (0.46) NOM NOTES:

All dimensions are In inches bold and millimeters (parentheses).

Pins are tin.plated kovar.

Package material Is plastic.

.02' R .580 MAX 1.6354' (14.73)

I

.060 ~ 1.524) .025 10.635)

~H=H=~~~~~~~~~~~~~~~~~=d~SEATING

.200 (5.080) .125 (2.540)

iPLANE

NOTES:

I

.750 (19.0501 I

~ MAX -j

All dimensions are in inches bold and millimeters (parentheses).

Pin material is nickel gold'plated kovar.

Cap is kovar.

Base is ceramic.

Package weight is 6.5 grams.

2·5

•

4O-Pin Plastic Dual-In-Line

1 2.0SO

• . (52.070) ~

'I

"f]:::::::::::::::::::r _{J 1-}

.060 (1.524)

~:

.155

I--

.040 (1.016) .070 1.590 (14.99lj

(3.94) (1.778)

I

r·610 (15.49)

iWNUWllWUWUWHM

^:::1.lln9

1

^°.010

4-

.140(3.56) " I~

.,

^{(0.S08) Plane} ~ (0.254~)

.125(3.18)

J

L·ll0(2.794)TYP .018 _

j

M.~~5 ^{.680 MAX}

, .090 (2.286) . (0.457) (1.905) (17.27)

TYP. REF.

NOTES:

All dimensions are In inches bold and millimeters (parentheses).

Pins are tin·plated kovar.

Package material Is plastic.

4O-Pin Ceramic Dual-In-Line (EPROM)

.110 (14 9861 ."'.(143511

025(06351 R

410 (127001

021921 1'0(4064) .. 80 -

I -

:~::::::~'

1152~} ^.. ge~:: ~~::-l

r- r'"

.010(15241 ,,0127941 (121921

.04011 0161 __ _ _ .----:::::!-L

::.!4~. 0",0""

.'7Si-4·"~ J ~

^110c27941 .J' 041(1 1431

I~ ::0:::1 ::(~:2,9~51

^I

,1"(3,751 ! 1.010122861 --04r:~'016J 02010508,1- MAX -I

- 011104(6) TVP

NOTES:

All dimensions are In inches bold and millimeters (parentheses).

Pin material Is nickel gold-plated kovar.

Cap Is kovar.

Base is ceramic.

Package weight Is 6.5 grams.

2:6

48 Lead Sidebrazed Package

Ordering and Packaging Information

.030(0.76)R TYP .610 ± .010

(15.49 ± 0.25)

NOTES:

0.50R (1.27) MAX.

NOTCH

.165(4.19)MAX .125(3.12)MIN

I

I

I

.550 ± .003 sa

(13.97 ±l

008:;~90~ ~~~05)

24 j

25

1+·---(~04~~~~~~)---1

_.040(1.02)TYP

3. Base Is Ceramic 1. Lead Material Is Nickel Gold Plated Kovar or Alloy 42 4. Cavity Size Is .400 x 0400 2. Cap Is Kovar or Alloy 42 5. Package Weight Is 7.7 Grams

54· Pin Ceramic Dual·ln·Line

1---.510(12.954)~

1---1.63~R~~402)---~-I1

I---~:::~::~~:~:---I

11_.

018 (.457)

-'1

^TYP

NOTES:

CAP (REF)

__ .050 (1.270) TYP

AI,O, WINDOW FRAME A1203BASE

All dimensions are in inches bold and millimeters (parentheses).

Pin material is nickel gold-plated kovar.

Cap is kovar.

Base is ceramic.

Package weight is 6.5 grams.

2-7

1

.588 (14.935)

1

.582 (14.783)

I

.025 (.635) R (REF)

.600 (15.240) -BENDLlNE-

.011 (.279) .009(.229)

~.655 (16.637)----1 I~--.615(15.621) -I

•

68 Lead Ceramic Leaded Chip Carrier

1 - - - -^2.000 REf'---~

1 - - - . 9 8 R E F · - - - J

LEAD NO.1

.148 .145

.098

TYP

L

^LID(REF)

, c

r ---; --,-'

^!

i i

.120 .050 .100 REF

NOTES:

1. Lead Material Is Alloy 42 or Kovar Solder Coated 2. Lid Is Kovar or Alloy 42

3. Base & Top Are Ceramic 4. Cavity Size Is .400" x .400"

5. Package Weight Is 7.5 Grams 6. Lead Forming Is Optional

2-8

1

[!]

I INTRODUCTION

r;;l2

IORDERING AND PACKAGE

~ INFORMATION

F8 MICROCOMPUTER FAMILY

1

CTI

I CONTROLLER FAMILY

1~IF6800

MICROPROCESSOR FAMILY

101

F16000 MICROPROCESSOR FAMILY

1

~I

ROM PRODUCTS

~9

I DEVELOPMENT SYSTEMS AND

L!.J

SOFTWARE

1

[!QJ

¹ APPLICATIONS

I [!IJ

I RESOURCE AND TRAINING CENTERS I 1

~

I SALES OFFICES

FAIRCHILD

A Schlumberger Company

General

The distribution of logic among the various elements of a microcomputer system is one of the most variable features of such systems. The traditional division of logic cor- responds to the requirements of a computer; e.g., one device serving as CPU, one as memory, and one as I/O. In the F8 microcomputer family, logic is implemented in devices in terms of application complexity rather than in terms of computer function. Thus, for example, two F8 devices implement all of the basic functions of a small microcomputer.

To accomplish this, the deSign of the F8 family includes a number of non-traditional function assignment features:

1. A small amount of RAM is implemented within the CPU as a scratchpad memory.

2. Memory addressing logic is implemented in the memory devices rather than in the CPU.

3. The I/O ports are implemented in the CPU and memory devices rather than in discrete I/O devices.

Every F8 configuration must contain an F3850 CPU, at least one F3851 Program Storage Unit (PSU) or memory interface device, and standard ROM or PROM (see figure 3-1). The memory-oriented devices may be used Singly or together in the same system; when necessary, multiple units of the same type may be used. For example, an F3850 and two F3851s may comprise a system requiring 2K words of ROM, 64 bytes of RAM, and six I/O ports.

Memory Interface Devices

When required by the application, the F3851 PSU may be replaced by an F3853 Static Memory Interface (SMI). Both of these devices interpret control signals output by the F3850 and generate the standard address and control signals re- quired by off-the-shelf dynamic and static memory devices.

3-3

Section 3

Fa Microcomputer Family

Input/Output Devices

Applications that require additional I/O and interrupt capabilities but do not require the PSU storage capacity can make use of the F3861 Peripheral Input/Output (PIO) device. The PIO, which also contains interrupt logic and a programmable timer, interprets CPU control signals to drive • two 8-bit I/O ports.

Bus Structure

The F8 microcomputer components are interconnected by means of a system bus structure that is composed of the following elements:

1. Eight data bus lines (DBo - DB7)

2. Five control lines (ROMCo - ROMC4) 3. Two clock lines (<I>, WRITE)

4. Three interrupt lines (PRI IN, PRI OUT, INT REO) Instruction Set

The instruction set of a microprocessor or microcomputer is the software tool used to shape the device or system for a particular application. The F8 instruction set is divided into four functional groups.

1. Input/Output 2. Arithmetic/Logical 3. Address Register Control

4. Indirect Scratchpad Address Register (ISAR) and Status Control

The F8 instruction set is presented in table 3-1.

Table 3-1 Fa Instruction Set Instruction Description

ADC Add Accumulator to Data Counter AI Add Immediate to Accumulator AM Add (Binary) Memory to Accumulator AMD Add (Decimal) Memory to Accumulator AS Add (Binary) Scratchpad Memory

to Accumulator

ASD Add (Decimal) Scratchpad Memory to Accumulator

BC Branch on Carry BF Branch on false BM Branch on Negative BNC Branch if No Carry BNO Branch if No Overflow BNZ Branch if Not Zero BP Branch if Positive BR Unconditional Branch BR7 Branch on ISAR BT Branch on True BZ Branch on Zero CI Compare Immediate CLR Clear Accumulator

COM Complement

DCI Load Data Counter Immediate DI Disable Interrupt

DS Dessement Scratch pad Memory Content EI Enable Interrupt

IN Input Long Address INC Increment Accumulator INS Input Short Address

3-4

Instruction Description JMP Branch Immediate LI Load Immediate LIS Load Immediate Short LlSL Load Lower Octal Digit oflSAR LlSU Load Upper Octal Digit of ISAR LM Load Accumulator from Memory LNK Link Carry to Accumulator LR Load Register

NI AND Immediate

NM Logical AND from Memory NOP No Operation

NS Logical AND from Scratchpad Memory 01 OR Immediate

OM Logical OR from Memory OUT Output Long Address OUTS Output Short Address PI Call to Subroutine Immediate

PK Call to Subroutine Direct and Return from Subroutine Direct

POP Return from Subroutine SL Shift Left

SR Shift Right ST Store to Memory XDC Exchange Data Counters XI Ekxclusive-OR Immediate XM Exclusive-OR from Memory

XS Exclusive-OR from Scratch pad Memory

Descriptions

F8 Microcomputer Family

Following is data that describes the members of the FB microcomputer system family.

F3851 PROGRAM STORAGE UNIT

F3853 STATIC MEMORY INTERFACE

F3856 PROGRAM STORAGE UNIT

F3861 PERIPHERAL INPUT/OUTPUT

F8 FAMILY ORGANIZATION

F3850

CENTRAL PROCESSING UNIT

3·5

F3871 PERIPHERAL INPUT/OUTPUT

II

3·6

I=AIRCHILO

A Schlumberger Company

Description

The Fairchild F3850 is the Central Processing Unit (CPU) for the F8 8-Bit Microprocessor family. The F3850 contains more than 70 instructions in its instruction set and operates on 8-bit units of information.

• N-channellsoplanar MOS Technology

• 2 IJ.s Cycle Time

• 64-Byte Scratchpad on the CPU Chip

• "TINo Bidirectional, 8-Bit 1/0 Ports, with Output Latches

Signal Functions

-

^{¢ INTREQ} - - - } INTERRUPT

-

^{WRITE ICB --+-- LINES}

CLOCK ^LINES

-

^{XTLX ROMCo}

=)-~

XTLY ROMe,

XTLZ ROMe2 --+- LINES

ROMe3

-

--

^1/000

--

^{1/001 EXTREs}

---

^RESET

--

^{1/002 1/003} DBo

--

--

^{1/004 DB,}

_--

--

^{liDos DB,}

--

1/0

--

^{1/006 DB,}

--

^DATA

PORT

1/007 BUS

LINES

-- _--

^{1/010 DB, DBs}

_-- --

^LINES

1/011 DB,

--

-

^{1/012 DB,}

--

- -- -- -- --

^{1/0 14 1/017 1/0 13 1/°15 1/°16 VGG Vss Voo}

^...- -- _)~'"

F3850

Central Processing Unit (CPU)

Microprocessor Product

• 8-Blt Arithmetic and Logic Unit, Supporting Both Binary and Decimal Arithmetic

• Interrupt Control Logic

• Power-on Reset Logic

• Clock Generation Logic Within the CPU Chip. With Crystal and External Clock Generation

• More Than 70 Instructions

• +5 V and +12 V Power Supplies

•

• Low Power Dissipation (l\'pically Less Than 330 mW)

Connection Diagram

¢ XTLZ

WRITE 39 XTLZ

Voo 38 XTLY

VGG 37 EXTREs

1/003 36 1/004

DB, 3S DB,

1/0 13 34 1/014

1/012 1/0 15

DB, 32 DB,

1/002 1. 31 1/0 ..

1/001 11 liD"

DB, 12 DB,

1/011 13 28 1/016

1/010 l' ⁱ⁷⁰¹⁷

DBo 15 26 DB,

1/000 16 25 11007

ROMeo 17 2' ^Vss

ROMe, 18 INTREQ

ROMe2 19 ICB

ROMe3 2. ROMC 4

(Top View)

3-7

Device Organization

The logical organization and pins for the F3850 CPU are illustrated in Figure 1.

Arithmetic and Logic Un.lt

The arithmetic and logic unit (ALU) provides all data manipulating logic for the F3850. It contains logic that operates on a single 8-bit source data word or combines two 8-bit words of source data to generate a single 8-bit result. Additional information is reported in status flags, where appropriate.

Operations performed on two units of source data include addition, compare, and the Boolean operations (AND, OR, Exclusive-OR).

The two sources are input to the ALU through the left and right multiplexer buses; the result is placed on the result bus.

Operations performed on a single 8-bit unit of source data include complement, increment, decrement, shift right, shift left, and clear.

The source is input to the ALU through either the left or right multi- plexer bus; the result is placed on the result bus.

Instruction Register

The CPU contains registers for storing various types of data.

The instruction register holds an 8-bit code, which defines the operations to be performed by the CPU.

Figure 1 F3850 CPU Logical Organization

RESULTS BUS

1

~

The contents of the instruction register are decoded by control unit logic, which generates signals to enable specific sequences of logic operations within the CPU chip. In response to the con- tents of the instruction register, the control unit also generates five signals, ROMCo through ROMC4, that control operations throughout the microprocessor system.

Accumulator

The accumulator is a general-purpose 8-bit data register, which is the most common data source and results destination fortheALU.

Scratchpad and ISAR

The scratchpad provides 64 8-bit registers that may be used as general-purpose RAM memory (see Figure 2).

Figure 2 F8 Programming Model

. - - BITNO.

~ __ ^~~~~ __ ^~ ______ ^~I

^ISAR

~

HI NOT INCREMENTED •

OR DECREMENTED .-J

64 x 8-BIT

LO

L

INCREMENTED AND DECREMENTED

~I ACCUMULATOR

J--

^~

r-

^ALU I - I - SCRATCHPAD _REGISTERS 1-

~

... ..

:J ::>

:;

..

t--ffi

^a:

- I

^{STATUS(W) w )(} w

~ ~

r-

...

^::> _:;

~

I

INSTRUCTION

I---

^:t

"

^a:

- i

^ISAR

1-...

i~

I

INTERNAL OAT A BUS

l-

^f----

~ _{I r~~'!} ^t _I I 'j'''-j ^{t I ...}

^{CONTROL LOGIC UNIT INTERRUPT LOGIC DETECT POWER ON CIRCUITS CLOCK}

t ^t ~ ~ i !

E x l

J 11v LL

-

111

1/°07 1/008 DBo DB, ROMCO ROMC. INT ICB

REO

ES X LZ XTLX

3-8

The indirect scratchpad address register (ISAR) is a 6-bit register used to address the 64 scratchpad registers,

The first 16 scratchpad bytes can be identified either by instruc- tions without using the ISAR or referenced through the ISAR.

The remaining scratchpad bytes are referenced through the ISAR;

Figure 3 ISAR Register

ACCUMULATOR 0 LR r, A

~--~~~--~~ GENERAL ^CPU REGISTERS

ISAR

Z E R O - - - - ' CARRY _ _ _ _ _ ...J

11~2

REGISTER ADDRESS POINTER

LRJ,W LRW,J

A B C D SIGN _ _ _ _ _ _ ..J

15 DATA COUNTER

MEMORY ADDRESS POINTER

LRDC,H LRH,DC LRDC,Q LRQ,DC

10

3F

J H H K K 0 0

3-9

F3850

i,e" the ISAR is assumed to hold the address of the scratchpad byte that is to be referenced,

The ISAR may be visualized as holding two octal digits, HI and LO, as illustrated in Figure 3, This division of the ISAR is important, since a number of instructions increment or decrement the con-

10 11

12 PK,PI

13 POP

,.

15 15

16 LRP,K

LRK,P STACK POINTER

63

II

tents of the ISAR, when referencing scratchpad bytes through the ISAR. This makes it easy to reference a buffer consisting of con- tiguous scratchpad bytes. However, only the low-order octal digit (LO) is incremented or decremented; thus ISAR is incremented from 0'27'* to 0'20', not to 0'30'. Similarly, ISAR is decremented from 0'20' to 0'27', not to 0'17'. This feature of the ISAR is very useful in that it greatly simplifies many program sequences.

Selected scratchpad registers are reserved for direct communi- cation with other registers within the F8 system, as illustrated in Figure 4.

Scratchpad register 9 (0'11 ') is used as temporary storage for the CPU status register (W register). Scratchpad registers 10 through 15 (0'12' through 0'17') communicate directly with data

*The notation O'nn' represents an octal number.

Figure 4 F3850 CPU Scratchpad Registers

and program memory address registers that are maintained on the F3851, F3852, and F3853 chips. Figure 4 identifies the data transfers that can be implemented by executing a single F8 instruction. For example, the illustration:

W register of F3850 CPU - J

means that a single instruction can move the contents of the W (or status) register to scratch pad register 9 (J register). Another single instruction can move data in the opposite direction.

Status Registers

The status (W) register holds five status flags. Table 1 summarizes the way each flag is used. Note that status flags are selectively modified following execution of different instructions. See the

"Instruction Execution" section for a discussion of the way individual F8 instructions modify status flags.

SCRATCHP4D BYTE ADDRESS SCRATCHPAD DECIMAL OCTAL

§

W REGISTER OF F3850 CPU _ J 11

DC REGISTER OFF3851 PSU. F3852 OMI AND F3853 SMI

!

~

-!

^{H ( HU} HL ¹⁰ ₁₁ ¹² 13 PCOORPC1 (STACK) REGISTER OFF3851 1. ~l ^{KU 12 14 '}

PSU F3852 DMI AND F3853 SMI \ (KL 13 15

DC OR PCO REGISTER OF F3851 PSU F3852 DMI AND F3853 SMI

l

- ^(QU

j

QL ^{14 16} 15 17 16 20

58 72 59 73

60 74

61 75 62 76

63 77

3-10

I C

B o

~BITNO.

z

I

^C

I I

STATUS REGISTER (W)

~ ^{L LSIGN}

^CARRY

ZERO

OVERFLOW

INTERRUPT MASTER ENABLE

Sign (S Blt)-When the results of an ALU operation are being interpreted as a signed binary number, the high-order bit (bit 7) represents the sign of the number. At the conclusion of instruc- tions that may modify the accumulator bit 7, the S bit is set to the complement of the accumulator bit 7.

Table 1 Summary of Status Bits OVERFLOW

ZERO CARRY SIGN

= CARRY7

+

CARRY6

= ALU7 ALU6 ALU5 ALU4 ALU3 ALU2 ALU1 ALUo

= CARRY7

= ALU7

Carry (C Blt)-The C bit may be visualized as an extension of an 8-bit data unit; i.e., the ninth of a 9-bit data unit. When two bytes are added, and the sum is greater than 255, then the carry out of the high-order bit appears in the C bit; e.g.:

Accumulator contents:

value added:

C 7 P 5432 1 0 - Bit Number 01100101

01110110 Sum: 0 1 1 0 1 1 0 1 1 There is no carry, so C is reset to O.

C 7 6 5 4 3 2 1 0 - Bit Number Accumulator contents: 1 00 1 1 1 0 1

value added: 11010001 Sum: 1 0 1 1 0 1 1 1 0 fhere is a carry, so C is set to 1.

Zero (Z bit)-The Z bit is set whenever an arithmetic or logical operation generates a zero result. The Z bit is reset to 0 when an arithmetic or logical operation could have generated a zero result but did not.

3-11

F3850

Overflow (0 Blt)-When the results of an ALU operation are being interpreted as a signed binary number, since the high-order bit (bit 7) represents the sign of the number, some method must be provided for indicating a carry out of the highest numeric bit (bit 6). This is done using the 0 bit. After arithmetic operations, the 0 bit is set to the Exclusive-OR of a carry out of bits 6 and 7.

The simplification of signed binary arithmetic is described in the

F8 and F3870 Guide to Programming; examples are presented

II

below:

Accumulator contents:

value added:

Sum:

76543210 - Bit Number 10110011

01110001 11100100

There is a carry out of bit 6 and a carry out of bit 7, so the 0 bit is reset to 0 (1 EEl 1 = 0). The C bit is set to 1.

Accumulator contents:

value added:

7 6 5 4 3 2 1 0 - Bit Number 01100111

00100100 Sum: 10001011

There is a carry out of bit 6, but no carry out of bit 7; the 0 bit is set to 1 (1 EEl 0 = 1). The C bitis reset to O.

Interrupts (ICB Blt)-Externallogic can alter program execution sequence within the CPU by interrupting ongoing operations.

However, interrupts are allowed only when the ICB is set to 1;

interrupts are disallowed when the ICB is reset to O.

Control Unit

The control unit decodes the contents of the instruction register and generates two sets of control signals. These signals are transparent to the user.

Five control signals (ROMCo through ROMC4) are output by the control unit to identify operations that other chips of the Fa family must perform. These signals are described in the "ROMC Signals" section.

Interrupt Logic

This logic handles the interrupt requests. For a complete description refer to the "Interrupt" discussion within the

"Instruction Execution" section.

Power on Detect

When the External Reset (EXT RES) signal is pulled low and then returned high, or when power is turned on, the power on detect logic sets the PC registers to 0, causing a program originating at memory location 0 to be executed. Also, the interrupt control status bit is set low, inhibiting interrupt acknowledgement. The system is locked in an idle state while EXT RES is held low.

Signal Descriptions

The F3850 input and output signals are described in Table 2.

"nIble 2 F3850 Signal Descriptions

Mnemonic Pin No. Name Description

Clock

tf> 1 Clock These output signals drive all other devices in the F8 family.

WRITE 2 Write

XTLX 39 Crystal Clock The XTLX output Signal is used when generating the system clock in the crystal mode (with the XTL Y and XTLZ signals).

XTLY 38 External Clock The XTL Y input signal is used with the XTLX signal when generating the system clock in the crystal mode, and is also used for operating in the external clock mode.

XTLZ 40 Crystal Clock This input signal must be grounded for crystal clock or external clock.

VOPort

1/000-1/007 16,11,10,5,36,31,30,25 1/0 Port Zero These bidirectional signals are ports through which the CPU communicates with logic external to the microprocessor system.

1/010-1/017 14, 13, 8, 7,34,33,28,27 I/O Port One Intern.lpt

ICB 22 Interrupt Control The ICB output signal indicates whether or not the CPU is Bit currently ignoring the INT REO line. If the ICB signal is low, the

CPU responds to interrupt requests; if the ICB signal is high, the CPU ignores interrupt requests.

INTREO 23 Interrupt Request This input line is used to signal the CPU that an interrupt is being requested.The F3851 PSU, F3861 and F3871 PIOs, and F3853 SMI devices contain logic to initiate interrupt requests by pulling the INT REO signal low. The CPU acknowledges interrupt requests by outputting the appropriate ROMC signals.

Control

ROMCo- 17-21 Control The ROMC output signals control logic operations for other

ROMC4 devices in the F8 family. These signals assume a state early in

each machine cycle and hold that state for the duration of the cycle. Refer to the "Instruction Execution" section for further discussion and a summary table of the ROMC interpretation by CPU logic.

3-12

Table 2 F3850 Signal Descriptions (Continued)

Mnemonic Pin No. Name

Reset

EXT RES :r7 External Reset

Data Bus

DBo-DB7 15, 12, 9, 6, 35, 32, 29, 26 Data Bus

Power

VDD 3 Power Supply

VGG 4 Power Supply

Vss 24 Ground

Clock Circuits

A unique feature of the F8 microprocessor is that clock logic forms an integral part of the F3850 CPU chip. The F3850 CPU offers two methods of generating a system clock: crystal mode and external mode.

Crystal Mode

Figure 5 shows the pin configuration for clock generation using the crystal mode. A crystal in the 1- to 2-MHz range is placed across the XTLX and XTLY pins, along with two capacitors (C1 and C_2), to provide a highly precise clock frequency. The external crystal (and capacitors) together with internal circuitry combine to form a parallel resonant crystal oscillator. Capacitors C1 and C2 should be approximately 15 pF. The characteristics of the crystal

Figure 5 Crystal Mode Clock Generation

Vss

XTLZ

C,

XTLY F3850

CPU

T

^XTLX

1

^C,

Vss

T

F3850

Description

This input signal can be used to externaliy reset the system.

When the line is pulled low, a program originating at memory address 0 is executed.

These eight bidirectional signals are data bus lines that link the F3850 CPU with all other F8 devices in the system. They are multiplexed lines used to transfer data and addresses.

Nominal +5Vdc Nominal +12 Vdc

Common power and signal return

3·13

used in this mode of clock generation are summarized as:

Frequency: 1 to 2 MHz, typical AT cut Mode of Oscillation: Fundamental Operating Temp. Range: O°C to +70°C Drive Level: 10 mW

Frequency Tolerance: fa = 1 or 2 MHz±1000 ppm @ CL

=20pF External Mode

For F8 applications where synchronization with an external sys- tem clock is desired, the external clock mode may be used as shown in Figure 6. For example, a slave F3850 CPU may receive its timing from a master F3850 CPU by having the master c/> output drive the slave XTLY input.

Figure 6 External Mode Clock Generation

Vss

EXTERNAL CLOCK

XTLY

XTLX

F3850 CPU

•

Figure 7 illustrates the timing characteristics of the clock signal needed for external mode clock generation and the timing characteristics of the cf> and WRITE signals generated by the CPU.

Timing Signal Outputs

In response to the three clock mode inputs, the F385a CPU outputs two timing signals: clock signal cf> and instruction cycle control signal WRITE. As shown in Figure 7, cf> is the signal used to synchronize the entire microprocessor system. The WRITE signal defines the duration of each machine cycle. Refer to the

"Instruction Execution" section. Parameters and specifications for the timing signals are detailed in the "Timing Characteristics"

section.

Instruction Execution

The F385a CPU logic controls instruction execution through the cf> and WRITE timing signals, plus the five ROMC control lines. Devices external to the F385a CPU must respond directly to these signals.

Instruction Cycle

All instructions are executed in cycles that are timed by the trailing edge of WRITE.

There are two types of instruction cycle: the short cycle, which is four cf> periods long, and the long cycle, which is six cf> periods long.

The long cycle is sometimes referred to as 1.5 cycles. Figure 7 illustrates the short cycle (PWs ) and the long cycle (PWd. Note that WRITE high appears only at the end of an instruction cycle.

The simplest instructions of the F8 instruction set execute in one short cycle. The most complex instruction (PI) requires two short cycles plus three long cycles.

Figure 7 Clock Generation Timing Signals

I --P'-I

PWk ---..

1"-

XTLY

ROMC Signals

The CPU logic uses the five ROMC signals to identify operations that devices must perform during any instruction cycle. The 32 possible ROMC states are described in the "ROMC Signal Functions" section. The state of the ROMC signals and the operation they identify last through one instruction cycle.

The general distribution of logic among devices of the F8 family and general data movements associated with instruction execution are given in the F8 and F3870 Guide to Programming.

Memory addressing logic is located on the F3851 Program Storage Unit (PSU), the F3852 Dynamic Memory Interface (DMI), and the F3853 Static Memory Interface (SMI) devices.

Each of these devices contains registers to address programs (PCa and PC1) or data (DCa or DC1). The F3851 PSU does not have a DC1 register.

Unlike other microprocessors, the F385a CPU does not output addresses at the start of memory access sequences; a simple command to access the memory location addressed by pca or DCa is suffiCient, since the device receiving the memory access command contains pca and DCa registers. (The PC1 and DC1 are buffer registers for pca and DCa.)

Moving memory addressing logic from the CPU to memory (and memory interface) devices simplifies CPU logic; however, it creates the potential for devices to compete when responding to memory access commands.

There will be as many PCO and DCa registers in a microcomputer system as there are PSU, DMI, and SMI devices; the ambiguity of which unit will respond to a memory read or write command is resolved by ensuring that all pca and DCa registers contain the same information at all times. Every PSU, DMI, and SMI device

I-- ~ I-

^td'

td,

_I P~

^....

~~~~---

^PWs

---<~~I

--.A N1\...-_ _ _ ----IL __ ]---..11 ~l\--_

WRITE

k-

^pW,

^j '""I.~---

P w L - - + - l - - - -__

1

3-14

has a unique address space, i.e., a unique block of memory addresses within which it responds to memory access commands.

For example, an F3851 PSU may have an address space of H'OOOO' through H03FF'; an F3852 DMI may have an address space of H'0400' through H'07FF'. If a microcomputer system has these two memory devices and no others, then the F3851 PSU will respond to memory access commands when the PCO or DCO registers (whichever are identified as the address source) contain a value between H'OOOO' and H03FF'; the F3852 DMI will respond to addresses in the range H'0400' through H07FF'. No device will respond to addresses beyond H'07FF', even though such addresses may exist in PCO and/or DCO.

Each device compares its address space with the contents of PCO and DCO, whichever is identified as the address source, and only responds to a memory access command if the contents of PCO or DCO is within the device's address space.

If all memory address registers (PCO, PC1, DCO, and DC1) are to contain the same information, then ROMC states that require any of these registers' contents to be modified must be acted upon by all devices containing any of these four registers. If devices are not to compete when an ROMC state specifies that a memory access must be performed, then only a device whose address space includes the identified memory address must respond to the ROMC state.

As illustrated in Figure 8, the five ROMC signals that define the ROMC state are output early in the instruction cycle and are main- tained stable for the duration olthe instruction cycle; i.e., only one ROMC state can be specified per instruction cycle. Therefore, devices can only be called upon to perform one instruction execu- tion related operation per one instruction cycle.

Figure 8 ROMC Timing Signals Output by F3850 CPU

1_

td,

F3850

As referenced in the "ROMC Signal Functions" section, each ROMC state is identified by individual signal line states (1 for high, 0 for low), and by a two-digit hexadecimal code. The hexadecimal code is used to identify ROMC states throughout this data sheet. Also given in the "ROMC Signal Functions" section is the instruction cycle length (short or long) implied by each code, plus the way in which codes must be interpreted by the other F8devices.

Instruction Execution Sequence

Every instruction execution sequence ends with an instruction code being fetched from memory to identify the next instruction cycle. The instruction code is loaded into the CPU instruction register, out of which it is decoded by the CPU control unit logic.

An instruction fetch is executed during the last instruction cycle of the previous instruction, as illustrated in Figure 9.

There is a group of F8 instructions that cause operations to occur entirely within the F3850 CPU. These instructions do not use the data bus, therefore can execute in one cycle. Since one-cycle in- structions do not use the data bus, no ROMC state needs to be generated for the one-cycle instruction being executed; therefore, as illustrated in Figure 9, ROMC state 0 is specified, causing the instruction fetch of the next instruction.

Multi-cycle instructions must end with a cycle that does not use the data bus; ROMC state 0 is specified at the beginning of this last instruction cycle, causing the next instruction to be fetched.

Following an instruction fetch, CPU logic decodes the fetched instruction code and executes the specified instruction. There are Five types of instruction cycles that can follow.

1. Operations may all be internal to the CPU. This will be the last or the only cycle for an instruction, and will specify ROMC state 0, as illustrated in Figure 9.

WRITE

\ _____________

^~L

___

^~

___

^~/

r---, _____

^\~

l~td3_.1 LONG CYCLE

ROMe

_______________________ --J){r---S-T-AB-L-E---

3-15

•

Figure 9A Short Cycle Instruction Fetch

XTLY

WRITE

ROMC

Id, -r- ^{P~ --=:1} r

^td,

__ ^~AI N _____________________ ^{I ~~---}

_ PW2-111 __ "

----PWL----~rl

I II

______________________ I ______

-'){~~

___________________

T_R_U_E_RO_M_C_S_TA_~

^__ O __________________

~I~I---

^___

J.:- Id. -I I I

I

I--~I

---I---~XOPCODEFORNEXTI ONE CYCLE OF THE SINGLE. LONG

CYCLE DS INSTRUCTION (DECREMENT SCRATCHPAD)

• •• INSTRUCTION

Figure 98 Long Cycle Instruction Fetch (During DS Only)

XTLY

b,-J r--1

WRITE

ROMC

DATA BUS

Id'~i~ ~~~~---PWs---~·1

____ t ^N_~ _ _ _ _ _ _ _ ---,I NL. _ _ _ _

I-PW2--l1 II

I II

---~I---X

^{• .•}

... ________ ---III

TRUEROMCSTA~O

I--Id,-I II

I 1-- Id.,. ---J I

---~X

OP CODE FOR NEXT INSTRUCTION ONE CYCLE OF A SINGLE CYCLE

INSTRUCTION, OR LAST CYCLE OF A MUL nCYCLE INSTRUCTION

3·16

NEXT INSTRUCTION

2. Data may be transferred between the F38S0 CPU and memory devices. See the "Referencing Memory" section.

3. Data may be transferred from one memory device to all memory devices. The CPU is not the transmitter or the receiver of data in this transfer. See the "Memory-to-Memory Data Transfers" section.

4. Data may be transferred to or from an 1/0 port, as described in the "lnpuVOutput Interfacing" section.

5. An interrupt may be acknowledged, as described in the

"Interrupts" section.

Every F8 instruction is executed as one, or a sequence of, standard instruction cycles. Timing for the standard instruction cycles is illustrated in Figures 9, 10, 11 and 12.

Figure 10 Memory Reference Timing

F3850

Refer to the "Instruction Cycle Execution and Timing" section for a list of the instruction cycles and their associated ROMC state.

Referencing Memory

Memory may be referenced during an instruction cycle either to transfer the data from the CPU to a memory word or to transfer data from a memory word to the CPU. A memory reference

occurs as shown in Figure 10. •

If data is being output by the CPU, then the delay before data out- put is stable will be tdb1 when data comes from the accumulator;

the instruction cycle will be long. The delay before data output is stable will be tdb2 when data comes from the scratchpad; the instruction cycle in this case will also be long.

11 . .

: - - - P W s - - - J

(WRITE)

.../r----'li~\,---....1

~I·~---I~,--~---~

PWL

N ^-I

I _I I L.

1 1

-I I I

DATA BUS (1)

I X

1~.---Idb·--

__

¹

I

(HIGH IMPEDANCE)

DATA BUS (1)

X

1~.~---ldb2---~~ ·1

^STABLE

I

DATA BUS

DATA BUS

DATA BUS

(1) liming for CPU outpulling data onto the data bus.

Delay tdb, is the delay when data is coming from the accumulator.

Delay tdb2 is the delay when data is coming from the scratchpad (or from a memory device).

Delay tdbo is the delay for the CPU to stop driving the data bus.

3-17

X

I·

^Idb,

^-I

I'

^Id".

^-I

X

DATA STABLE

I

I'

^Id",

^-I

X

DATA STABLE 1

(2) There are four possible cases when inputting data to the CPU. via the data bus lines which depend on the data path and the destination in the CPU. as follows:

tdb,.: Destination -IR (instruction Fetch)

tdb.,: Destination - Accumulator (with ALU operation - AM) tdbs: Destination - Scratchpad (LR K.P etc.)

tdbo;: Destination - Accumulator (no ALU operation - LM)

In each case a stable data hold time of 50 ns from the WRITE reference point is required.

Figure 11 Timing for Data Input or Output at 1/0 Port Pins

(WRITE)J

' _ 4

- - P W S - - - I - '

~~ ________ ^~ ____ ^~/~--~N _________ __

~11_lh

•• - - - -

I," ----~~II

---~---~ ,---

1/0(1) DATA MAY CHANGE STABLE

I

OAT A MAY CHANGE

1

1 ... . . - - - -¹⁰ ----~---I

110 (2)---I---DA-T-A-F-R-0-M-0-L-O.-0-UT-S---...

X',,~~~~~~~~N~E-W_-_D~A-T_A~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=

(1) This represents the timing for data at the I/O pin during the execution of the INS instruction, Le., the CPU is inputting.

Figure 12 Interrupt Signals Timing

14

PWs

W R I T E J ' l -PW 2 ---..

r I_

I

ROMC

:~ld3~

r l d ' - - I

ICB(1) 1

X

I

I _ · d ' : : j INTREQ(2)

I ~

I

I'

^Id,

INTREQ(2) 1

EXT RES

'\ 14

(1) The ICB signal will go from a 1 .to a 0 following the execution of the E1 instruc- tion and will go from a 0 to a 1 following either the execution of the 01 instruc- tion or the CPU's acknowledqement of an interrupt.

TRUE

3-18

(2) This represents the timing for data· being output by the CPU at the liD pin.

-I / '--

/ N

PWL

-I

I I I I

-I I ^I _I I I

!"

-I

I

(2) This is an input to the CPU chip and is generated by a PSU or F3853 M1 chip.

The open drain outputs of these chips are all w~re-ANDed together on this line with the pull-up being located on the CPU chip. For a 0 to 1 transition the delay is measured to 2.0 V.