A New Orthogonal Online Digital Calibration for Time-Interleaved Analog-to-Digital Converters

A New Orthogonal Online Digital Calibration for Time-Interleaved Analog-to-Digital Converters

G. Ferré, M. Jridi, L. Bossuet, B. Le Gal and D. Dallet

IMS Laboratory – CNRS UMR 5218 - ENSEIRB – University of Bordeaux 1 351 Cours de la libération 33405 Talence Cedex - France

{guillaume.ferre, maher.jridi, lilian.bossuet, bertrand.legal, dominique.dallet}@ims-bordeaux.fr Abstract–Modern communication technologies need faster analog-

to-digital converters (ADC). To significantly increase the sampling rate of an ADC, time-interleaved ADC (TIADC) is an efficient solution. A M-channels TIADC is composed of M ADCs which operate at interleaved sampling times. Due to the manufacturing process, the main drawback of a TIADC system is that the M ADCs are not exactly the same. This means that offset, gain and time mismatch errors are introduced. As a result, these errors cause distortions in the output sampled signal and introduce unwanted tones and noise, and hence, reduce the spurious free dynamic range (SFDR) as well as the signal to noise ratio (SNR). In this paper, we propose a new orthogonal online digital calibration, for timing skew, offset and gain mismatches, based on Code Division Multiple Access (CDMA) technique already used in communications. Our calibration is online, this means that errors can be estimated while the ADC is running. Since most of the calibration processes are carried out on the digital outputs, very little change is needed on the analog part of the ADC. Simulations results showed the efficiency of our proposed calibration architecture.

I. INTRODUCTION

In recent years, the increasing trends of communication systems, such as ultra-wide band (UWB) or software defined-radio, have resulted in applications requiring analog-to-digital converters operating at very high rates [1]-[3]. These investigations are issued from the originally work of Black and Hodges [4] about TIADC (Fig. 1). The TIADC system works as follows:

¾ the input signal is connected to all the ADCs,

¾ if the TIADC is composed of M ADCs, each of them works with a sampling interval of MTs, where Ts =1/Fs is the sampling rate of the overall system,

¾ the clock signal of the kth ADC is delayed with kTs.

Ideally, the ADCs should have the same characteristics, and should sample the input signal with timing phases uniformly spaced in time.

Unfortunately, the main difficulty with the interleaved structure is that, due to the manufacturing process, all the ADCs are not identical and mismatch errors and timing jitter effects will occur in the system. The three main mismatch errors will be treated in this paper.

Offset errors: the ground level differs between the different ADCs, i.e. there is constant amplitude offset in each ADC.

Gain errors: The gain, from analog input to digital output, differs between the different ADCs.

Timing errors: they are two kinds of timing errors to be identified.

Clock skew (determinist): the delay times of the clock between the different ADCs are not equal, i.e. the signal will be periodically but nonuniformly sampled. Random jitter (random

phase noise): random jitter is mainly due to device noise and random noise coupled from the power supply and substrate.

Figure 1. Time-interleaved ADC architecture

The resulting gain, offset and timing mismatches can degrade performance significantly [5], so they need to be estimated and corrected.

With a sinusoidal input, the mismatch errors can be seen in the output spectrum as distortion. With input signal frequency f₀, the gain and time errors cause distortion at the frequencies

s f0

kF M ± , whereas offset errors cause distortion at kF M_s , where

1, 2, ,

k= " M . Fig. 2 shows a TIADC output spectrum composed

of 4 ADCs.

In this paper, a digital calibration method for TIADC based on orthogonal code properties is introduced. Some works have already been done on this subject [6] but with only offset and gain error calibrations. Using the same approach, a new algorithm allowing a total online digital calibration (time, offset and gain) is proposed and presented in this paper.

The utility of orthogonal sequences in data-channel separation has been proved, as the case of spread-spectrum like CDMA [7] used for example in wireless and optical communications. In this paper, we propose to use separation property of orthogonal sequences in order to uncorrelate the contributions of time skew, offset and gain mismatches.

The paper is organised as follows. In section II notations and definitions used in the paper will be defined. A new orthogonal online digital calibration algorithm will be proposed in section III.

This work has been done with financial partnership of Délégation Générale pour l’Armement

978-1-4244-1684-4/08/$25.00 ©2008 IEEE 576

Section IV contains simulation results and finally section V presents conclusions.

Figure 2. Output spectrum from TIADC system composed of 4 ADCs.

II. NOTATIONS AND DEFINITIONS

In this section, all the different notations used in the paper are explained. The TIADC input signal will be noted,

( ) sin(2 0 )

x t = ×A πf t (1)

where A and f₀ are respectively the input signal maximal amplitude and frequency. M denotes the number of ADC in the TIADC, and the nominal sampling period of the overall system is Ts. ADC resolution will be noted n_b and time vector acquisition length (FFT size) L.

Gk, O_k and Δt_k represent respectively, gain, offset and clock skew associated to the kth ADC, with 1≤ ≤k M^.

Random jitter δt_k is assumed to have a uniform distribution within a range of ±0.5% of the sampling period, i.e.

[

]

k s s

t T T

δ ∈ − + . Clock skews are supposed to be

within the same range with different fixed value for each ADC.

We assume throughout this paper that x t( ) is bandlimited to the Nyquist frequency of the TIADC. We suppose that the errors (timing skew, offset and gain) are static or slowly time varying. It means that these errors can be assumed to be constant for the same ADC from one cycle to the next over an interval of some million samples.

III. ORTHOGONAL CALIBRATION ALGORITHM In this section, we propose a new online calibration method. The algorithm is based on orthogonal properties between two vectors, B andC of length L, defined such as:

1

0

( ) ( ) 0

L

n

B n C n

−

=

¦

and

1 1

0 0

( ) ( ) and ( ) ( )

L L

n n

B n B n L C n C n L

− −

= =

= =

¦ ¦

with ( )B n = −( 1)ⁿ and ( )C n =1, ∀ ≤ ≤ −0 n L 1.

Just before analog to digital conversion, the input signal of length L is multiplied by B, on each TIADC channels. So, the nth input sampling signal from the kth ADC is:

, ( ) ( ) sin(2 0 )

k n B s

x n = ×A n × πf nT (4)

with n =(k+Mn), and 0≤ ≤ −n L 1

In practice, it is important to note that B will be an analog square signal of period MT_s, range between ±FS/ 2 where FS is the ADC full-scale range.

If y n_k( ) denotes the nth output sampling signal from the kth ADC, we can write:

( ) ,( ) ( )

k k n k

y n =x n B n +O (5)

where,

, ( ) sin(2 0( ))

k n k s k k

x n = AG πf nT + Δ +t δt (6) By using sin(a+b) trigonometry property, we can rewrite (6) as:

0 0

,

0 0

sin(2 ) cos(2 ( ))

( )

cos(2 ) sin(2 ( ))

k k

k n k

k k

s

s

f nT f t t

x n AG

f nT f t t

π π δ

π π δ

= Δ +

+ Δ +

§ ·

¨ ¸

© ¹

(7)

As 2πf₀(Δ +t_k δt_k)1, using the first term of sinus and cosines Taylor developments, (5) becomes:

0

0 0

( ) ( ) sin(2 )

2 ( )( ) cos(2 )

k k

k k k

k

s

s

y n AG B n f nT

f AG B n t t f nT

O

π

π δ π

+ Δ +

+

(8)

A. Offset estimation

Generally, calibration process needs error estimation phase before correction. The first step of the algorithm proposed is to estimate the offset, which is easily done by the following relation:

ˆ 1

k k

O T

L

= y ×C (9)

B. Gain and clock skew estimation

The second step is dedicated to gain and clock skew estimation, which implies offset cancellation. This is done using the zero mean property of B:

1 _T

k k

L

=

y y B (10)

With relation (8), we can write the nth sample of (10) as:

0

0 0

( ) sin(2 )

2 ( ) cos(2 )

k k

k k k

s

s

n AG f nT

f AG t t f nT

π

π δ π

+ Δ +

=

y

(11) The previous equation shows the correlation between (Δ +t_k δt_k) and G_k leading to a linear equation system with two unknowns:

(Δ +t_k δt_k) and G_k. This problem will be solved using matrix notations. Let us consider the following vectors:

[ ]

[ ]

, , , ( 1)

, , , ( 1 )

(0), , ( ), , ( 1)

(0), , ( ), , ( 1)

k k k k n k k M L

k k k k n k k M L

V V n V L

W W n W L

+ −

+ −

= −

= −

­ ®

¯

" "

" "

V

W (12)

where

577

, 0

, 0

( ) sin(2 )

( ) cos(2 )

k n

k n

s

s

V n A f nT

W n A f nT

π π

=

=

(11) becomes:

2 0( )

k k k k k k k

Tk

G G πf t δt

= + Δ +

y V W (13)

As (13) is over determined, two auxiliary equations (14) and (15) was formed:

for 0≤ ≤n L 2 1− ,

(1) (1 ) (1 )

k k k k k

k =G +G T

y V W (14)

and for L 2≤ ≤ −n L 1,

(2) ( 2 ) ( 2 )

k k k k k

k =G +G T

y V W (15)

with ^y_k =

ª ¬

º ¼

ª ¬

º ¼

ª ¬

º ¼

Finally, by combining (14) and (15), it has been shown that analytical estimations of clock skew and gain are:

( 2 ) ( 2 ) (1) ( 2 )

(1 ) ( 2 ) ( 2 ) (1)

k

k k k k

k k k k

m m m m

T

m m m m

=

−

−

y V y V

y W y W

,

(1 )

(1 ) (1 )

k

k k

k k

m G

m T m

=

−

y

V W

(16)

where

2 1

0

2 ( )

L

n

m u n

L

−

=

=

¦

u .

C. Calibration process

Finally we obtain the corrected output digital signal:

( )

ˆk = k−Oˆk −Tk k

/

y y C W (17)

Calibration process leads to cancel offset, gain and clock skew mismatch errors. We can remark that relation (11) proposes a direct cancellation of the offset. So, for the architecture implementation, a simplification of (17) could be done using (11) instead of (8). Thus (17) becomes:

( )

ˆ_k = _k−T_{k k}

/

y y W (18)Ҟ

IV. SIMULATION RESULTS

To evaluate the efficiency of the new TIADC calibration algorithm presented in this paper, a time-interleaved ADC system composed by two ADCs has been simulated. Two kinds of simulation results are presented: clock skew and gain errors estimation. For each case, sampling and input frequencies ratio, resolution and FFT size influence on the estimation are shown. It means that error estimation was computed by:

theoretical value estimated value theoretical value

− (%)

Clock skew was set to: Δ = −Δt¹ t²

= [

]

Fig. 3 and 4 show respectively the precision of clock skew and gain errors estimations for frequency ratio (f₀/F_s) set to 499/2048, 499/4096 and 499/8192. Lower is the frequency ratio, more precise are the estimations. And lower are the clock skew errors, higher is the precision. The estimation is very efficient because (in Fig. 3) with the previous condition, time precision is between 1.2 10× ⁻⁵ and 5 10× ⁻8, and gain precision between 1 10× ⁻⁵ and 5 10× ⁻⁸ in Fig. 4.

Figure 3. Phase errors estimation, sampling frequency impact. TIADC with M=2, 1024 FFT points, nb=8 bits, G1=1.3 and G2=0.98

Figure 4. Gain errors estimation, sampling frequency impact. TIADC with M=2, 1024 FFT points, nb=8 bits, G1=1.3 and G2=0.98

B. TIADC resolution influence

Fig. 5 shows that TIADC resolution has no influence on gain and clock skew errors estimation. Moreover, estimations are extremely close to the real distortion parameters. Fig. 6 shows the resolution influence on SNR during the estimation. Performances are extremely interesting because our SNR is very close to the theoretical expression (6.02nb+1.76 dB).

Figure 5. Gain and phase errors estimation. Resolution impact. TIADC with M=2, 1024 FFT points, G1=1.3, G2=0.98, O1=0.05A and O2=-0.2A

578

Figure 6. SNR evolution. Resolution impact. TIADC with M=2, 1024 FFT points, G1=1.3, G2=0.98, Δt1= -Δt2 =0.001Ts,O1=0.05A and O2=-0.2A

C. FFT size influence

Fig. 7 shows that FFT size has no influence on the precision and ones more you can see our algorithm efficiency.

Figure 7. Gain and phase errors estimation. FFT size impact. TIADC with M=2, 1024 FFT points, G1=1.3, G2=0.98, O1=0.05A and O2=-0.2A

D. TIADC Output spectrum

The results (Fig. 8 (a), (b)) show that SFDR improves 38.25dB and SNR 1.5dB. Also, we can see that distortions are completely cancelled.

V. CONCLUSION

In this paper, a digital online calibration technique to suppress offset error and to reduce gain and clock skew error effects in TIADC is proposed. This technique is based on orthogonal sequence properties and it doesn’t require any input signal timing information.

Simulation results show that our proposed method is very efficient regardless to the clock skew and gain errors estimation. Clearly, we are able to find an optimal trade-off between performances and complexity in order to propose hardware implementation.

An improvement in SFDR can be obtained depending on the input frequency and the resolution. The advantages of this technique are that no major change in the analog circuits is required and most of calibration and processing steps are carried out in digital domain.

(a)

(b)

Figure 8. FFT spectrum before (a) and after (b) calibration. TIADC with M=2, 1024 FFT points, nb=8 bits, G1=1.3, G2=0.98, Δt1= -Δt2 =0.001Ts,

O1=0.05A and O2=-0.2A

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