New Adaptive Calibration Method for Time Interleaved Analog to Digital Converters

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New Adaptive Calibration Method for Time Interleaved Analog to Digital Converters

Maher Jridi, Lilian Bossuet, Bertrand Le Gal and Dominique Dallet IMS Laboratory-UMR CNRS 5218-ENSEIRB University of Bordeaux

351 cours de la lib´eration, 33405 Talence Cedex Email: maher.jridi@ims-bordeaux.fr

Abstract— To increase the sampling rate of Analog to Digital Converters (ADC), Time-Interleaved ADC (T IADC) is an efficient solution. However, offset mismatch, gain mismatch, and timing errors between time-interleaved channels limit the T IADC performances. This setting presents a new adaptive method for gain and offset mismatch error compensation. The technique proposed is based on adaptive filtering process using DLMS algorithm. Mixed simulations using V HDL−AMS language show spectral performance improvement. A material implementation onF P GAis presented to evaluate the consumed resources.

I. INTRODUCTION

In new communication receivers, the trend is to take profit of Digital Signal ProcessingDSP flexibility to improve receiver architecture consumption by avoiding Intermediate Frequency F I architecture. In this way, Analog to Digital Converter ADC, which is the interface between analog environnement and digital circuits, should be placed close to the antenna. To comply with these requirements, ADC should provide high sample rate and high resolution to digitize the high speed and the significant dynamic antenna signal: this is the today’s ADC challenge.

A state of the art of more than 200 ADC with different architectures is given in [1]. The most important results of this study are summarized in figure 1. It has been shown that the effective number of bit (ENOB) and the sampling frequency f_s cannot increase in the same time. Therefore, with existing communications standards such CT N,UMT S and base station for GSM the availableADC are sufficient.

However, with the new telecommunication trends, only one converter cannot achieve all the needed requirements. To solve this problem, one solution consists in parallelizing existing ADCcores on a die to increase the sampling rate for the same resolution [2]. The resulting system is called Time Interleaved Analog to Digital Converter (T IADC). Figure 2 describes a T IADC structure using two ADC. The T IADC has a parallel structure, where the input analog signal is successively sampled by each ADC (demultiplexer). The digital output is taken from each ADC and reconstructed by means of a multiplexer The T IADC output has a resolution ofnbit and a sample rate2 times over that of a single channel.

This concept is widely adopted in the test and measurement industry, particularly for wide band digital oscilloscopes.

T IADC impact in this market is evidenced by the 20-GSPS, 8-bitADCthat was recently developed by Agilent Labs. This

Fig. 1. ADCstate of the art

T IADC structure uses 80 ADCs, each one has a sampling rate of 250-MSPS [3].

Although time-interleaved ADC systems thrive at the 8-bit level, they continue to fall short in applications that require high resolution, dynamic range and wide bandwidth. In fact, T IADC systems introduce new set of problem: mismatch errors. Indeed, each converter is characterized by its proper errors caused by manufacturing process imperfections and these errors are classified in two kinds:

• the static errors including offset, gain and non linearities,

• the dynamic errors including aperture jitter and timing skew.

Obviously, these errors are constant during conversion cycle for one converter but they are different from one converter to another. So, when different converters are assembled in T IADC, differences (mismatches) between data converters cause significant distortion and decrease the whole system effective resolution. Therefore, to combine resolution and speed inT IADC, mismatch error calibration method is needed. In literature, calibration methods are applied to reduce offset and gain mismatchs ([4], [5], [6]) and non-linearities compensation methods are presented in [7], [8]. Regarding dynamic errors, [9] proposes a method to compensate timing error. The future directions in term ofT IADCcalibration methods are focused on digital adaptive correction for all errors [10].

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Fig. 2. T IADCprinciple

In this paper, a special attention is given toT IADC compensation method using adaptive filtering. Simulation results and F P GA implementation validate the proposed method.

The paper is organized as follows: problem formulation is introduced in section 2. In section 3, the method proposed is introduced, showing the principle and some simulation results.

F P GA implementation are exposed in section 4 to validate the method proposed.

II. PROBLEM FORMULATION

This section reviews the effects of offset, gain, and timing mismatch in T IADC. These errors are the results of imperfections in manufacturing process. They are different from one converter to another. To simplify the analysis, T IADC with only two converters is considered. In spectral point of view, mismatch offset causes dC non harmonic component and spurs at ^f₂^s, figure 3. Gain and timing mismatchs cause spurs at

fs

2 −f_in, where f_in represents the input signal frequency.

The magnitude of all these components depends on input and sampling signal characteristics. The influence of static errors in SNR parameter is shown in 1.O represents difference between channel offsets,Gcharacterizes gain difference between interleaved channels andN refers to the converter resolution.

In addition, jitter differences between converters increase the output spectrum noise floor.

SNR=6.02N+ 1,73

−10log₁₀(3×2^2N−1O+ 1)

Offset−loss

−10log10(3×2^2N−1∆G+ 1) + 20log10G

Gain−loss

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Since these errors depend on the input signal characteristics, their positions and magnitudes change by changing the input signal characteristics. Consequently, to remove spurs of figure 3, pass band filter is not enough. Calibration method should be adaptive.

III. PROPOSED CALIBRATION METHOD

In this section the proposed method for mismatch error calibration is detailed.

0 0.1 0.2 0.3 0.4 0.5

−70

−60

−50

−40

−30

−20

−10

Normalized frequency

Magnitude (dB)

Gain and timing skew mismatch component Offset mismatch

component

Fig. 3. Error mismatch effects

ADC1

ADC2

Interpolation

D1

M U X D2

Proposed calibration mehod

FIR - +

LMS filter d(n)

u(n)

e(n) y(n)

Fig. 4. Proposed method principle

A. Principle

The basic idea consists to obtain the same characteristics, in term of errors, on each T IADC channel. This will be performed using theLMS adaptive filter. To apply theLMS algorithm to two T IADC channels, one ADC output was taken as reference signal (desired signal) and the other one was the signal to be filtered. As shown in figure 4, theADC2 output will converge to ADC1 output. With an appropriate filter order and step-size, the difference betweenADCoutputs converges to zero. Thus, the dissimilarities between ADC characteristics are reduced and consequently mismatch errors between different channels. Interpolation bloc in figure 4 is used to synchronizeADC outputs. To smooth output discon- tinuities, the interpolation method was a cosine one.D1 and D2were two delays to compensate respectively interpolation and filtering times.

B. Spcifications

To model an LMS filter we have to fixe essentially two parameters : the step size and the filter order, [11]. The step

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0 0.2 0.4 0.6 0.8 1

0 10 20 30 40 50 60 70 80 90 100

Adaptation step

Adaptation time (µs)

8 order filter 10 order filter 12 order filter

Fig. 5. Adaptation time evolution

size is limited by the following equation [11]:

0< µ < 2

Mσ_x² (2)

where σ_x² represents input signal power and M is the filter order. Note that µ is a multiplicative constant applied to the signal to be filtered u(n). To make a material description of the solution proposed, all constants should be written with a signed binary notation. In order to reduce the circuit consumption, constants will be written as 2^l integer. Since µ <1, the multiplication will be replaced by a binary division (right shifts).

The u(n) vector bit width is equal to the ADC resolution.

Consequently, µ will be coded on N −1 constant vector.

For an8bit converter resolution, simulation results show that there will be stability problems and a high calibration time for µ < 0.25 figure 5. For 0.25 ≤µ ≤ 1, the calibration times are nearly identical. The calibration time quoted in figure 5 is the CPU time (on Sun ultra 5 station) required for filter coefficient convergence with the same simulation parameters used in section III. Consequently, the filter order is limited by the next equation:

4√ 2

A < M < 2^N⁻¹²

A (3)

For ADC resolution between 8 and 12, LMS filter order is set to 8.

AfterLMS calibration, output spectrum is shown in figure 6. Compared to spectrum of figure 3, offset mismatch components are eliminated and gain and timing mismatch component magnitudes are reduced by 20dB.

C. Improvements

1) Case of non stationary signals: T IADCis used in many applications especially in communication systems. Signal in radio receivers are generally non stationary. When the input signal frequency changes, theLMSfilter adapts coefficients to

0 0.1 0.2 0.3 0.4 0.5

−100

−80

−60

−40

−20 0

Normalized frequency

Magnitude (dB)

Fig. 6. Output spectrum after calibration

correct mismatching errors. After the first steady state, if there is an abrupt frequency change, the system diverge. In fact, convergence time and step size parameters depend on signal energy. For non stationary signal case, this energy changes but the step size is constant. NormalizedLMS (NLMS) filter is the solution to cope with non stationary signal effect. Filter coefficients are updated with the following relation

H(n+ 1) =H(n) + µ

P(X)X(n+ 1)e(n+ 1) (4) Where P(X) is the input signal power and H is the filter coefficient vector.

2) Speed improvement: The architecture proposed shown in figure 4, is modeled usingV HDL−AMS(Analog and Mixed Signal) language [12]. The post-digital correction part formed by an eighth order NLMS filter and a cosine interpolation blocks is implemented on a VirtexIIPro XC2VP30 using ISE software. The estimated maximum frequency is about 73.866MHz. But, the main objective ofT IADCis to increase the sample rate . This fact constitutes the main inconvenient of our method. To overcome the filter sampling rate problem, we use the DelayedLMS (DLMS)[13], which consists of a linear array of identical PM (processing modules) specifically suited to the computational requirements of the delayedLMS algorithm. The resulting adaptive filter structure can accom- modate very high sampling rates, which are independent of the filter order. Filter coefficients of DLMS algorithm are updated with the following relation

H(n+ 1) =H(n) +µX(n+ 1−D)e(n+ 1−D) (5) The main difference with LMS filter consists on delay element insertions (D is the number of delay element) into error feedback vector. These elements provide a parallel structure.

For non stationary signals, the step sizeµof equation 5 is di- vided by signal energy. The resulting filer is calledNDLMS (Normalized Delayed LMS), [14]. The estimated maximum frequency using the sameF P GAis about 114.129MHz. The SF DRis increased by 20 dB for an eighth bit converter.

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Family Circuit Slices Flip Flop LUT DSP Frequency Slice percentage

Spartan2 Xilinx XC2S200 1421 626 2572 - 86.283MHz 19%

Spartan3 Xilinx XC3S4000 1346 630 2156 - 89.461MHz 19%

Virtex Xilinx XCV800 1471 626 2572 - 86.21MHz 21%

Virtex2PRO Xilinx XC2VP30 1346 630 2157 - 114.505MHz 9%

Virtex4 Xilinx XC4VFX140 346 627 146 16 162.41MHz 3%

Virtex5 Xilinx XC5VLX330t 622 - 162 16 177.73MHz 5%

Virtex2PRO Xilinx XC2VP30 1346 630 2157 - 114.505MHz 9%

Virtex4 Xilinx XC4VFX140 346 627 146 16 162.41MHz 3%

Virtex5 Xilinx XC5VLX330t 622 - 162 16 177.73MHz 5%

Cyclone Altra EP1C4F324 3056 630 2720 - – 31%

Stratix2 Altra EP1C4F324 – 630 298 24 – 2%

TABLE I

F P GACONSUMED RESSOURCES

0 2 4 6 8 10 12

40 60 80 100 120 140 160

Filter order

Maximum frequency (MHz)

Correction with NDLMS Correction with LMS

Fig. 7. Maximum frequency evolution after synthesis

IV. F P GAIMPLEMENTATION

The proposed solution, formed by theDLMSadaptive filter and cosine interpolation block, is synthesized into F P GA components. The proposed solution is implemented into dif- ferentF P GAfamilies and technologies to be able to make a global analysis of area consumption. To optimize the design speed, all multiplier are synthesized as F P GA embedded blocks. Table I details different F P GA consumed resources.

Slices consumption is given with the circuit percentage to show theF P GAarea occupation ratio. Implementation results show that the design speed improvement depends on target technology. Moreover, theoretically, this speed is independent for the filter order in case of DLMS filter. The DLMS filter output computation in parallel structure is distributed on different Processor Module contrary to the LMS case. Fig.7 shows the maximum frequency evolution for the proposed correction method with LMS and DLMS structures using a Virtex2 target. The maximum speed decreases as the filter order increase in LMS case. However, thanks to DLMS parallel structure, the maximum frequency is constant.

V. CONCLUSION

This paper deals with new online adaptive calibration method for T IADC. We propose a solution based on min- imizing quadratic error algorithms. A debate is done to show the advantages of NDLMS filter. The proposed solution, formed by an adaptive filter and cosine interpolation bloc, is synthesized into Xilinx F P GA component. As future work, a test bench will be made to test the proposed solution.

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